This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2014-224587, filed on Nov. 4, 2014, the entire contents of which are incorporated herein by reference.
The technique disclosed herein relates to a power source circuit, an electronic circuit, and an integrated circuit.
A processing circuit, such as a CPU core logic circuit, an analog circuit, an I/O circuit, and an interface circuit, operates by receiving supply of power source. The supply of power includes the case where a necessary power source is supplied from the outside to a power source terminal provided in an integrated circuit (IC) chip mounting a processing circuit and the case where an external power source is supplied to a power source circuit mounted on an IC chip via a power source terminal and the power source circuit generates a power source for the processing circuit. Such a power source circuit is referred to as a regulator.
For example, implementing a processing system is performed by mounting a plurality of processing circuits, such as a CPU core logic circuit, an analog circuit, an I/O circuit, and an interface circuit, on one board (printed circuit board). In one configuration, a power source circuit that generates various direct-current (DC) power sources required in a plurality of processing circuits from an electric light line (AC power source) is provided outside the board and a plurality of power sources is supplied to a plurality of power source terminals of the board from the power source circuit. In another configuration, the power source circuit is mounted on a board and the AC power source is supplied to the board from the electric light line.
There is a case where the power sources that are supplied to a plurality of processing circuits differ not only in power source voltage but also in power source quality. For example, the power source of the CPU core logic circuit and the analog circuit has a voltage of 1.2 V, the power source of the I/O circuit has a voltage of 3.3 V, and the power source of the high-speed interface circuit has a voltage of 1.8 V. The power source of the CPU core logic circuit and the analog circuit has the same voltage, i.e., 1.2 V, but it is desirable that the power source of the analog circuit be a power source with less ripples and have good voltage stability, while the power source of the CPU core logic circuit accepts comparatively low voltage stability. Consequently, the power source circuit generates a low-voltage DC power source, such as 3.3 V, from the AC power source by using a step-down circuit or a switching power source circuit that utilizes a transformer, and generates a base DC power source with good voltage stability by utilizing a large-capacity capacitance element or the like. The power source that is supplied to the CPU core logic circuit is generated by a switching regulator from the base DC power source and the power sources of the analog circuit and the high-speed interface circuit are generated by a linear regulator, respectively, and the power source of the I/O circuit is supplied as it is.
In recent years, a system on a chip (SoC) is being widely used, in which a processing system is implemented by one IC chip by mounting a plurality of processing circuits, such as a CPU core logic circuit, an analog circuit, an I/O circuit, and an interface circuit, on one IC chip. The case of the SoC also includes the case where each of a plurality of power sources is supplied from the outside to a plurality of processing circuits and the case where the base DC power source is supplied to the SoC and various regulators are provided within the SoC. It is common to connect an inductance element (coil) and a capacitance element (capacitor) that are used in a switching regulator to the IC chip as discrete parts, but there is a case where the inductance element and the capacitance element are mounted on the SoC.
In embodiments explained below, a case is explained as an example where a regulator is mounted on a board or IC chip and a base DC power source is supplied to the regulator of the board or IC chip.
There is a case where a high voltage is applied to the power source line due to static electricity though the application time is short, and if such a high voltage is applied, there is a possibility that a failure will occur in the regulator and in the processing circuit to which the base DC power source is supplied even though the application time is short. Consequently, an electrostatic discharge (ESD) protection circuit is provided in the power source line.
In the case where the regulator is mounted on the board or IC chip and the base DC power source is supplied to the regulator of the board or IC chip, the ESD protection circuit is provided in the vicinity of the terminal of the board or IC chip, to which the base DC power source is supplied.
In a general ESD protection circuit, a transistor is connected between a high potential side power source line and a low potential side power source line of a power source and a control is performed so that the transistor turns off when the power source is turned on and during the normal time and when a surge voltage due to static electricity is applied, the transistor turns on temporarily. Due to this, a high voltage is prevented from being applied to a circuit element connected between the high potential side power source line and the low potential side power source line for a predetermined period of time or longer when a surge voltage is applied. In order to perform such control of the transistor, a time constant circuit that utilizes a resistor and a capacitance element is used and the ESD protection circuit returns to the normal state after discharging the surge voltage.
[Patent Document 1] Japanese Laid Open Patent Publication No. 2005-64374
According to a first aspect of embodiments, a power source circuit includes: a P-type transistor one of a source and a drain of which is connected to a first power source line and the other of the source and the drain of which is connected to an output node; a resistor connected between a back gate of the P-type transistor and the first power source line; and a capacitance element connected to the back gate of the P-type transistor and to a second power source line having a potential lower than a potential of the first power source line.
According to a second aspect of embodiments, an electronic circuit includes: a processing circuit; and
a power source circuit which supplies a power source voltage to the processing circuit, wherein the power source circuit includes: a P-type transistor one of a source and a drain of which is connected to a first power source line and the other of the source and the drain of which is connected to an output node; a resistor connected between a back gate of the P-type transistor and the first power source line; and a capacitance element connected to the back gate of the P-type transistor and to a second power source line having a potential lower than a potential of the first power source line.
According to a third aspect of embodiments, an integrated circuit includes: a plurality of processing circuits; and a plurality of regulators that supply a power source voltage to each of the plurality of processing circuits, wherein each of the plurality of regulators includes: a transistor one of nodes of which is connected to a power source line and the other node of which is connected to an output node from which the power source voltage is output; and an ESD protection circuit that temporarily brings the transistor into conduction when a surge voltage is applied to the power source line.
The object and advantages of the embodiments will be realized and attained by means of the elements and combination particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.
Before explaining data holding circuits of the embodiments, a general data holding circuit will be explained.
A base power source that is supplied to a linear regulator is a power source with less ripples and good voltage stability. The linear regulator in
The resistor R1 and the capacitance element C1 are connected in parallel between VDD and GND. In other words, PMOS1 and R1 are connected in series between VCC and GND. The reference voltage source 11 is a circuit that is connected between VCC and GND and generates a reference voltage by a band gap reference or the like. The error amplifier 12 generates a control signal that is applied to the gate of PMOS1 by comparing the voltage in a specific position of the resistor R1 with the reference voltage. In accordance with the control signal, the resistance value of PMOS1 changes. The voltage in the specific position of the resistor R1 has a voltage value that is obtained by dividing the voltage between VDD and GND by a resistor and is proportional to VDD. The error amplifier 12 generates the control signal so that the difference between the voltage and the reference voltage becomes zero, and therefore, VDD becomes a desired voltage at all times. The capacitance element C1 is provided in order to stabilize VDD. The linear regulator is widely known, and therefore, more explanation is omitted.
As described above, the linear regulator is a circuit that steps down VCC to VDD by the resistance component of PMOS1 and if VCC is a power source with good voltage stability, the voltage stability of VDD is also good, but power is consumed by the resistance component of PMOS1, and therefore, efficiency is low. Because of this, the linear regulator is used as a regulator of an analog circuit, a high-speed interface circuit, etc., whose power consumption is comparatively small but for which high voltage stability is required. In the case where the linear regulator in
The switching regulator has a reference voltage source 21, an error amplifier 22, an oscillation circuit 23, a control circuit 24, a PMOS transistor PMOS2, an NMOS transistor NMOS2, a coil (inductance element) L2, and a capacitance element C2. PMOS2 and NMOS2 are connected in series between VCC and GND and to the gates, a switching signal from the control circuit 24 is applied and PMOS2 and NMOS2 turn on and off in accordance with the switching signal. A connection node LX of PMOS2 and NMOS2 is connected to VDD via the coil L2. The capacitance element C2 is connected between VDD and GND.
The reference voltage source 21 generates a reference voltage like the reference voltage source 11 in
The efficiency of the switching regulator is higher than that of the linear regulator because a loss due to the resistance component is less, but the voltage stability is lower than that of the linear regulator because ripples accompanying switching are generated in VDD. Because of this, the switching regulator is used as a regulator of a CPU core logic circuit or the like whose power consumption is large and for which high voltage stability is not required.
As described previously, in the power source line, the ESD (Electro-Static Discharge) protection circuit for protecting the circuit from a surge voltage due to static electricity is provided.
As illustrated in
The linear regulator (LDO) 10 has the same configuration as that of the linear regulator in
In the normal state of the ESD protection circuit 30, the voltage of the C point is VCC, the output (voltage of a D point) of Inv1 is the L level, and NMOS10 is in the turned-off state. This is the same also in the case where VCC increases gradually when the power source is turned on and NMOS10 is in the turned-off state. If a positive surge voltage is applied to VCC in the state where the power source VCC is not applied, VCC increases instantaneously, but an increase in voltage of the C point is delayed due to the resistor R10. The power source of Inv1 is VCC and GND and the increase in voltage of the C point is delayed, and therefore, the input of Inv1 relatively turns to the L level, the output (voltage of the D point) of Inv1 turns to the H level, and NMOS10 turns on. Due to this, VDD and GND are brought into conduction and the voltage of VCC having increased instantaneously drops, and thereby, the surge voltage is absorbed. When the power source is turned on after the application of such a surge voltage, NOMOS10 turns off as described above, and therefore, the normal state is brought about.
On the other hand, if a positive surge voltage is applied to VCC in the state where the power source VCC is applied, as in the above, NMOS10 turns on and the surge voltage is absorbed. After that, if the voltage of VCC increases, current flows to the capacitance element C10 via the resistor R10 and charges C10, and therefore, the voltage of the C point increases. The charging speed is determined by a time constant determined by the resistance value of the resistor R10 and the capacitance value of the capacitance element C10. Further, by NMOS10 turning on, the increased voltage of VDD also drops, and therefore, the input of Inv1 relatively turns to the H level, the level of the D point turns to L, and NMOS10 turns off, and thereby, the original state is returned. As above, the ESD protection circuit 30 protects the linear regulator (LDO) 10 from a surge voltage by absorbing the influence of the surge voltage.
As illustrated in
The switching regulator 20 has the same configuration as that of the linear regulator in
The ESD protection circuit illustrated in
In the embodiment explained below, a power source circuit having an ESD protection circuit with a small area is disclosed.
As illustrated in
PMOS1 and the resistors R11 and R12 are connected in series between VCC and GND. A connection node (A point) of PMOS1 and R11 is the output node and when in use, the capacitance element C1 (not illustrated) in
The linear regulator of the first embodiment differs from the linear regulator in
As illustrated in
In the linear regulator of the first embodiment, in the normal state, the voltage of a B point is VCC and to the back gate of PMOS1, VCC is applied. This state is the same as the state in
If a positive surge voltage is applied to VCC in the state where the power source VCC is not applied, VCC increases instantaneously, a current that charges the capacitance element C31 flows through the resistor R31, a difference in voltage occurs between VCC and the B point, and a current is generated between the emitter and base of the parasitic transistor pnp1. Due to this current, pnp1 turns on, a current flows between the emitter and collector, i.e., between the high potential side power source line VCC and the low potential side power source line GND, the voltage of VCC drops, and thereby, the surge voltage is absorbed. When the power source is turned on after the application of such a surge voltage, the voltage of the B point becomes VCC as described above, and therefore, the normal state is brought about.
If a positive surge voltage is applied to VCC in the state where the power source VCC is applied, as in the above, a difference in voltage occurs between VCC and the B point, pnp1 turns on, and thereby, the surge voltage is absorbed. At the same time, if the voltage of VCC increases, current flows to the capacitance element C31 via the resistor R31 and charges C31, and the voltage of the B point increases. The charging speed is determined by a time constant determined by the resistance value of the resistor R31 and the capacitance value of the capacitance element C31. Further, when pnp1 turns on, the increased voltage of VDD also drops, and therefore, the level of the B point becomes close to VCC, pnp1 turns off, and the normal operation state is returned. The linear regulator of the first embodiment prevents VCC from increasing considerably by absorbing the influence of the surge voltage as described above. In other words, the linear regulator of the first embodiment implements the ESD protection circuit by making use of PMOS1 and adding R31 and C31.
Consequently, it is not necessary to separately provide the ESD protection circuit 30 as in
In the above-described explanation, the case is explained where a positive surge voltage is applied to VCC, and the case where a negative surge voltage is applied to VCC will be described later.
As illustrated in
With the above structure, a parasitic transistor npn1 is formed between the B point and GND by the N well, the P-type substrate (Psub), and the N well (Nwell) 16 as indicated by a broken line. A resistor R15 is a resistance component between the P-type substrate and GND.
As illustrated in
In the linear regulator of the first embodiment, by turning on the parasitic transistor pnp1, the surge voltage of VCC is discharged to GND, but the parasitic transistor pnp1 has a small amplification factor hfe and is not large enough to discharge the surge voltage in a brief time. In order for the linear regulator to resist a large surge voltage, it is required to increase the size of the parasitic transistor pnp1, i.e., to increase the size of PMOS1.
In contrast to this, in the linear regulator of the second embodiment, it is possible to cause a large current to flow by the thyristor operation, and therefore, it is not necessary to increase the size of PMOS1.
As illustrated in
During the normal operation during which VCC is applied, the C point is the H level, PMOS41 is in the turned-on (ON) state, the drain of PMOS41 outputs VCC, and this is applied to the B point at VCC.
As illustrated during the ESD test in
As illustrated during the normal operation (during which the power source is turned on) in
During the normal operation during which VCC is supplied, if a surge voltage is applied to the power source line VCC, as described above, the voltage of the B point increases, pnp1 and npn1 turn on, and a large current resulting from the surge voltage is discharged to GND by the thyristor structure. When the thyristor structure turns on once, the thyristor structure enters the latch-up state where the on state is maintained even if VCC drops. On the other hand, the voltage of the C point increases gradually because the time constant determined by R41 and C41 is long, and exceeds the threshold value of Inv41, and the output of Inv41 turns to the L level, and PMOS41 turns on. Due to this, the B point enters the state of being connected to VCC and pnp1 turns off, and therefore, npn1 also turns off. In this manner, the thyristor structure in the latch-up state is turned off forcibly.
As explained above, in the linear regulator of the third embodiment, the thyristor structure formed by two parasitic transistors is forcibly turned off even if the thyristor structure latches up due to the application of a surge voltage. Due to this, it is possible for the thyristor structure to turn on only when absorbing a surge voltage and to prevent the destruction of the element (PMOS1) caused by an overcurrent due to the latch-up state continuing to flow.
In the first to third embodiments, the case is explained where a positive surge voltage is applied to the high potential side power source line VCC, but there may be a case where a negative surge voltage is applied to the high potential side power source line VCC. That the linear regulators in the first to third embodiments will operate normally even in such a case is explained by taking the third embodiment as an example.
The switching regulator of the fourth embodiment has the portion 22A including the reference voltage source 21, the resistors R21 to R23, and the capacitance element C21, the amplifier 22B, the PWM amplifier 24A, and the control unit 24B. The switching regulator of the fourth embodiment further has the PMOS transistor PMOS2, the NMOS transistor NMOS2, the coil (inductance element) L2, and the capacitance element C2. The above configuration is the same as that of the switching regulator 20 illustrated in
The switching regulator of the fourth embodiment has a resistor R51 connected between the high potential side power source line VCC and the back gate of PMOS2, and a capacitance element C51 connected between the back gate of PMOS2 and the low potential side power source line GND.
The operations of the portions except for the resistor R51 and the capacitance element C51 are the same as those of the switching regulator 20 in
In the fourth embodiment, PMOS2 of the switching regulator has an element structure as illustrated in
In the normal state, the voltage of the B point is VCC and to the back gate of PMOS2, VCC is applied. This is the same as the state in
If a positive surge voltage is applied to VCC in the state where the power source VCC is not applied, VCC increases instantaneously, a current that charges the capacitance element C51 flows through the resistor R51, a difference in voltage between VCC and the B point occurs, and a current is generated between the emitter and base of pnp1. Due to this current, pnp1 turns on, a current flows between the emitter and collector, i.e., between the high potential side power source line VCC and the low potential side power source line GND, the voltage of VCC drops, and thereby, the surge voltage is absorbed. When the power source is turned on after the application of such a surge voltage, as described above, the voltage of the B point becomes VCC, and therefore, the normal state is brought about.
If a positive surge voltage is applied to VCC in the state where the power source VCC is applied, as in the above, a difference in voltage between VCC and the B point occurs, the pnp transistor turns on, and thereby, the surge voltage is absorbed. At the same time, after it is determined by the time constant determined by the resistance value of the resistor R51 and the capacitance value of the capacitance element C51, the level of the B point becomes close to VCC, pnp1 turns off, and the normal operation state is returned.
The switching regulator of the fourth embodiment absorbs the influence of a surge voltage as above and prevents VCC from increasing considerably. In other words, the switching regulator of the fourth embodiment implements the ESD protection circuit by making use of PMOS2 and adding R51 and C51.
Consequently, it is not necessary to separately provide the ESD protection circuit 30 as in
The switching regulator of the fifth embodiment has the same circuit configuration as that of the fourth embodiment. However, in the fifth embodiment, as in the second embodiment, the guard ring ISO is provided around the N well (Nwell) in which PMOS2 is formed and the guard ring ISO is also provided around at least part of the N well (Nwell) around the guard ring ISO. In other words, the N well guard ring is formed in PMOS2.
The switching regulator of the fifth embodiment implements the ESD protection circuit having a thyristor structure by the parasitic transistors pnp1 and npn1 by making use of PMOS2, adding R51 and C51, and forming the N well guard ring in PMOS2.
The operation as the switching regulator is the same as that of the switching regulator of the first embodiment in
The switching regulator of the sixth embodiment differs from the linear regulator of the fifth embodiment in that a latch-up recovery circuit including the resistor R41, the capacitance element C41, the inverter Inv41, and the P-type MOS transistor PMOS41 is added.
The configuration and operation of the latch-up recovery circuit are the same as those of the third embodiment and it is possible to prevent the destruction of the element (PMOS2) caused by an overcurrent due to the latch-up state continuing to flow by forcibly turning off the thyristor structure even if it latches up due to the application of a surge voltage.
As above, the first to sixth embodiments are explained and next, an example of the SoC that uses the linear regulator of the first to third embodiments and the switching regulator of the fourth to sixth embodiments is explained.
As illustrated in
As a result, the number of power source terminals and the number of kinds of power source terminals that are provided in the SoC increase, and therefore, the number of pins increases, and that the wiring of the power sources from the external power source circuits up to the SoC becomes complicated.
Consequently, as illustrated in
In the case where the ESD protection circuit 30 illustrated in
In contrast, if the switching regulator 201 is implemented by the switching regulator of the fourth to sixth embodiments and the linear regulators 202 and 203 are implemented by the linear regulator of the first to third embodiments, it is not necessary to separately provide the ESD protection circuit. Therefore, it is possible to suppress an increase in the chip area of the SoC 200.
All examples and conditional language provided herein are intended for pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a illustrating of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Number | Date | Country | Kind |
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2014-224587 | Nov 2014 | JP | national |