Patent Application
20130099568
1. Technical Field
The present disclosure relates to a power supply circuit for memory slots.
2. Description of Related Art
In general, a Sandy Bridge-EP central processing unit (CPU) is mounted between two groups of memory slots, and each group of the memory slots is controlled by a power supply controller. When the CPU operates, the memory slots operate simultaneously. Even if all the memory slots of a group are unoccupied, a memory power supply still provides a voltage to the idle memory slots through the corresponding memory power controller, which wastes energy.
Many aspects of the embodiments can be better understood with reference to the following drawing. The components in the drawing are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments.
The FIGURE is a circuit diagram of an exemplary embodiment of a power supply circuit.
The disclosure, including the accompanying drawing, is illustrated by way of example and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.
Referring to the FIGURE, a power supply circuit 100 is configured for providing a voltage to a memory slot group 90. An exemplary embodiment of the circuit 100 includes a platform controller hub (PCH) 60, a basic input/output system (BIOS) 50, a control circuit 70, and a power supply 80. The slot group 90 includes a plurality of memory slots 40, each of which is connected to a data terminal SDA and a clock terminal SCL of the PCH 60 through a system management bus (SMBUS). The slots 40 can receive memory chips (not shown).
The PCH 60 detects whether any of the slots 40 are occupied by a memory chip, and notifies the BIOS 50 if there are. If there are any slots 40 occupied by a memory chip the BIOS 50 enables a general purpose input/output (GPIO) terminal of the PCH 60.
The control circuit 70 includes an integrated circuit (IC) chip 75, metal-oxide-semiconductor field-effect transistors (MOSFETs) M1 and M2, an inductor L, resistors R1 and R2, and a capacitor C. An enable terminal EN of the IC chip 75 is connected to the GPIO terminal. A gate of the MOSFET M1 is connected to a signal terminal S1 of the IC chip 75, and a gate of the MOSFET M2 is connected to a signal terminal S2 of the IC chip 75. A drain of the MOSFET M1 is connected to the power supply 80. A source of the MOSFET M1 is connected to a drain of the MOSFET M2. The source of the MOSFET M1 is further grounded through the inductor L, the resistor R1, the capacitor C, and the resistor R2 connected in series. A node between the resistor R1 and the capacitor C is connected to all the memory slots 40. A source of the MOSFET M2 is grounded.
The control circuit 70 controls the power supply 80 to output or not output a voltage to the memory slot group 90 based on whether the GPIO terminal is enabled, which in turn enables the terminal EN. In this embodiment, when the terminal EN is not enabled, the control circuit 70 controls the power supply 80 to stop outputting a voltage to the slot group 90, and when the terminal EN is enabled, the control circuit 70 controls the power supply 80 to periodically output a voltage to the slot group 90 and to the inductor L and capacitor C.
In use, the PCH 60 detects whether the memory slots 40 are idle through the SMBUS. If the PCH 60 detects all the memory slots 40 are unoccupied, the PCH 60 sends a detection result to the BIOS 50. Based on the received detection result, the BIOS 50 does not enable the GPIO terminal, and no power is output by the power supply 80 because the IC chip 75 turns off the MOSFETs M1 and M2.
If the PCH 60 detects one or more memory chips are inserted in the memory slots 40, the BIOS 50 enables the output GPIO terminal which then outputs a high-level signal enabling the terminal EN. The signal terminals S1 and S2 alternately output a high-level signal. In detail, the IC chip 75 outputs a high-level signal to the MOSFET M1 through the signal terminal S1, and outputs a low-level signal to the MOSFET M2 through the signal terminal S2, thereby turning on the MOSFET M1 and turning off the MOSFET M2. The power supply 80 charges the inductor L and the capacitor C while at the same time supplying power to the slot group 90. After the inductor L and the capacitor C are charged, the IC chip 75 outputs a low-level signal to the MOSFET M1 through the signal terminal S1, and outputs a high-level signal to the MOSFET M2 through the signal terminal S2, thereby turning off the MOSFET M1 and turning on the MOSFET M2. The power supply 80 stops providing voltage to the slot group 90, while the inductor L and the capacitor C discharges to provide a voltage to the slot group 90 and then the cycle repeats.
The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible. The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others of ordinary skill in the art to utilize the disclosure and various embodiments and with such various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those of ordinary skills in the art to which the present disclosure pertains without departing from its spirit and scope. Accordingly, the scope of the present disclosure is defined by the appended claims rather than by the foregoing description and the exemplary embodiments described therein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201110318410.7 | Oct 2011 | CN | national |
