1. Field
Embodiments described herein relate generally to a power supply circuit.
2. Background Art
A conventional power supply circuit is provided with a regulator to cope with a drop of a power supply voltage. The regulator of the conventional power supply circuit induces an overshot and takes longer to stabilize the output voltage, if the response speed is increased.
A power supply circuit according to an embodiment includes a voltage generating circuit that generates an output voltage responsive to a reference voltage and outputs the output voltage at a voltage output terminal. The power supply circuit includes a power supply-side resistor that receives a power supply-side detection voltage that is based on the output voltage at a first end thereof. The power supply circuit includes a power supply-side capacitor connected to a second end of the power supply-side resistor at a first end thereof and to a ground at a second end thereof. The power supply circuit includes a ground-side resistor connected to the voltage output terminal at a first end thereof. The power supply circuit includes a ground-side capacitor connected to a second end of the ground-side resistor at a first end thereof and to the ground at a second end thereof. The power supply circuit includes a power supply-side amplifier that is connected to the voltage output terminal at a non-inverting input terminal thereof and to the second end of the power supply-side resistor at an inverting input terminal thereof and outputs a power supply-side control signal at an output terminal thereof. The power supply circuit includes a ground-side amplifier that is connected to the second end of the ground-side resistor at a non-inverting input terminal thereof, receives a ground-side detection voltage that is based on the output voltage at an inverting input terminal thereof and outputs a ground-side control signal. The power supply circuit includes a power supply-side switch element that is connected to a power supply at a first end thereof and to the voltage output terminal at a second end thereof and is controlled by the power supply-side control signal. The power supply circuit includes a ground-side switch element that is connected to the voltage output terminal at a first end thereof and to the ground at a second end thereof and is controlled by the ground-side control signal.
In the following, an embodiment will be described with reference to the drawings.
As shown in
The voltage generating circuit “VC” generates an output voltage “VOUT” responsive to a reference voltage “VREF” and outputs the output voltage “VOUT” at a voltage output terminal “TOUT”.
The voltage generating circuit “VC” has a first pMOS transistor “PG1”, a second pMOS transistor “PG2”, a first nMOS transistor “NG1”, a second nMOS transistor “NG2”, a third nMOS transistor “NG3”, a fourth nMOS transistor “NG4”, a fifth nMOS transistor “NG5” and an output resistor “RO”.
The first pMOS transistor “PG1” is connected to a power supply “VDD” at a source thereof and is diode-connected.
The second pMOS transistor “PG2” is connected to the power supply “VDD” at a source thereof and to a gate of the pMOS transistor “PG1” at a gate thereof.
The first nMOS transistor “NG1” is connected to a drain of the first pMOS transistor “PG1” at a drain thereof and to a reference voltage terminal “TREF”, to which the reference voltage “VREF” is applied, at a gate thereof.
The second nMOS transistor “NG2” is connected to a drain of the second pMOS transistor “PG2” at a drain thereof and to a source of the first nMOS transistor at a source thereof.
The third nMOS transistor “NG3” is connected to the source of the first nMOS transistor “NG1” at a drain thereof. The third nMOS transistor “NG3” is configured so that a predetermined voltage is applied to a gate thereof, and a predetermined current flows therethrough.
The fourth nMOS transistor “NG4” is connected between a source of the third nMOS transistor “NG3” and a ground and is configured to receive a signal that controls turning on and off thereof at a gate thereof.
The output resistor “RO” is connected between a gate of the second nMOS transistor “NG2” and the voltage output terminal “TOUT”.
The fifth nMOS transistor “NG5” is connected to the power supply “VDD” at a drain thereof and to the voltage output terminal “TOUT” at a source thereof.
The power supply-side voltage dividing circuit “DU” is connected between the voltage output terminal “TOUT” and the ground and is configured to output a power supply-side detection voltage “V1” obtained by dividing the output voltage “VOUT”.
As shown in
The ground-side voltage dividing circuit “DD” is connected between the voltage output terminal “TOUT” and the ground and is configured to output a ground-side detection voltage “V2” obtained by dividing the output voltage “VOUT”.
As shown in
The voltage division ratio of the power supply-side voltage dividing circuit “DU” is set to be equal to the voltage division ratio of the ground-side voltage dividing circuit “DD”, for example.
The power supply-side detection voltage “V1” and the ground-side detection voltage “V2” are set to be lower than the output voltage “VOUT”, for example.
The power supply-side resistor “RU” is connected to an output of the power supply-side voltage dividing circuit “DU” (the another end of the first power supply-side voltage dividing resistor “R1”) at one end thereof, for example. That is, the power supply-side resistor “RU” receives the power supply-side detection voltage “V1” that is based on the output voltage “VOUT” at the one end thereof.
The power supply-side capacitor “CU” is connected to another end of the power supply-side resistor “RU” at one end thereof and to the ground at another end thereof.
The ground-side resistor “RD” is connected to the voltage output terminal “TOUT” at one end thereof.
The resistance of the power supply-side resistor “RU” is set to be equal to the resistance of the ground-side resistor “RD”, for example.
The ground-side capacitor “CD” is connected to another end of the ground-side resistor “RD” at one end thereof and to the ground at another end thereof.
The capacitance of the power supply-side capacitor “CU” is set to be equal to the capacitance of the ground-side capacitor “CD”.
Since the resistance of the power supply-side resistor “RU” is set to be equal to the resistance of the ground-side resistor “RD”, and the capacitor of the power supply-side capacitor “CU” is set to be equal to the capacitance of the ground-side capacitor “CD” as described above, a pull-up phase and a pull-down phase can be aligned with each other, and a through-current can be suppressed. However, depending on the characteristics required by the design, the resistance of the power supply-side resistor “RU” and the resistance of the ground-side resistor “RD” can be set to be different, and the capacitance of the power supply-side capacitor “CU” and the capacitance of the ground-side capacitor “CD” can be set to be different so that the pull-up phase and the pull-down phase differs from each other.
The power supply-side amplifier “AU” is connected to the voltage output terminal “TOUT” at a non-inverting input terminal thereof and to another end of the power supply-side resistor “RU” at an inverting input terminal thereof and outputs a power supply-side control signal “SU” at an output terminal “TU” thereof.
As shown in
The first power supply-side pMOS transistor “PU1” is connected to the power supply “VDD” at a source thereof and is diode-connected.
The second power supply-side pMOS transistor “PU2” is connected to the power supply “VDD” at a source thereof and to a gate of the first power supply-side pMOS transistor “PU1” at a gate thereof.
The first power supply-side nMOS transistor “NU1” is connected to a drain of the first power supply-side pMOS transistor “PU1” at a drain thereof and to the inverting input terminal of the power supply-side amplifier “AU” at a gate thereof.
The second power supply-side nMOS transistor “NU2” is connected to a drain of the second power supply-side pMOS transistor “PU2” at a drain thereof, to a source of the first power supply-side nMOS transistor “NU1” at a source thereof and to the non-inverting input terminal of the power supply-side amplifier “AU” at a gate thereof.
The third power supply-side nMOS transistor “NU3” is connected to the source of the first power supply-side nMOS transistor “NU1” at a drain thereof. The third power supply-side nMOS transistor “NU3” is configured so that a predetermined voltage is applied to a gate thereof, and a predetermined current flows therethrough.
The fourth power supply-side nMOS transistor “NU4” is connected between a source of the third power supply-side nMOS transistor “NU3” and the ground and is configured to receive a signal that controls turning on and off thereof at a gate thereof. In operation of the power supply-side amplifier “AU”, the fourth power supply-side nMOS transistor “NU4” is controlled to be in an on state.
The third power supply-side pMOS transistor “PU3” is connected to the power supply “VDD” at a source thereof, to the output terminal “TU” of the power supply-side amplifier “AU” at a drain thereof and to the drain of the second power supply-side pMOS transistor “PU2” at a gate thereof.
The fifth power supply-side nMOS transistor “NU5” is connected to the ground at a source thereof, to the output terminal “TU” of the power supply-side amplifier “AU” at a drain thereof and to the gate of the third power supply-side nMOS transistor “NU3” at a gate thereof.
The power supply-side gate driver “GU” controls the power supply-side switch element “SWU” with a signal “UG” in response to the power supply-side control signal “SU”.
As shown in
The first power supply-side inverter “IU1” is connected to the output terminal “TU” of the power supply-side amplifier “AU” at an input thereof.
The second power supply-side inverter “IU2” is connected to an output of the first power supply-side inverter “IU1” at an input thereof and to a gate of a pMOS transistor (power supply-side switch element “SWU”) at an output thereof.
The ground-side amplifier “AD” is connected to another end of the ground-side resistor “RD” at a non-inverting input terminal thereof, receives the ground-side detection voltage “V2” that is based on the output voltage “VOUT” at the inverting input terminal thereof, and outputs a ground-side control signal “SD” at an output terminal “TD” thereof.
As shown in
The first ground-side pMOS transistor “PD1” is connected to the power supply “VDD” at a source thereof and is diode-connected.
The second ground-side pMOS transistor “PD2” is connected to the power supply “VDD” at a source thereof and to a gate of the first ground-side pMOS transistor “PD1” at a gate thereof.
The first ground-side nMOS transistor “ND1” is connected to a drain of the first ground-side pMOS transistor “PD1” at a drain thereof and to the inverting input terminal of the ground-side amplifier “AD” at a gate thereof. In this embodiment, the first ground-side nMOS transistor “ND1” is connected to an output of the ground-side voltage dividing circuit “DD” (the another end of the first ground-side voltage dividing resistor “R3”) at the gate thereof.
The second ground-side nMOS transistor “ND2” is connected to a drain of the second ground-side pMOS transistor “PD2” at a drain thereof, to a source of the first ground-side nMOS transistor “ND1” at a source thereof and to the non-inverting input terminal of the ground-side amplifier “AD” (the one end of the ground-side resistor “RD”) at a gate thereof.
The third ground-side nMOS transistor “ND3” is connected to the source of the first power supply-side nMOS transistor “NU1” at a drain thereof. The third ground-side nMOS transistor “ND3” is configured so that a predetermined voltage is applied to a gate thereof, and a predetermined current flows therethrough.
The third ground-side pMOS transistor “PD3” is connected to the power supply “VDD” at a source thereof, to the output terminal “TD” of the ground-side amplifier “AD” at a drain thereof and to the drain of the second ground-side pMOS transistor “PD2” at a gate thereof.
The fourth ground-side nMOS transistor “ND4” is connected between a source of the third ground-side nMOS transistor “ND3” and the ground and receives a signal that controls turning on and off thereof at a gate thereof. In operation of the ground-side amplifier “AD”, the fourth ground-side nMOS transistor “ND4” is controlled to be in the on state.
The fifth ground-side nMOS transistor “ND5” is connected to the ground at a source thereof, to the output terminal “TD” of the power supply-side amplifier “AU” at a drain thereof and to the gate of the third ground-side nMOS transistor “ND3” at a gate thereof.
The ground-side gate driver “GD” controls a ground-side switch element “SWD” with a signal “DG” in response to the ground-side control signal “SD”.
As shown in
The ground-side inverter “ID” is connected to the output terminal “TD” of the ground-side amplifier “AD” at an input thereof and to a gate of an nMOS transistor (ground-side switch element “SWD”) at an output thereof.
The power supply-side switch element “SWU” is connected to the power supply “VDD” at one end thereof and to the voltage output terminal “TOUT” at another end thereof. The power supply-side switch element “SWU” is turned on and off under the control of the power supply-side control signal “SU” (an output of the power supply-side gate driver “GU”).
As shown in
The ground-side switch element “SWD” is connected to the voltage output terminal “TOUT” at one end thereof and to the ground at another end thereof. The ground-side switch element “SWD” is turned on and off under the control of the ground-side control signal “SD” (an output of the ground-side gate driver “GD”).
As shown in
The capacity of the fifth nMOS transistor “NG5” described above to flow a current is set to be higher than the capacities of the power supply-side switch element “SWU” (a pMOS transistor) and the ground-side switch element “SWD” (an nMOS transistor) to flow a current.
In
Next, an example of an operation of the power supply circuit 100 configured as described above will be described.
As an example, a case where a high current consumption occurs in a load to which the power supply circuit 100 supplies electric power will be first described.
As shown in
If a drop of the output voltage “VOUT” occurs as described above, a gate voltage “G2U” of the second power supply-side nMOS transistor “NU2” in the power supply-side amplifier “AU” first decreases, as shown in
As shown in
The power supply-side amplifier “AU” detects the drop of the output voltage “VOUT” when the level of the gate voltage “G2U”, which is a feedback of the output voltage “VOUT”, decreases below the level of the gate voltage “G1U”, and outputs the power supply-side control signal “SU” responsive to the detection result.
The power supply-side control signal “SU” turns on the power supply-side switch element “SWU”. As a result, the output voltage “VOUT” increases (a drop reducing period).
As shown in
In the case where the drop of the output voltage “VOUT” occurs due to the abrupt increase of the current consumption, the level of a gate voltage “G2D” of the second ground-side nMOS transistor “ND2” also increases, but the increase lags behind the increase of the gate voltage “G1D” of the first ground-side nMOS transistor “ND1” because the phase of the gate voltage “G2D” is shifted by the ground-side resistor “RD” and the ground-side capacitor “CD”.
The ground-side amplifier “AD” detects the recovery operation when the level of the gate voltage “G1D” increases above the level of the gate voltage “G2D”, and outputs the ground-side control signal “SD” responsive to the detection result. The ground-side control signal “SD” turns on the ground-side switch element “SWD”. As a result, an increase of the output voltage “VOUT” is suppressed (a recovery braking period).
In this way, a power supply drop and an overshoot that would otherwise occur when a high current consumption occurs are prevented, and therefore, a ringing is prevented. And an overdrive that would otherwise occur when the high current consumption stops is also prevented.
In particular, if the output voltage “VOUT” has not reached a target level when the recovery braking period ends, the recovery operation starts again. And if an abrupt recovery starts, the ground-side switch element “SWD” brakes the recovery operation.
Thus, the ground-side switch element “SWD” can start operating before the target level is reached. As a result, the recovery operation can be braked, and the output voltage “VOUT” can be slowly brought back to the target level.
As a result, an overcharge can be prevented, a ringing can be prevented, and the time required to recover and stabilize the level of the output voltage “VOUT” having once dropped can be reduced compared with a comparative example (
In addition, the capability of the power supply-side switch element “SWU” can be enhanced, and as a result, a drop of the output voltage “VOUT” can be suppressed.
Next, as an example, a case where a high current consumption of a load to which the power supply circuit 100 supplies electric power stops will be described.
As shown in
When the output voltage “VOUT” increases as described above, the gate voltage “G2U”, which is a feedback of the output voltage “VOUT”, and the gate voltage “G1U” also increase as shown in
Since the magnitude relationship between the gate voltage “G2U” and the gate voltage “G1U” is maintained, the power supply-side amplifier “AU” does not operate, and the level of the power supply-side control signal “SU” is maintained. The power supply-side control signal “SU” keeps the power supply-side switch element “SWU” in an off state.
As shown in
The gate voltage “G2D” of the second ground-side nMOS transistor “ND2” in the ground-side amplifier “AD” also starts increasing, but the increase lags behind the increase of the gate voltage “G1D” of the first ground-side nMOS transistor “ND1” because the phase of the gate voltage “G2D” is shifted by the ground-side resistor “RD” and the ground-side capacitor “CD”.
The ground-side amplifier “AD” detects the recovery operation of the power supply circuit 100 when the level of the gate voltage “G1D” increases above the level of the gate voltage “G2D”, and outputs the ground-side control signal “SD” responsive to the detection result. The ground-side control signal “SD” turns on the ground-side switch element “SWD”. As a result, an increase of the output voltage “VOUT” is suppressed (an overshoot reducing period).
In this way, a drop of the output voltage “VOUT” and an overshoot of the output voltage “VOUT” that would otherwise occur when a high current consumption occurs are prevented, and therefore, a ringing is prevented. And an overdrive that would otherwise occur when the high current consumption stops is also prevented.
Since the output voltage “VOUT” is slowly brought back to the target level as described above, a ringing can be suppressed, and the time required to recover and stabilize the level of the output voltage “VOUT” having once dropped can be reduced.
In particular, as described above, the power supply-side detection voltage “V1” input to the power supply-side amplifier “AU” that detects a drop of the output voltage “VOUT” and the ground-side detection voltage “V2” input to the ground-side amplifier “AD” that detects a recovery are set to be lower than the output voltage “VOUT” (5% or so, for example). Therefore, the power supply-side switch element “SWU” or the ground-side switch element “SWD” can be prevented from being kept in the on state.
As described above, the power supply circuit according to the embodiment can stabilize the output voltage.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
This application is based upon and claims the benefit of U.S. provisional Application No. 61/875,301, filed on Sep. 9, 2013, the entire contents of which are incorporated herein by reference.
Number | Date | Country | |
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61875301 | Sep 2013 | US |