The present disclosure relates to a field of semiconductor manufactures, and more particularly relates to a method of manufacturing a flat cell read-only memory (ROM) device.
In integrated circuits such as a micro control unit (MCU), an application specific integrated circuit (ASIC), and so on, a large area of the flat cell ROM arrays are usually required to store and read various programs and data. In order to improve the reliability of the flat cell ROM circuit, it is necessary to increase a withstand voltage of a device, and to reduce a leakage current and to alleviate a punch through phenomenon. In a conventional manufacturing process, after the fabrication of an N-type region (N-type region serves as a source-drain region of the flat cell ROM device), an additional isolation mask is usually added to perform dopant ion implantation to prevent an occurrence of the punch through phenomenon between a source and a drain, which increases a process cost and difficulty.
Accordingly, it is necessary to provide a method of manufacturing a flat cell ROM device, which can effectively reduce a process cost and a leakage current of a source-drain, and improve a breakdown voltage (BV) of the device.
A method of manufacturing a flat cell ROM device includes the following steps of:
providing a substrate;
forming a P well on the substrate;
forming a photolithography mask layer on the P well and performing photolithography to form an implantation window;
performing P-type ion implantation to the implantation window by using the photolithography mask layer to form a P-type region;
performing N-type ion implantation to the implantation window by using the photolithography mask layer to form an N-type region on the P-type region; wherein the N-type region comprises a first N-type region and a second N-type region; the first N-type region and the second N-type region serve as a source and a drain of the flat cell ROM device, respectively;
forming a gate oxide layer on surfaces of the substrate and the N-type region; and
forming a polysilicon gate on a surface of the gate oxide layer.
According to the aforementioned method of manufacturing the flat cell ROM device, the same photolithography mask layer is used to manufacture the P-type region and the N-type region, so that the P-type region having a higher concentration than the P-well is formed at an interface between the N-type region and the P-well in the device. Therefore, the P-type doping concentration at an interface of a channel region formed by the N-type region and the P well is increased. Thus a barrier height of a p-n junction is increased, thereby reducing the leakage current of the source-drain of the device. Therefore the punch through phenomenon is alleviated, and the withstand voltage of the device is increased. In addition, the N-type region and the P-type region are manufactured by using the same photolithography mask layer, thus there is no need to add additional isolation mask to improve the characteristic of resistance to breakdown of the device, thereby saving a production cost.
In order to illustrate the technical solution of the invention or prior art more clearly, hereinafter, a brief introduction of accompanying drawings employed in the description of the embodiments or the prior art is provided. It is apparent that accompanying drawings described hereinafter merely are several embodiments of the invention. For one skilled in the art, other drawings can be obtained according to the accompanying drawings, without a creative work.
Embodiments of the present disclosure are described more fully hereinafter with reference to the accompanying drawings, in which some embodiments of the present disclosure are shown. The various embodiments of the present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.
In the specification and accompanying drawings, the reference signs N and P assigned to the layers or regions indicate that such layers or regions contains a large number of electrons or holes. Further, reference signs + and − assigned to the N or P indicate that a concentration of dopant is greater or lower than a concentration in the layers without such signs. In the following description and accompanying drawing of the embodiment, similar components aligned similar reference sings and redundant illustration is omitted herein.
In step S110, a substrate is provided.
The substrate can be made of silicon, carborundum, gallium arsenide, and indium phosphide. The resistivity of the substrate can be configured according to a demand of a withstand voltage of the device to be manufactured.
In step S115, a P well is formed on the substrate.
P-type ion implantation is performed on the substrate to form the P well.
In step S120, a photolithography mask layer is formed on the P well and photolithograph is performed to form an implantation window.
In step S130, the P-type ion implantation is performed to the implantation window by using the photolithography mask layer to form a P-type region.
The formed photolithography mask layer is used as a blocking layer to perform the P-type ion implantation to form the P-type region. In the illustrated embodiment, the P-type ion implantation is performed at a tilt angle, i.e., the P-type ion is implanted at a certain angle with respect to a vertical plane. The angle can be 20 to 30 degrees. An implantation depth and region can be controlled by performing the P-type implantation at the certain angle. In the process of the P-type ion implantation, if the P-type ion concentration is too high, avalanche breakdown of the p-n junction may occur, and the BV of the device will be reduced. Therefore, a suitable dose of the P-type ion implantation is required to be selected. Specifically, the implanted P-type ion is boron, and the dose of the implanted P-type ion is 7×1012 cm−2 to 3×1013 cm−2. In an alternative embodiment, the P-type ion can be indium or boron difluoride (BF2).
In step S140, N-type ion implantation is performed to the implantation window by using the photolithography mask layer, so as to form an N-type region on the P-type region.
Specifically, an N+ region is formed in the P-type region by the N-type ion implantation. In the illustrated embodiment, the N-type ion is arsenic, and the N-type ion implantation is performed perpendicular to the surface of the device. In an alternative embodiment, the N-type ion is phosphorus or antimony.
After completing the step of ion implantation, it is also necessary to perform the step of removing the photolithography mask layer and performing a corresponding thermal process. By merits of the proper thermal process via the furnace tube, the P-type impurity can diffuse to the interface of the channel region, therefore the doping concentration of the channel region is increased without affecting the size of the channel. For those skilled in the art, it is a common manufacturing process to accelerate the diffusion of the P-type doping by the thermal process, thus temperature and a length of the time during the thermal process can be selected by those skilled in the art according to the actual requirement.
S150: a gate oxide layer is formed on surfaces of the substrate and the N-type region.
S160: a polysilicon gate is formed on a surface of the gate oxide layer.
After performing the ion implantation, the gate oxide layer and the polysilicon gate are formed by steps S150 and S160, and the corresponding subsequent steps are performed to accomplish the manufacturing process of the device.
According to the aforementioned method of manufacturing the flat cell ROM device, the P-type ion implantation and the N-type ion implantation are performed using the same photolithography mask layer, so that the P-type region having a higher concentration than that of the P-well is formed at an interface between the N-type region and the P-well of the device. Therefore, the P-type doping concentration at an interface between the N-type region and a channel region is increased, a barrier height of a P-N junction is increased, thereby reducing the leakage current of the source-drain of the device. Therefore the punch through phenomenon is alleviated, and the withstand voltage of the device is improved. In addition, the N-type region and the P-type region are manufactured by using the same photolithography mask layer, thus there is no need to add additional isolation mask to improve the characteristic of resistance to breakdown of the device, thereby saving a production cost. The adjustment of the withstand voltage of the device can be achieved by controlling the implantation dose and angle of the implanted P-type ion. In the illustrated embodiment, the implantation dose of the implanted P-type ion is 7×1012 cm−2 to 3×1013 cm−2, and the withstand voltage can be increased by 5V to 8V.
In the illustrated embodiment, by merit of controlling the dose of the ion implantation in the P-type region, the control of the doping concentration of the region can be achieved. Therefore the ability of the withstand voltage of the device and preventing the punch though can be adjusted.
Although the respective embodiments have been described one by one, it shall be appreciated that the respective embodiments will not be isolated. Those skilled in the art can apparently appreciate upon reading the disclosure of this application that the respective technical features involved in the respective embodiments can be combined arbitrarily between the respective embodiments as long as they have no collision with each other. Of course, the respective technical features mentioned in the same embodiment can also be combined arbitrarily as long as they have no collision with each other.
The aforementioned implementations are merely specific embodiments of the present disclosure, but are not intended to limit the protection scope of the present disclosure. It should be noted that persons skilled in the art can understand and embody all or part of flowcharts of the aforementioned implementations. Equivalent variation figured out by persons skilled in the art shall all fall within the protection scope of the present disclosure.
Number | Date | Country | Kind |
---|---|---|---|
201510048123.7 | Jan 2015 | CN | national |
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/CN2015/090375 | 9/23/2015 | WO | 00 |