I. Field of the Disclosure
The technology of the disclosure relates to processing of computer instructions in central processing unit (CPU)-based systems.
II Background
The universe of instructions that can be executed by a central processing unit (CPU) of a computer is defined by an “instruction set architecture,” such as the ARM architecture. The instruction set architecture specifies the semantics of all legal encodings of instructions and arguments in the instruction set. By applying the specifications provided by the instruction set architecture, the validity or invalidity of a given instruction encoding may be readily determined.
However, some instruction set architectures designate certain instruction encodings as “unpredictable.” Such instruction encodings are technically valid, in that they comply with the semantics of the instruction set, but nevertheless the instruction encodings are architecturally incorrect. As a result, the instruction set architecture is unable to specify the outcome that will occur should execution of the unpredictable instruction encodings be attempted. Execution of unpredictable instruction encodings is undesirable because of the risk of causing a system hang, or a violation of user privileges or system security. Moreover, additional logic may need to be implemented in hardware to handle the special cases raised by unpredictable instruction encodings.
Some implementations of instruction set architectures attempt to reduce the risks posed by unpredictable instruction encodings by checking for unpredictable conditions prior to placing the instructions in an instruction cache (“I-cache”). If a problematic unpredictable instruction encoding is detected, a modified or replaced instruction can be placed in the I-cache in lieu of the original instruction. However, the bits of an instruction already stored in the I-cache may be altered by a parity error, resulting in an unpredictable instruction encoding in the I-cache. This may result in the unpredictable instruction encoding being executed and potentially causing a system hang, a privilege or security violation, or an occurrence of an undesirable special case. Recovering from execution of the unpredictable instruction may also require that a program counter of the CPU be rolled back to a previous state or that the unpredictable instruction be re-decoded, resulting in decreased CPU performance.
Embodiments disclosed in the detailed description include preventing execution of parity-error-induced unpredictable instructions, and related processor systems, methods, and computer-readable media. In this regard, in one embodiment a method for processing instructions in a central processing unit (CPU) is provided. The method comprises decoding an instruction comprising a plurality of bits in an instruction pipeline of a CPU, and generating a parity error indicator indicating whether a parity error exists in the plurality of bits prior to execution of the instruction. If the parity error indicator indicates that the parity error exists in the plurality of bits, one or more of the plurality of bits are modified to indicate a no execution operation (NOP), without effecting a roll back of a program counter of the CPU and without re-decoding the instruction. In this manner, the possibility of the parity error causing an inadvertent execution of an unpredictable instruction is reduced, without incurring a CPU performance penalty associated with rolling back the program counter or re-decoding the instruction.
In another embodiment, an instruction processing circuit in a CPU is provided. The instruction processing circuit comprises an instruction decoding circuit, a parity error detection circuit, and an instruction modification circuit. The instruction decoding circuit is configured to decode an instruction comprising a plurality of bits. The parity error detection circuit is configured to generate a parity error indicator indicating whether a parity error exists in the plurality of bits prior to execution of the instruction. The instruction modification circuit is configured to receive as input the parity error indicator. The instruction modification circuit is further configured to modify one or more of the plurality of bits to indicate a NOP if the parity error indicator indicates that the parity error exists in the plurality of bits, without effecting a roll back of a program counter of the CPU and without re-decoding the instruction,
in another embodiment, an instruction processing circuit is provided. The instruction processing circuit comprises a means for decoding an instruction comprising a plurality of bits. The instruction processing circuit further comprises a means for generating a parity error indicator indicating whether a parity error exists in the plurality of bits prior to execution of the instruction. The instruction processing circuit also comprises a means for modifying one or more of the plurality of bits to indicate a NOP if the parity error indicator indicates that the parity error exists in the plurality of bits, without effecting a roll back of a program counter of the CPU and without re-decoding the instruction.
In another embodiment, a non-transitory computer-readable medium is provided, having stored thereon computer-executable instructions to cause a processor to implement a method comprising decoding an instruction comprising a plurality of bits. The method implemented by the computer-executable instructions further comprises generating a parity error indicator indicating whether a parity error exists in the plurality of bits prior to execution of the instruction. The method implemented by the computer-executable instructions also comprises modifying one or more of the plurality of bits to indicate a NOP if the parity error indicator indicates that the parity error exists in the plurality of bits, without effecting a roll back of a program counter of the CPU and without re-decoding the instruction.
With reference now to the drawing figures, several exemplary embodiments of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
Embodiments disclosed in the detailed description include preventing execution of parity-error-induced unpredictable instructions, and related processor systems, methods, and computer-readable media. In this regard, in one embodiment a method for processing instructions in a central processing unit (CRU) is provided. The method comprises decoding an instruction comprising a plurality of bits in an instruction pipeline of a CPU, and generating a parity error indicator indicating whether a parity error exists in the plurality of bits prior to execution of the instruction. If the parity error indicator indicates that the parity error exists in the plurality of bits, one or more of the plurality of bits are modified to indicate a no execution operation (NOP), without effecting a roll back of a program counter of the CPU and without re-decoding the instruction. In this manner, the possibility of the parity error causing an inadvertent execution of an unpredictable instruction is reduced, without incurring a CPU performance penalty associated with rolling back the program counter or re-decoding the instruction.
In this regard,
With continuing reference to
The instruction processing circuit 14 of the processor-based system 10 may comprise an instruction decode circuit 26 holding a group of multiple instructions 28(0-N) simultaneously for decoding, as well as a parity error detection circuit 30, and an instruction modification circuit 32. The instruction decode circuit 26 receives the instruction 23 from the instruction fetch circuit 22, and decodes the instruction 23 by translating it into processor-specific microinstructions. The parity error detection circuit 30 also receives the instruction 23 from the instruction fetch circuit 22. The parity error detection circuit 30 generates a parity emir indicator represented by arrow 31 that indicates whether a parity error exists in a plurality of bits (not shown) constituting the instruction 23.
The instruction decode circuit 26 and the parity error detection circuit 30 then provide the instruction 23 and the parity error indicator 31, respectively, to an instruction modification circuit 32. The instruction modification circuit 32 is configured to modify one or more of the plurality of bits constituting the instruction 23 to indicate a NOP if the parity error indicator 31 indicates that the parity error exists in the plurality of bits. In some embodiments, modifying the one or more of the plurality of bits by the instruction modification circuit 32 to indicate a NOP may comprise modifying an encoding of the instruction 23. Some embodiments may provide that modifying the one or more of the plurality of bits by the instruction modification circuit 32 to indicate a NOP may comprise de-asserting a control signal associated with the instruction 23, where the control signal would have otherwise caused the instruction 23 to perform an action. In some embodiments, modifying the one or more of the plurality of bits by the instruction modification circuit 32 to indicate a NOP may comprise preventing the instruction 23 from reading and/or writing one or more architected resources, one or more non-architected resources, or a combination thereof. As used herein and understood by one of skill in the art, “architected resources” are processing resources provided by the CPU architecture, such as the registers 16(0-X) of
The instruction 23 may then optionally be issued to an instruction queue 34 (i.e., a buffer for storing instructions), or the instruction 23 may be issued to one of the execution pipelines 12(0-Q) for execution. in some embodiments, particular execution pipelines 12(0-Q) may restrict the types of operations that may be carried out within that particular execution pipeline. For example, pipeline P0 may not permit read access to the registers 16(0-X); accordingly, an instruction that indicates an operation to read register R0 may only be issued to one of the execution pipelines P1 through PQ.
With continuing reference to
To more clearly illustrate an exemplary processing of a parity-error-induced unpredictable instruction by the instruction processing circuit 14 of
As seen in
As indicated by arrow 46 of
With continuing reference to
A parity error indicator 31, indicating whether a parity error exists in the plurality of bits prior to execution of the instruction 23, is generated by the instruction processing circuit 14 (block 66). In some embodiments, the parity error indicator 31 may be generated by a parity error detection circuit, such as the parity error detection circuit 30 of
With continuing reference to
Accordingly, to prevent execution of the parity-error-induced unpredictable instruction, the instruction processing circuit 14 modifies one or more of the plurality of bits of the BLX instruction 84 to indicate a NOP. This is shown in resulting instruction stream 86 of
Preventing execution of parity-error-induced unpredictable instructions, and related processor systems, methods, and computer-readable media according to embodiments disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA a monitor, a computer monitor, a vision, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player.
In this regard,
Other master and slave devices can be connected to the system bus 98. As illustrated in
The CPU(s) 92 may also be configured to access the display controller(s) 110 over the system bus 98 to control information sent to one or more displays 116. The display controller(s) 110 sends information to the display(s) 116 to be displayed via one or more video processors 118, which process the information to be displayed into a format suitable for the display(s) 116. The display(s) 116 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The arbiters, master devices, and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a processor, a DSP, an Application Specific Integrated Circuit (ASIC), FPGA other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The embodiments disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. It is to be understood that the operational steps illustrated in the flow chart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present application claim priority to U.S. Provisional Patent Application Ser. No. 61/655,147 filed on Jun. 4, 2012, and entitled “PREVENTING EXECUTION OF PARITY-ERROR-INDUCED UNPREDICTABLE INSTRUCTIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS AND METHODS,” which is incorporated herein by references in its entirety.
Number | Date | Country | |
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61655147 | Jun 2012 | US |