Patent Application
20120247825
1. Technical Field
The disclosure generally relates to printed circuit boards, and more particularly to a printed circuit board used for eliminating coupled noise signals.
2. Description of the Related Art
A multilayer printed circuit board (PCB) is used to mechanically support and electrically connect electronic components using conductive pathways, such as copper traces. The PCB usually defines a plurality of vias, the vias extend through layers of the PCB to allow electrical connections of conductors on different layers. However, arrangement of the vias near conductive pathways, traces, and other vias, may cause coupled noise and mutual interference. To reduce the coupled noise, the distance between vias and the conductive pathways or other vias may be increased, but this will increase the size of the PCB as well.
Therefore, there is room for improvement within the art.
Many aspects of a printed circuit board can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the printed circuit board. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment.
Referring to
In this embodiment, at least one group of differential lines 12 is formed on the top signal layer 10. At least one group of differential lines 42 and at least one high-speed signal line 44 are formed on the bottom signal layer 40. The layer VCC is electrically connected to a power supply unit and provides operating power for the PCB 100. The layer GND is ground for electronic components of the PCB 100. The first middle layer 20 and the second middle layer 30 are for additional conductive paths that do not fit on the top layer 10 and the bottom layer 40.
The PCB 100 defines a plurality of vias 50 extending through all or some of the layers of the PCB 100. In this embodiment, the vias 50 are divided into a plurality of groups, each group includes two vias 50 that are electrically connected to two corresponding differential lines 12 in one group of the top signal layer 10. Each of the two vias 50 of one group is electrically connected to a corresponding differential line 42 of the bottom signal layer 40.
In this embodiment, since two differential lines in one group carry and deliver two equal and opposite-phase electrical signals, so when the two equal and opposite-phase electrical signals flow through the two vias 50 that are in the same group, the two vias 50 fail to generate coupled noise and mutual interference.
The PCB 100 further includes at least two ground vias 82 and at least one protection line 84 electrically connected between the corresponding ground via 82 to prevent and insulate noise. In this embodiment, the number of the ground vias 82 is two. The ground vias 82 extend through the PCB 100 and are electrically connected to the layer GND. The centers of the ground vias 82 and the centers of the vias 50 are located on the same line; the two vias 50 of one group are located between the two ground vias 82.
The protection lines 84 are located on the top signal layer 10, the bottom signal layer 40, and the first middle layer 20 and/or the second middle layer 30. In detail, referring to
Referring to
Referring to
In this embodiment, the coupled noise and interference on the bottom signal layer 40 are created by the high-speed signal line 44 and the vias 50, and are prevented and insulated by the protection lines 84, and are further guided to the layer GND through the protection lines 84 and the ground vias 82. In addition, the coupled noise and interference between two adjacent vias 50 in respectively two groups are prevented and insulated by the ground via 84 located between the two adjacent vias 50. The coupled noise is guided to the layer GND through the protection lines 84 and the ground vias 82.
In other embodiment, each group of the vias can include one, three, four or five vias 50, but not limited to two. In addition, the number of the ground vias 82 can be adjustably increased, such as six or eight, but not limited to two or four.
Moreover, the PCB can be a four-layer board, which omit the first middle layer 20 and the second middle layer 30. Thus, the protection lines 84 can be located on the ground layer GND.
In summary, in the PCB of this disclosure, the ground vias 82 are located and arranged adjacent to the corresponding vias 50, and the ground vias 82 are electrically connected using the protection lines 84. Thus, the coupled noise and the interference between the two adjacent vias 50 are prevented and isolated by the ground vias 82 and the protection lines 84. In addition, the protection lines 84 are located between the high-speed signal line 44 and the via 82. Thus, the coupled noise and interference between the vias 50 and the high-speed signal line 44 are prevented and insulated by the protection line 84, but not increasing the size of the PCB.
In the present specification and claims, the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. Further, the word “comprising” does not exclude the presence of other elements or steps than those listed.
It is to be understood, however, that even though numerous characteristics and advantages of the exemplary disclosure have been set forth in the foregoing description, together with details of the structure and function of the exemplary disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of exemplary disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201110074784.9 | Mar 2011 | CN | national |
