Patent Application
20230422408
The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2022-100320, filed Jun. 22, 2022, the entire contents of which are incorporated herein by reference.
A technology disclosed herein relates to a printed wiring board.
Japanese Patent Application Laid-Open Publication No. H11-214828 describes a printed wiring board in which a conductor circuit is formed on an insulating layer having a roughened surface. The entire contents of this publication are incorporated herein by reference.
According to one aspect of the present invention, a printed wiring board includes a first conductor layer, a resin insulating layer having an opening extending from a first surface to a second surface of the resin insulating layer and laminated on the first conductor layer, a second conductor layer formed on the first surface of the resin insulating layer such that the first conductor layer is facing the second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the opening of the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer and that the via conductor and the second conductor layer include a seed layer and an electrolytic plating layer formed on the seed layer. The seed layer includes an amorphous metal in a range of 5 wt % to 80 wt %.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
The insulating layer 4 is formed using a resin. The insulating layer 4 may contain inorganic particles such as silica particles or alumina particles. The insulating layer 4 may contain a reinforcing material such as a glass cloth. The insulating layer 4 has a third surface 6 (upper surface in the drawing) and a fourth surface 8 (lower surface in the drawing) on the opposite side with respect to the third surface 6.
The first conductor layer 10 is formed on the third surface 6 of the insulating layer 4. The first conductor layer 10 includes a signal wiring 12 and a pad 14. Although not illustrated in the drawing, the first conductor layer 10 also includes conductor circuits other than the signal wiring 12 and the pad 14. The first conductor layer 10 is mainly formed of copper. The first conductor layer 10 is formed of a seed layer (10a) on the insulating layer 4 and an electrolytic plating layer (10b) on the seed layer (10a). The seed layer (10a) is formed by a first layer (11a) on the third surface 6 and a second layer (11b) on the first layer (11a). Both the first layer (11a) and the second layer (11b) are sputtering films formed by sputtering. The first layer (11a) has a thickness of 10 nm or more and 500 nm or less. The second layer (11b) has a thickness of 10 nm or more and 1,000 nm or less. The seed layer (10a) contains 5 wt % or more and 80 wt % or less of an amorphous metal. That is, both the first layer (11a) and the second layer (11b) contain 5 wt % or more and 80 wt % or less of an amorphous metal. The first layer (11a) is formed of a copper alloy containing copper, silicon and aluminum. The copper content in the copper alloy is 90 at % or more and less than 99 at %. The copper content in the copper alloy is 90 at % or more and 98 at % or less. The second layer (11b) is formed of copper. The copper content in the second layer (11b) is 99 at % or more. The electrolytic plating layer (10b) is formed of copper. The first layer (11a) is in contact with the insulating layer 4.
A device for measuring the crystallinity of the seed layer (10a) is, for example, SEM “S-4300SE” manufactured by Hitachi High-Tech, EBSD “PEGAPUS Integration System” manufactured by TSL Solutions, or the like. Analysis conditions are, for example, an acceleration voltage of 15 kV and a measurement area of (6 μm)×(15 μm) (step size: 0.05 μm). Data processing conditions are, for example, a minimum grain size of 5 points, a grain boundary definition angle of 5 degrees or more, and a GCI of greater than 0.1.
The resin insulating layer 20 is formed on the third surface 6 of the insulating layer 4 and on the first conductor layer 10. The resin insulating layer 20 has a first surface 22 (upper surface in the drawing) and a second surface 24 (lower surface in the drawing) on the opposite side with respect to the first surface 22. The second surface 24 of the resin insulating layer 20 faces the first conductor layer 10. The resin insulating layer 20 has an opening 26 that expose the pad 14. The resin insulating layer 20 is formed of an epoxy resin and inorganic particles dispersed in the epoxy resin. Examples of the resin include a thermosetting resin and a photocurable resin. Examples of the inorganic particles include silica particles and alumina particles. An amount of the inorganic particles in the resin insulating layer 20 is 75 wt % or more.
The first surface 22 of the resin insulating layer 20 is formed mostly of the resin. Some of the inorganic particles are exposed in a small amount from the first surface 22. No unevenness is formed on the first surface 22 of the resin insulating layer 20. The first surface 22 is not roughened. The first surface 22 is formed substantially smooth. The first surface 22 has an arithmetic mean roughness (Ra) of 0.02 μm or more and 0.08 μm or less.
The second conductor layer 30 is formed on the first surface 22 of the resin insulating layer 20. The second conductor layer 30 includes a first signal wiring 32, a second signal wiring 34, and a land 36. Although not illustrated in the drawing, the second conductor layer 30 also includes conductor circuits other than the first signal wiring 32, the second signal wiring 34, and the land 36. The first signal wiring 32 and the second signal wiring 34 form a pair wiring. The first signal wiring 32 and the second signal wiring 34 are adjacent to each other.
The second conductor layer 30 is mainly formed of copper. The second conductor layer 30 is formed by a seed layer (30a) on the first surface 22 and an electrolytic plating layer (30b) on the seed layer (30a). The seed layer (30a) is formed by a first layer (31a) on the first surface 22 and a second layer (31b) on the first layer (31a). Both the first layer (31a) and the second layer (31b) are sputtering films formed by sputtering. The first layer (31a) has a thickness of 10 nm or more and 500 nm or less. The second layer (31b) has a thickness of 10 nm or more and 1,000 nm or less. The seed layer (30a) contains 5 wt % or more and 80 wt % or less of an amorphous metal. That is, both the first layer (31a) and the second layer (31b) contain 5 wt % or more and 80 wt % or less of an amorphous metal. The first layer (31a) is formed of a copper alloy containing copper, silicon and aluminum. The content of copper in the copper alloy is 90 at % or more and less than 99 at %. The copper content in the copper alloy is 90 at % or more and 98 at % or less. The second layer (31b) is formed of copper. The copper content in the second layer (31b) is 99 at % or more. The electrolytic plating layer (30b) is formed of copper. The first layer (31a) is in contact with the first surface 22.
The crystallinity measuring device, analysis conditions, and data processing conditions for the seed layer (30a) are the same as above.
The via conductor 40 is formed in the opening 26. The via conductor 40 connects the first conductor layer 10 and the second conductor layer 30. In
Although not illustrated in the drawings, each side of the printed wiring board 2 has a length of 50 mm or more. The length of each side is preferably 100 mm or more. The length of each side is 250 mm or less.
As illustrated in
The protective film 50 completely covers the first surface 22 of the resin insulating layer 20. An example of the protective film 50 is a film formed of polyethylene terephthalate (PET). A release agent is formed between the protective film 50 and the resin insulating layer 20.
As illustrated in
After that, the inside of the opening 26 is cleaned. Resin residues generated when the opening 26 is formed are removed. The cleaning of the inside of the opening 26 is performed using plasma. That is, the cleaning is performed in a dry process. The cleaning includes a desmear treatment. The inner wall surface 27 of the opening 26 is roughened with plasma. The inner wall surface 27 of the opening 26 is formed of the resin and the inorganic particles that form the resin insulating layer 20. On the other hand, the first surface 22 of the resin insulating layer 20 is covered by the protective film 50. The first surface 22 is not affected by the plasma. No unevenness is formed on the first surface 22 of the resin insulating layer 20. The first surface 22 is not roughened. Some of the inorganic particles are exposed in a small amount on the first surface 22. The first surface 22 is formed substantially smooth.
As illustrated in
As illustrated in
When the first layer (31a) and the second layer (31b) are formed by sputtering, sputtering conditions are adjusted such that a distance between a target and a substrate surface in a sputtering device is in a range of 50 mm or more and 250 mm or less, a voltage is in a range of 15 eV or more and 50 eV or less, and a gas concentration is in a range of 0.1 Pa or more and 1.0 Pa or less. As a result, the first layer (31a) is formed to have a thickness of 10 nm or more and 500 nm or less. The second layer (31b) is formed to have a thickness of 10 nm or more and 1,000 nm or less. Both the first layer (31a) and the second layer (31b) contain 5 wt % or more and 80 wt % or less of an amorphous metal.
As illustrated in
As illustrated in
After that, the plating resist 60 is removed. The seed layer (30a) exposed from the electrolytic plating layer (30b) is removed. The seed layer (30a) is removed by wet etching. By the wet etching, the first layer (31a) and the second layer (31b) are removed at the same time. The second conductor layer 30 and the via conductor 40 are formed at the same time. The printed wiring board 2 (
In the printed wiring board 2 of the embodiment (
In a first alternative example of the embodiment, the first layers (11a, 31a) of the seed layers (10a, 30a) are each formed of copper and a second element. The second element is selected from silicon, aluminum, titanium, nickel, chromium, carbon, oxygen, tin, calcium, magnesium, iron, molybdenum, and silver. The first layers (11a, 31a) are each formed of an alloy containing copper. The second layers (11b, 31b) are each formed of copper. The copper content (at %) forming the second layers (11b, 31b) is 99.9 at % or more, and preferably 99.95 at % or more.
In a second alternative example of the embodiment, the first layers (11a, 31a) of the seed layers (10a, 30a) are each formed of any one metal of aluminum, titanium, nickel, chromium, calcium, magnesium, iron, molybdenum, and silver.
In a third alternative example of the embodiment, the seed layer (10a) is formed by electroless plating.
The five conductor layers include a first conductor layer 110, a second conductor layer 130, a third conductor layer 230, a fourth conductor layer 330, and a fifth conductor layer 430. The conductor layers are each formed of a seed layer (110a, 130a, 230a, 330a, 430a) and an electrolytic plating layer (110b, 130b, 230b, 330b, 430b).
The seed layer (110a) of the first conductor layer 110 and the seed layer (230a) of the third conductor layer 230 are electroless plating films formed by electroless plating. The seed layers (110a, 230a) do not contain an amorphous metal. Hereinafter, the seed layers (110a, 230a) may be referred to as “first type seed layers.” The electrolytic plating layers (110b, 230b) on the first type seed layers (seed layers (110a, 230a)) may be referred to as “first type electrolytic plating layers.” The first conductor layer 110 and the third conductor layer 230 may be referred to as “first type conductor layers.” The first type conductor layers are each, for example, a signal wiring layer including a signal wiring.
On the other hand, the second conductor layer 130, the fourth conductor layer 330, and the fifth conductor layer 430 are similar to the second conductor layer 30 of the embodiment. That is, the seed layer (130a) of the second conductor layer 130, the seed layer (330a) of the fourth conductor layer 330, and the seed layer (430a) of the fifth conductor layer 430 are sputtering films formed by sputtering. Although not illustrated in
The four resin insulating layers include a first resin insulating layer 120, a second resin insulating layer 220, a third resin insulating layer 320, and a fourth resin insulating layer 420. The first resin insulating layer 120 is similar to the resin insulating layer 20 of the embodiment. The second resin insulating layer 220, the third resin insulating layer 320, and the fourth resin insulating layer 420 have the same structure (the resin and the inorganic particles) as the first resin insulating layer 120. The first resin insulating layer 120, the second resin insulating layer 220, the third resin insulating layer 320, and the fourth resin insulating layer 420 are formed using the same method as that for the resin insulating layer 20 of the embodiment.
Although not illustrated, the first resin insulating layer 120, the second resin insulating layer 220, the third resin insulating layer 320, and the fourth resin insulating layer 420 have openings. Via conductors are formed in the openings. The via conductors in the openings of the first resin insulating layer 120 connect the first conductor layer 110 and the second conductor layer 130. The via conductors in the openings of the second resin insulating layer 220 connect the second conductor layer 130 and the third conductor layer 230. The via conductors in the openings of the third resin insulating layer 320 connect the third conductor layer 230 and the fourth conductor layer 330. The via conductors in the openings of the fourth resin insulating layer 420 connect the fourth conductor layer 330 and the fifth conductor layer 430.
As illustrated in
The build-up layer 700 has 5 or more conductor layers. The build-up layer 700 preferably has 10 or more conductor layers. The number of the conductor layers is 20 or less.
Japanese Patent Application Laid-Open Publication No. H11-214828 describes a printed wiring board in which a conductor circuit is formed on an insulating layer having a roughened surface. The conductor circuit is formed of an electroless plating film formed on the insulating layer and an electrolytic plating film formed on the electroless plating film. The electroless plating film is formed following the roughened surface of the insulating layer.
In Japanese Patent Application Laid-Open Publication No. H11-214828, the electroless plating film is formed following the roughened surface of the insulating layer. A part of the electroless plating film is formed entering an inner side of the surface of the insulating layer. It is thought that when the electroless plating film is removed in a manufacturing process, an etching amount is large. It is thought that the electrolytic plating film is excessively removed. Therefore, it is thought that it is difficult to form a fine wiring. Further, it is thought that, since the surface of the conductor circuit is roughened, transmission loss increases. As a result, it is thought that a high-quality printed wiring board is not provided.
A printed wiring board according to an embodiment of the present invention includes: a first conductor layer; a resin insulating layer that has a first surface and a second surface on the opposite side with respect to the first surface, an opening extending from the first surface to the second surface, and is laminated on the first conductor layer such that the second surface faces the first conductor layer; a second conductor layer that is formed on the first surface of the resin insulating layer; and a via conductor that is formed in the opening and connects the first conductor layer and the second conductor layer. The second conductor layer and the via conductor are formed of a seed layer and an electrolytic plating layer formed on the seed layer. The seed layer contains 5 wt % or more and 80 wt % or less of an amorphous metal.
In a printed wiring board according to an embodiment of the present invention, the seed layer contains 5 wt % or more and 80 wt % or less of an amorphous metal. The seed layer containing 5 wt % or more and 80 wt % or less of an amorphous metal is more easily removed by etching than a seed layer that does not contain an amorphous metal. When the seed layer is removed in a manufacturing process of the printed wiring board, an etching amount is reduced. Since the electrolytic plating layer is not excessively removed, a fine wiring is formed. Further, since the surface of the conductor circuit in the second conductor layer is unlikely to be roughened, transmission loss is reduced. As a result, a high-quality printed wiring board is provided.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-100320 | Jun 2022 | JP | national |
