Claims
- 1. A central processor of a digital computer system comprising:
- a store into cache memory, said cache memory including memory array storage means for computer data, operands or instructions, or both, having an address; and primary and secondary access control means responsive to access request signal sets being applied to said primary and secondary access control means, where each access request signal set includes an address of computer data and instruction signals for controlling the operation of the cache memory, for causing the memory array storage means to execute substantially simultaneously the instruction signals of two access request signal sets applied to the memory array by the primary and secondary access control means substantially simultaneously;
- central unit pipeline structure (CUPS) means for executing instructions in pipeline fashion and for producing an access request signal set for each instruction in execution;
- first circuit means for applying exclusively access request signal sets produced by the CUPS to the primary access control means of the cache memory;
- a paging unit of the CUPS for correlating a virtual address and a real address and for producing the address of computer data included in each access request signal set produced by the CUPS and for producing access request signal sets of computer data used by the paging unit in producing the address signals of access request signal sets applied to the secondary access control means of the cache memory;
- a ports unit of the central processor for accessing the main memory of the digital computer system and for producing access request signal sets of computer data for writing computer data into the memory array storage means of the cache memory and for reading computer data out of the memory array storage means of the cache memory;
- an instruction fetch unit of the central processor for producing access request signal sets of instructions;
- second circuit means for applying in parallel access request signal sets produced by the paging unit of the CUPS, the ports unit and the instruction fetch unit to the secondary access control means of the cache memory; and
- means for prioritizing which of the access request signal sets applied to the secondary access control means waiting executing is to be placed in execution by the memory array storage means based on the function of the instruction signals of the sets of access request signal sets applied thereto.
Parent Case Info
This is a continuation of co-pending application Ser. No. 06/470,126 filed on Feb. 28, 1983, now abandoned.
US Referenced Citations (14)
Foreign Referenced Citations (1)
Number |
Date |
Country |
164338 |
Aug 1982 |
JPX |
Continuations (1)
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Number |
Date |
Country |
Parent |
470126 |
Feb 1983 |
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