Patent Application
20090254875
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
A net layout may include a mapping of electrical connections within each of a variable number of layers in a semiconductor integrated circuit. Computer-driven routing systems are often used to build layouts to articulate designs to be expressed in an integrated circuit. Such systems typically use a netlist which is a description of required connections between terminals, and create a net layout to make such required connections.
To perform routing, the router receives chip technology data including various rules such as geometric rules that describe parameters and characteristics of layers on which rectangles representing wires can be generated, the minimum allowed width of any part of a trace, and the minimum allowed separation between traces. Typically, a router executes a global routing step for allocating groups of nets to be routed through corresponding general routing areas.
One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions should be, made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design and manufacture for those of ordinary skill having the benefit of this disclosure.
Drivers 12a-c, which are also known as a sources, are generally configured to generate or propagate a signal intended for a destination located at another location on integrated circuit 10 (receivers 16a-c, for example). In some embodiments, drivers 12a-c include a simple circuit, an instance, and/or a cell. For, example, drivers 12a-c may be a part of a logic component, such as an output pin of a flip-flop, latch, a buffer, and the like. In some embodiments, the drivers 12a-c are logic component pins. Drivers 12a-c may also be an input/output component, such as an input pad.
Net layout 14 is a map of electrical connections on various layers in integrated circuit 10. Net layout 14 includes one or more nets 18 that interconnect one or more of drivers 12a-c and receivers 16a-c.
Receivers 16a-c are configured to receive signals generated from one or more of drivers 12a-c. Although three receivers 16 are illustrated, any suitable number of receivers may be coupled via nets 18 to one or more of drivers 12a-c. For example, receivers 16a-c may be a part of a logic component, such as an input pin of a flip-flop, latch, a buffer, and the like. In some embodiments, the receivers 16a-c are logic component pins. Receivers 16a-c may also be output ports.
Although
For example, in
At the same time, it is also often desirable for a particular net to take the shortest route between driver 12a and receiver 16a through net layout 14. The amount of time it takes for a signal to travel from driver 12a to receiver 16.a typically increases as net length increases. Because most integrated circuits operate on a clock, the “slowest” net and/or the slowest timing path may dictate the timing for the entire integrated circuit. In addition, many integrated circuit designers establish time thresholds for signals to travel between the driver 12a and the receiver 16a. If a particular net is so long that a signal cannot traverse between driver 12a and receiver 16a during the established time limit (e.g., 500 picoseconds), an error can develop on integrated circuit 10.
As described above there may be many drivers 12a-c and receivers 16a-c sharing a single net layout 14 or a section of net layout 14. Ideally, these drivers and receivers would be interconnected by nets that each took the shortest route through net layout 14 while still maintaining the target separation from other nets. In the reality of contemporary semiconductor design, however, this ideal is rarely, if ever, possible, and some nets may have to take less than optimal routes through net layout 14. For example, physical implementation 36b is two grid lines or “tracks” off center from the ideal route between driver 12a and receiver 16a and net 36c is both off-center and longer than the ideal route due to diversion 38 in the route of physical implementation 36c. Diversion 38 may be necessary, for example, to avoid another net (not shown), such as a net entering grid 30 from another layer of net layout 14 (also not shown).
One or more of the embodiments described below provides techniques for setting routes through net layout 14 that balance the competing concerns of each net based on the specific attributes of integrated circuit 10, driver 12a, receiver 16a, and/or the signals passing between them on the net 36 that connects driver 12a and receiver 16a. Moreover, the techniques may be employed before full global routing is performed on an integrated circuit design.
Referring again to
Parasitic extraction of a physical implementation (routes) of a net involves a process of calculating the capacitance, resistance, and inductance values corresponding to the route segments and determining the connectivity among these segments to create a parasitic network. The topology of the parasitic network and the values of its parasitic elements are used by delay calculator to determine the amount of time it takes for a signal to propagate from a driver to any of the receivers of the net. In some embodiments, a delay calculator is used to determine this time, in particular, in embodiments using static timing analysis. Since global routes of a net do not contain information about the exact geometries, 2D extraction employs probabilistic methods to estimate capacitance and resistance of such routes.
Next, technique 50 may involve a component of the design, automation tool set performing a static timing analysis on drivers 12a-c and receivers 16a-c using a netlist for integrated circuit 10, as indicated by block 54. In some systems, a timing tool may perform the static timing analysis. As those of ordinary skill in the art will appreciate, performing a static timing analysis may involve determining the signal timing along an ideal or optimistic (i.e., shortest) route for each net on the netlist. In some embodiments, determining the signal timing includes determining timing along a timing path that includes multiple nets in series.
The static timing analysis also involves determining slack for each net in the netlist, for integrated circuit 10. In some embodiments, determining slack for the net involves first determining slack for a timing path that may include multiple nets in series. The slack for the timing path can be determined by subtracting the ideal timing for the timing path from the permissible delay for the timing path. The permissible timing for the entire path may be part of a specification or set of design/timing rules for integrated circuit 10. For example, the permissible timing may be based on a desired clock frequency for integrated circuit 10.
After the slack is determined for the net, the technique 50 may include applying a routing condition to the net, as indicated by block 56. A routing condition is a shortcoming/imperfection in a physical implementation of a net. In some embodiments, the routing condition is characterized by a number indicative of the severity of the condition. One exemplary routing condition is a detoured routing. A detour of a net routing is routing with a wire length that is longer than the shortest or ideal route through net layout 14. A detour routing condition may be characterized by a detour factor, which is indicative of the degree of the detour. For example, the detour routing condition may be a percentage (e.g., 50%, 100%, 150%) increase in wire length. Another exemplary routing condition is crosstalk which correlates to net slowdown by capacitive crosstalk from other nets. A crosstalk routing condition may be characterized by a Miller factor. In still other examples, any one of a number of other suitable routing conditions may be selected.
After the routing condition is applied, the technique 50 may include calculating an extra delay in the instance driving the net and along the net as a result of the routing condition, as indicated by block 58. For example, if the routing condition is a detour with a 50% increase in wire length and the delay along the ideal route is 4 nanoseconds, the 50% increase in wire length may add 3 ns of extra delay on the net (if the net delay is linear) or 4 ns of delay (if the net delay is quadratic). Similarly, if the routing condition is crosstalk, applying the routing condition may involve increasing the Miller factor on the net by a factor of 2× or 2.5×, for example, and calculating the resulting delay along the net (e.g., 6 ns). This extra delay together with the extra delay in the instance driving the net is referred to as the sensitivity of the net. In some embodiments, the extra delay may include an extra delay related to delay in a driver instance or a delay caused by another net in a timing path.
Once the extra delay that would result from the routing condition is computed, a criticality of the net to the extra delay can be determined, as indicated by block 62. In some exemplary embodiments, determining the criticality of the net involves determining an adjusted slack value for the net. Adjusted slack is determined by subtracting the extra delay that would be caused by the routing condition from the slack on the net (see block 54 above). If the extra delay would exceed the slack, then the net is determined to be critical with respect to the routing condition. Typically, the smaller the adjusted slack the more critical the net. In other embodiments, different techniques may also be employed to determine if the net is sensitive to the routing condition.
In some embodiments, blocks 56-62 may then be repeated to determine the criticality based on other routing conditions and/or other nets. For example, blocks 56-60 may be performed once to determine the criticality for a detour routing condition and another time for a crosstalk routing condition. In other embodiments, blocks 56-60 may involve computing these two criticalities at the same time or in a co-pending manner.
Based at least partially on the determined criticality of the net, the technique 50 may next involve setting a soft constraint for the net, as indicated by block 64. A soft constraint is a control, in a router or routing tool, for example, that can be applied on a net to reduce the probability and severity of the routing condition on that net. For example, the soft constraint may be a limitation on detouring the net either at all or by a certain amount.
The soft constraint is termed “soft”, because it is typically not possible to satisfy every soft constraint during global routing and detail routing of integrated circuit 10. As such, some soft constraints may have to be ignored, as described further below. In some embodiments, the technique 50 may include sorting the net into one or more “bins” based on that net's criticality. For example, the router may maintain one bin for the most critical soft constraints, another for slightly less critical soft constraints, and so on. For example, those nets with smaller adjusted slack can be placed into a more critical bin than other nets with larger adjusted slack values. Alternatively, the soft constraints may be sorted into linear order based on their individual adjusted slack values. Still other suitable statistical models or calculations, such as fuzzy logic, may also be employed for determining the best set of constraints.
After soft constraints have been determined for the desired number of nets, the technique 50, the router will perform a global routing, as indicated by block 68 of
In various embodiments, global routing may involve one or more of the following, nonexclusive steps:
Ideally, the global routing will apply all of the soft constraints. To the extent that it is not possible for the router to apply all of the soft constraints, the most critical soft constraints may be applied by the router first. For example, if the criticality analysis involved binning the soft constraints, those nets having soft constraints in the highest priority bin would be routed first, generally followed by those nets having soft constraints in the next highest priority bin, and so on. The router may also be configured to sort the soft constraints within each bin. As those of ordinary skill will appreciate, the router is configured to perform a global routing based on the soft constraints.
After global routing is complete, the router will perform detailed routing, as indicated by block 70. In various embodiments, detailed routing may involve one or more of the following, nonexclusive steps:
Conventional routers often encounter critical design problems during detail routing when two different steps (e.g. two design rules) cannot be reconciled. When these critical design problems are encountered by conventional routers, there is typically little choice but to make a manual change to the detailed routing parameters and to start the detailed routing process again. As the detailed routing process is typically the most time consuming and expensive portion of the wire routing process, it is desirable to reduce the number of times that detailed routing must be performed to arrive at a manufacturable design (ideally to a single detailed routing). Advantageously, technique 50 enables the router to perform global and detailed routing on the nets of integrated circuit 10 in an order that is based on the criticality of the net and its sensitivity to routing conditions. In doing so, design conflicts, such as crosstalk, that conventionally appear during detail routing are proactively addressed. Thus, implementation of technique 50 may reduce the time and expense of integrated circuit design.
As described above, technique 50 may be stored or embodied in hardware, software, or firmware that is executed by one or more tools in a design automation tool set.
Memory 102 may include a number of individual, volatile or non-volatile memory modules that store segments of operating system and, application software while power is supplied to router 100. Memory 102 may store a design automation tool set 110, library data 112 and netlist 114. Logic design tool 110 may include instructions capable of being executed by processor 104. In an alternative, design automation tool set 110 could be implemented by control circuitry through the use of logic gates, programmable logic devices, or other hardware components in lieu of a processor-based system. In at least one example system, design automation tool set 110 includes a version of NexusRoute software that has been configured to execute technique 50, as described above.
Processor 104 controls the operation of the workstation 100, including executing the arithmetic and logic functions contained in a particular computer program within memory 102. Although not depicted in
Storage 106 can be any type of storage device, such as a hard-disk drive, or a CD-ROM drive. Although storage 106 is shown as being incorporated within workstation 100, it could be external to workstation 100, either connected directly or on a local area network, on an external network, or attached to a remote computer system.
In various embodiments, workstation 100 can be implemented utilizing any suitable computer such a UNIX workstation, a PC, or other suitable computerized device, any of which are available from a variety of vendors. However, technique 50 can be executed on any computer system or configuration that allows circuit design, regardless of whether the computer system is a complicated, multi-user computing apparatus or a single-user work station
Many of the embodiments described above pertain to specific method steps implementable on a computer system or as a computer program product for use with a computer system. The programs defining the functions of the embodiment can be delivered to a computer via a variety of instruction-bearing media, which include, but are not limited to, (1) information permanently stored on non-writeable storage media (e.g., CD-ROM disks); (2) alterable information stored on writeable storage media (e.g., a hard-disk drive); or (3) information conveyed to a computer by a communications media, such as through a computer or telephone network, including wireless communications. Such instruction-bearing media when carrying computer-readable instructions that direct the functions of the above described embodiments are within the scope of those embodiments.
Although numerous embodiments have been described in detail above, it will be apparent to those skilled in the art that many additional embodiments taking a variety of specific forms and reflecting changes, substitutions, and alterations can be made without departing from the spirit and scope of the invention. The described embodiments illustrate the breadth of the claims but should not be interpreted to restrict the scope of the claims.
