Claims
- 1. A method of testing a semiconductor device comprising the steps of:providing a probe membrane having one or more probe tips adapted to provide electrical contact with input/output pads on said semiconductor device, said probe membrane having electrically conducting paths electrically connected to said probe tips, wherein said probe tips comprise compliant bump probe tips; providing a package for containing said probe membrane wherein said probe membrane is attached to said package by a layer of elastomeric material, said package having electrical connections electrically connected to said electrically conducting paths of said probe membrane; and providing test and burn in circuitry operably coupled to said electrical connections of said package.
- 2. The method as recited in claim 1, wherein said semiconductor device is mounted in said package by a layer of elastomeric material.
- 3. The method as recited in claim 1, wherein one or more of said compliant bump probe tips include a film of probing material.
- 4. The method as recited in claim 3, wherein said film of probing material includes an abrasive grit.
- 5. The method as recited in claim 1, wherein the compliant bump probe tips are comprised of a solid material.
CROSS-REFERENCE TO RELATED APPLICATION
This is a division of application Ser. No. 08/858,107 filed May 19, 1997, now U.S. Pat. No. 6,028,437.
This application for patent is related to co-pending U.S. patent application Ser. No. 08/748,843, now U.S. Pat. No. 5,898,783, which is hereby incorporated by reference herein.
US Referenced Citations (4)