Claims
- 1. An apparatus adaptable for the testing of semiconductor devices comprising:
- a package; and
- a probe membrane contained within said package having electrical paths adaptable for coupling to test circuitry, wherein said probe membrane includes a probe membrane head, a plurality of standoffs affixed to said probe membrane, and a plurality of probe tips affixed to said probe membrane head, said probe tips adaptable for making electrical contact with pads on said semiconductor device, wherein said probe tips are compliant bump probe tips.
- 2. The apparatus as recited in claim 1, said package further comprising:
- a package base having an upper surface adapted to receive said probe membrane, said probe membrane head having a lower surface,
- a bonding layer interposed between said probe membrane head lower surface and said package base upper surface; and
- a package lid having a lower surface adapted to receive said semiconductor device, wherein said package lid is positioned above said package base.
- 3. The apparatus as recited in claim 2, wherein said bonding layer is comprised of an elastomeric material.
- 4. The apparatus as recited in claim 2, wherein said semiconductor device is a die having an upper surface, said upper surface fixed to said package lid lower surface by a bonding layer interposed therebetween.
- 5. The apparatus as recited in claim 2, wherein said semiconductor device is a wafer having an upper surface, said upper surface fixed to said package lid lower surface by a bonding layer interposed therebetween.
- 6. The apparatus as recited in claim 4, wherein said bonding layer interposed between said die and said package lid lower surface is comprised of an elastomeric material.
- 7. The apparatus as recited in claim 5, wherein said bonding layer interposed between said wafer and said package lid lower surface is comprised of an elastomeric material.
- 8. The apparatus as recited in claim 1, wherein the compliant bump probe tips are comprised of a solid material.
- 9. The apparatus as recited in claim 1, wherein the semiconductor device is a wafer containing a plurality of dies, and wherein the probe membrane head has a sufficient number of the plurality of probe tips to simultaneously test each of the dies on the wafer.
- 10. An apparatus adaptable for the testing of semiconductor devices comprising:
- a package, wherein said package has a package lid having a lower surface adapted for receiving said semiconductor device, said semiconductor device having an upper surface, and a package base having an upper surface;
- a probe membrane contained within said package, wherein said probe membrane has electrical paths adaptable for coupling to test circuitry, said probe membrane including a probe membrane head, said probe membrane head having a plurality of probe tips affixed thereto, a plurality of standoffs affixed thereto, and a lower surface, wherein said probe tips are adaptable for making electrical contact with pads on said semiconductor device and are compliant bump probe tips;
- a bonding layer comprising an elastomeric material interposed between said package lid lower surface and said semiconductor device upper surface; and
- a bonding layer comprising an elastomeric material interposed between said probe membrane head lower surface and said package base upper surface, said package base being adapted for receiving said probe membrane head.
- 11. The apparatus as recited in claim 10, wherein the compliant bump probe tips are comprised of a solid material.
CROSS-REFERENCE TO RELATED APPLICATION
This application for patent is related to co-pending U.S. patent application Ser. No. 08/748,843, now U.S. Pat. No. 5,898,783, which is hereby incorporated by reference herein.
US Referenced Citations (10)