Process for counter doping N-type silicon in Schottky device with Ti silicide barrier

Abstract

A Schottky diode has a barrier height which is adjusted by boron implant through a titanium silicide Schottky contact and into the underlying N− silicon substrate which receives the titanium silicide contact. The implant is a low energy, of about 10 keV (non critical) and a low dose of less than about 1E12 atoms per cm2 (non-critical).

Description

FIELD OF THE INVENTION

[0002] This invention relates to a process of manufacturing Schottky barrier diodes where Titanium Silicide is used as a Schottky barrier metal, and its effective barrier height is increased by means of Boron implantation through the Titanium Silicide layer, followed by drive-in by a high temperature diffusion or sintering process.

BACKGROUND OF THE INVENTION

[0003] The self aligned Silicide (or Salicide) process is known in CMOS technology to create thin films of low resistivity. As the device dimensions shrink, the area of diffused regions shrink accordingly, and the parasitic resistance (to lateral conduction) of the conductive film is increased. This adversely affects the device operation because of the increased heat dissipation and increased time delay of signal propagation.

[0004] Due to its low bulk resistivity, titanium silicide (TiSi2) is an attractive material for lowering the sheet resistivity so that diffused regions can be connected over longer distances without additional heat dissipation.

[0005] However, the Schottky barrier height in these processes is not well controlled. It would be very desirable to control the barrier height of a titanium silicide Schottky device with a simple process.

BRIEF SUMMARY OF THE INVENTION

[0006] In the present invention a titanium silicide Schottky barrier diode is formed, using titanium silicide as a Schottky barrier metal and its barrier height is controlled by a N novel type counter-doping step.

[0007] As shown by comparative I-V measurements on non-implanted samples, the barrier height value of titanium suicide on N-type silicon is approximately 70 meV lower than molybdenum and 10 meV higher than vanadium, making this material a very good candidate for low forward voltage drop Schottky diodes required in applications where low power dissipation during forward conduction is the main requirement, such as portable equipment, disk drives, switching power supplies, battery charging and reverse battery protection equipment, converters and PC boards. A method is provided by the invention of controlling the barrier height of titanium silicide is provided, in order to slightly “tune” the I-V trade-off characteristics over a certain range to meet different target specifications. Thus, two successive annealing steps are used for the self-aligned titanium silicide formation process. After a thin (600 A) layer of titanium is sputtered atop a silicon wafer, the wafer is annealed in RTA system at a relatively low temperature (approx. 650° C.). The un-reacted titanium is next removed, preferably by an ammonia-based clean, and a low energy implantation to counter dope the underlying silicon is performed through the remaining titanium silicide layer. Thereafter an etch in ammonia, water and hydrogen peroxide is preferably used because of the high selectivity against oxide and titanium silicide. A second anneal is then carried out at higher temperature (850° C.) and the implanted species is driven-in from the silicide and activated to adjust the concentration of the silicon at the silicon surface. This simple 4-step process:

[0008] 1. Anneal 1

[0009] 2. Ti Etch

[0010] 3. boron implantation (for an N type silicon substrate)

[0011] 4. Anneal 2

[0012] completes the Schottky barrier formation. Process steps prior to Ti deposition and after the second anneal are part of the standard known process of Schottky diode manufacturing and need not be described.

[0013] The above barrier formation process has been used for both a planar Schottky diodes and Schottky diodes with a trench structure. In both cases a dependence of barrier height on the implanted dose is found and controlled, as demonstrated by Current-Voltage measurements on assembled parts which will be later described.

[0014] As indicated by forward drop measurements at a fixed forward current, the barrier height of the titanium silicide/silicon interface or contact can be increased by as much as 150 mV with a boron implant dose ranging from 0 to 9E13 atoms/cm2 (for a trench diode). The amount of charge depends upon several factors, such as silicide thickness and stoichiometry (which, in turn, depends upon annealing conditions) and the silicon doping level. The process uniformity achievable is related to silicide uniformity and implanter accuracy. Due to the shallow diffusion desired by this process, a low energy implanter is preferred.

[0015] Stated in other terms, the boron implant after the first Silicide anneal, and through the Silicide controls the “tail” of the boron in the silicon to obtain counter doping of the N-epi. That is, it puts the boron profile peak inside the TiSi2. This is done in such as way as to not create a P/N junction, but simply counter-dopes the N type silicon and reduces N concentration, and leakage current.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is a cross-section of the top surface of a Silicon die for a planar device, after the formation of a field oxide, a P+ guard ring and an etch to open the active area.

[0017] FIG. 2 is a cross-section of FIG. 1 after a titanium-sputter step.

[0018] FIG. 3 is a cross-section of FIG. 2 after a thermal anneal.

[0019] FIG. 4 is a cross-section of FIG. 3 after a titanium etch to remove metallic suicide and to expose the titanium silicide barrier in the active area.

[0020] FIG. 5 is a cross-section of FIG. 4 with a boron implant through the TiSi2 layer.

[0021] FIG. 6 is a cross-section of FIG. 5 after a rapid thermal anneal to drive and activate the boron implant.

[0022] FIG. 7 shows a second embodiment of the invention, and shows a cross-section of two of a large number of parallel trenches after the formation of the trench, and filling the trench with an oxide liner and polysilicon and after a titanium sputter step.

[0023] FIG. 8 is a cross-section of FIG. 7 after a rapid thermal anneal to form a titanium silicide.

[0024] FIG. 9 is the cross-section of FIG. 8 after a titanium etch.

[0025] FIG. 10 is the cross-section of FIG. 9 showing a boron implant.

[0026] FIG. 11 is the cross-section of FIG. 10 after a second rapid thermal anneal.

[0027] FIGS. 12A, 12B and 12C show the effect of the boron implant on the planar structure of FIGS. 1 to 6.

[0028] FIGS. 13A and 13B show the calculated boron profile after implant and drive for two doses, 9E12 and 9E13 atoms/cm2, respectively.

DETAILED DESCRIPTION OF THE DRAWINGS

[0029] Referring first to FIG. 1, there is shown the first step in the process of manufacture of a planar diode which uses the invention. Only, the upper surface of the silicon is shown. Thus, a die 20 which may be comprised of an N− epitaxial layer on an N− substrate (not shown) has a field oxide 21 formed thereon. The N− epitaxial layer may have a resistivity of about 0.1 to 0.5 ohm cm.

[0030] The field oxide 21 is patterned to permit the formation of a P+ diffused guard ring 22 of conventional structure. The field oxide is then opened to expose the silicon surface and an interior portion of the P+ ring 22, as shown by the labeled “active area”. Thereafter, the top surface is cleaned AS with a 100:1 HF clean step for 30 seconds.

[0031] Titanium layer 24, shown in FIG. 2, is next sputtered or otherwise formed atop the die. A 600 Å (non-critical) sputter with a pre-heating station at approximately 300° C. may be used.

[0032] Next, as shown in FIG. 3, a rapid thermal anneal is carried out at about 625° C. for 30 seconds in an N2 flow. This causes the formation of a titanium Silicide layer 25 and the growth of a Titanium Nitride layer 26.

[0033] Next, as shown in FIG. 4, a Ti etch is carried out, removing the titanium nitride and the unreacted titanium metal atop the TiS2 layer. This etch may take place at 21° C. with continuous agitation, using NH4OH:H2O2:H2O@6:1:1, followed by a deionized water flush and further flushes with NH4OH and H2O2.

[0034] Next, as shown in FIG. 5, and in accordance with the invention, a low dose boron implant takes place through the Titanium Silicide layer 25. This implant is at a low energy of about 10 kev and at a low dose of from 10E11 to 10E13 atoms/cm2. Other P type species can be used.

[0035] As next shown in FIG. 6, the boron implant is driven and activated in a second rapid thermal anneal process at 850° C. for 30 seconds in N2 flow.

[0036] Following this second anneal, standard process steps for completing the Schottky device are used, of:

[0037] contact metal pre-clean and deposition;

[0038] contact metal mask;

[0039] contact metal etch; and

[0040] back metal on the bottom of the N+ substrate (not shown).

[0041] As stated previously, the invention can also be applied to trench Schottky device. Thus as shown in FIG. 7, an N− epitaxial silicon substrate 40 has plural parallel spaced trenches, such as trenches 41 and 42 therein. The trenches 41 and 42 have thin oxide liners 43 and 44 respectively and are filled with conductive polysilcon fillers 45 and 46 respectively.

[0042] After cleaning, and as shown in FIG. 7, there is a 600 Å titanium sputter as in FIG. 2, depositing titanium layer 50 on the tops of the mesas between the trenches. The titanium thickness is not critical.

[0043] Thereafter, and as shown in FIG. 8, there is a rapid thermal anneal in N2 as in FIG. 3, forming titanium silicide layer 51 and the titanium nitride layer 52.

[0044] Next a titanium etch is carried out as in FIG. 4 to remove the titanium nitride layer 52 and titanium metal 50, producing the structure shown in FIG. 9.

[0045] As next shown in FIG. 10, a boron implant is carried out at a low energy of about 10 keV and a low dose of 9E12 to 9E13 through the titanium silicide layer 51.

[0046] Thereafter, and as shown in FIG. 11, a rapid thermal anneal process is carried out as in FIG. 6 to drive boron into the silicon mesas between trenches.

[0047] The Schottky device is then completed with the usual manufacturing steps for front and back metals.

[0048] In carrying out the process, it is useful to consider the following techniques:

[0049] Pre-cleaning—The clean before titanium sputter and after oxide etch can be any pre-metal clean available in the industry, or no cleaning at all. For example any H2SO4, HCI, HF, NH4OH, NH4F-based cleaning solutions can be used. That is because during the first anneal, about 1000 Å of silicon is converted to silicide, and the actual Schottky interface is moved inside the silicon epi-layer, making the final structure virtually independent of the condition of the original silicon surface.

[0050] Ti Deposition—Any technique can be used for titanium deposition; sputtering and electron beam evaporation being the most common techniques used in the industry. Any thickness of the titanium layer can be used. 600 Å is an optimized thickness, chosen to maximize the thickness of the silicide layer created after the first anneal, and to minimize the amount of unreacted titanium. This layer is removed in any case by the following cleaning step, and, if not controlled, would unnecessarily reduce the life of the titanium target.

[0051] Anneal1—The first annealing step can be any thermal process (furnace, RTA), such that the actual wafer temperature does not exceed ˜750° C. At higher temperature, titanium starts reacting with thermal oxide. Removing the un-reacted titanium, by a wet etch, becomes very difficult and either a higher temperature of etchant solution or a longer etch time have to be used. Any inert carrier gas (nitrogen, argon, helium, forming gas) can be used during the anneal.

[0052] Ti Etch—The titanium etch after the first anneal can be any ammonium hydroxide and hydrogen peroxide-based solution. Etch time can vary, but etch temperature should not exceed about 80° C. to avoid excessively fast decomposition of the H2O2.

[0053] Implant—After the first anneal, any implant species that acts as a P-type dopant in N-type Silicon wafers (for N-type Silicon Schottky diodes) can be used. boron or BF2, are the most common materials used in the industry. Maximum energy can be 50 keV. Low energy and low doses are preferred because high energy and heavy ion doses create more damage. The dose can be as high as 1×1015 atoms/cm2.

[0054] Anneal 2—The purpose of the second anneal is to remove the implant damage and activate and slightly drive in the implanted species. Minimum annealing temperature can be as low as 700° C., and a maximum around 1200° C. Any thermal process (furnace, RTA), can be used for this step. Annealing should be performed in a neutral ambient (nitrogen, argon, helium, forming gas) to avoid oxidation of the silicide layer.

[0055] FIGS. 12A, 12B and 12C show the effect of the boron implant on the planar diode structure. The change in the forward voltage (V) to reverse current (I) trade off characteristics is related to the increase in barrier height with the boron implant dose (FIG. 12A). A small (10 mV) increase of barrier height is achieved for a boron dose up to 1E12 atoms/cm2 as shown in FIG. 12B, with a 30% reduction in leakage current. No increase in series resistance was observed (FIG. 12C), and the I-V curves of implanted and non-implanted samples track one another.

[0056] FIGS. 13A and 13B show the calculated boron diffusion profile after implant in FIGS. 5 and 10, and after a 30 second drive at 850° C. and at 10 kev for doses of 9E12 and 9E13 respectively. The thickness of the silicide is about 1000 Å. The boron profile (line 60) depends on the composition and actual thickness of the silicide. For an implant dose in the 1E12 range boron is barely confined within the silicide after drive in, and no change in barrier height is observed. Higher doses are substantially change the I-V trade-off characteristics.

[0057] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.

Claims

1. A Schottky diode having an adjusted barrier height comprising, a substrate of N− silicon having a Schottky contact surface region; a titanum silicide Schottky contact layer in contact with said contact surface; and a low dose boron implant beneath said titanium silicide layer to at least partly counter dope the N− silicon beneath said titanium silicide layer.

2. The device of claim 1, wherein said diode is a planar diode and said contact surface region extends across the full active surface of said diode.

3. The device of claim 1, wherein said diode is a trench device and said contact surface region is the surface atop the silicon mesas formed between adjacent trenches into said silicon.

4. The device of claim 1, wherein said boron implant has a dose of less than about 1E12 atoms/cm2.

5. The process of forming a Schottky barrier diode comprising the steps of forming a titanium silicide layer atop an N− silicon substrate, and thereafter implanting a low dose P type species material through said titanium silicide layer to counter dope the N− silicon beneath and in contact with said titanium silicide layer, thereby to adjust the barrier height of the Schottky contact to said substrate.

6. The process of claim 5, wherein said species is boron.

7. The process of claim 5, wherein said implant dose is less than about 1E12 atoms/cm2.

8. The process of claim 6, wherein said implant dose is less than about 1E12 atoms/cm2.

9. The process of claim 5, wherein said titanium silicide layer has a non-critical thickness of less than about 1000 Å and wherein said implant is carried out at a low accelerating energy of about 10 keV.

10. The process of claim 6, wherein said titanium silicide layer has a non-critical thickness of less than about 1000 Å and wherein said implant is carried out at a low accelerating energy of about 10 keV.

11. The process of claim 7, wherein said titanium silicide layer has a non-critical thickness of less than about 1000 Å and wherein said implant is carried out at a low accelerating energy of about 10 keV.

12. The process of claim 8, wherein said titanium silicide layer has a non-critical thickness of less than about 1000 Å and wherein said implant is carried out at a low accelerating energy of about 10 keV.