Claims
- 1. A process for fabricating a buried, laterally insulated zone of increased conductivity in a semiconductor substrate, having the following steps:providing a silicon substrate with a buried zone of increased conductivity; forming a reference layer on the substrate; patterning the reference layer; forming a trench with at least one shallow region and at least one deep region in the substrate; and filling the trench with silicon oxide insulation material and depositing the insulation material on the structure thus produced in an ozone-activated CVD process; selecting a material of the reference layer such that a growth rate of the insulation material on the reference layer is at least by a factor of two less than a growth rate of the insulation material on a surface of the trench to be covered, a ratio of a width of the deep region to a step height of the shallow region being approximately equal to 2*α/(α−1), where α corresponds to a ratio of the growth rate of the insulation material on the surface of the trench to be covered to the growth rate of the insulation material on the reference layer.
- 2. The process according to claim 1, wherein the reference layer is a layer selected from the group consisting of a silicon nitride layer, a titanium nitride layer, and a polysilicon layer.
- 3. The process according to claim 1, wherein the filling step is continued until a substantially planar surface is formed in the surroundings of the trench (6).
- 4. The process according to claim 1, which comprises forming at least one intermediate layer between the substrate and the reference layer.
- 5. The process according to claim 4, wherein the intermediate layer is an oxide layer.
- 6. The process according to claim 1, which further comprises carrying out thermal oxidation subsequently to the filling and depositing steps.
- 7. The process according to claim 1, which further comprises carrying out a liner oxidation process subsequently to the step of forming the trench.
- 8. The process according to claim 1, which further comprises, after the filling and depositing step, removing the insulation material from above a level of the reference layer.
- 9. The process according to claim 1, wherein the zone of increased conductivity is located at a given depth in the substrate, and wherein the trench is formed into the substrate to a depth below the zone of increased conductivity.
- 10. The process according to claim 1, wherein the trench is an annular trench disposed laterally of and completely enclosing at least a part of the zone of increased conductivity.
- 11. The process according to claim 1, which further comprises removing the insulation material from above a level of the reference layer by a CMP process.
Priority Claims (1)
Number |
Date |
Country |
Kind |
196 29 766 |
Jul 1996 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of copending International application No. PCT/DE97/01542, filed Jul. 22, 1997, which designated the United States.
US Referenced Citations (5)
Foreign Referenced Citations (4)
Number |
Date |
Country |
42 11 050 |
Oct 1993 |
DE |
0 537 001 |
Apr 1993 |
EP |
0 582 724 |
Feb 1994 |
EP |
0 647 968 |
Apr 1995 |
EP |
Non-Patent Literature Citations (1)
Entry |
Japanese Patent Abstract No. 05218031 (Tsukasa), dated Aug. 27, 1993. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/DE97/01542 |
Jul 1997 |
US |
Child |
09/237174 |
|
US |