Claims
- 1. A process for forming field isolation comprising the steps of:
- forming a pad layer over a semiconductor substrate;
- depositing an amorphous silicon layer over the pad layer;
- annealing the amorphous silicon layer;
- forming a silicon-rich silicon nitride layer over the amorphous silicon layer;
- patterning the silicon-rich silicon nitride layer to form a patterned silicon-rich silicon nil-ride layer including an opening and a silicon-rich silicon nitride member;
- thermally oxidizing the substrate underlying the opening to form a field isolation region within the opening; and
- removing the silicon-rich silicon nitride member, wherein the step of annealing is performed in a separate step from the step of forming the silicon-rich silicon nitride layer and before the step of thermally oxidizing.
- 2. The process of claim 1, wherein the step of forming the silicon-rich silicon nitride layer is performed such that the silicon-rich silicon nitride layer has a refractive index in a range of about 2.02-2.50.
- 3. The process of claim 1, wherein the step of forming the silicon-rich silicon nitride layer is performed such that the silicon-rich silicon nitride layer has a silicon concentration no higher than 50 percent.
- 4. The process of claim 1, wherein the step of forming the silicon-rich silicon nitride layer is performed such that the silicon-rich silicon nitride layer has a refractive index in a range of about 2.02-2.2.
- 5. The process of claim 1, wherein the step of forming the silicon-rich silicon nitride layer is performed such that the silicon-rich silicon nitride layer has a silicon concentration no higher than 20 percent.
- 6. The process of claim 1, further comprising a step of removing any remaining portion of the amorphous silicon layer after the step of thermally oxidizing.
- 7. The process of claim 1, wherein:
- the silicon-rich silicon nitride layer is formed to a thickness in a range of about 1000-2500 angstroms; and
- the pad layer is formed to a thickness no greater than about 40 percent of the thickness of the silicon-rich silicon nitride layer.
- 8. The process of claim 1, wherein the step of annealing comprises a step of annealing the amorphous silicon layer in a furnace at a temperature in a range of about 300-620 degrees Celsius for at least twenty minutes.
- 9. The process of claim 1, wherein the step of annealing comprises a step of annealing the amorphous silicon layer in a rapid thermal processor at a temperature in a range of about 300-800 degrees Celsius for at least five seconds.
- 10. The process of claim 1, wherein the step of annealing comprises a step of annealing the amorphous silicon layer between the steps of forming the silicon-rich silicon nitride layer and thermally oxidizing, wherein the step of annealing is performed at a temperature no higher than 620 degrees Celsius.
- 11. The process of claim 1, wherein the step of forming the silicon-rich silicon nitride layer is performed at a temperature no greater than 600 degrees Celsius.
- 12. The process of claim 1, wherein the step of forming the silicon-rich silicon nitride layer is performed using low pressure chemical vapor deposition at a temperature in a range of about 700-800 degrees Celsius.
- 13. The process of claim 1, wherein the step of forming the silicon-rich silicon nitride layer is performed by plasma deposition.
- 14. The process of claim 1, wherein the step of annealing comprises a first portion and a second portion, wherein:
- the first portion is performed in a furnace at a temperature in a range of about 300-620 degrees Celsius; and
- the second portion is performed in a rapid thermal processor at a temperature in a range of about 300-800 degrees Celsius.
- 15. The process of claim 1, further comprising a step of forming a first bipolar transistor and a second bipolar transistor after the step of thermally oxidizing, wherein the field isolation region lies adjacent to and between the first and second bipolar transistors.
RELATED APPLICATION
This is a divisional application of application, Ser. No. 08/200,029, filed on Feb. 22, 1994, now U.S. Pat. No. 5,580,815, which is a continuation-in-part of U.S. patent application Ser. No. 08/106,456 filed Aug. 12, 1993 now abandoned which is assigned to the current assignee hereof.
US Referenced Citations (14)
Foreign Referenced Citations (1)
Number |
Date |
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56-111239 |
Sep 1981 |
JPX |
Divisions (1)
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Number |
Date |
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Parent |
200029 |
Feb 1994 |
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Continuation in Parts (1)
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106456 |
Aug 1993 |
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