Claims
- 1. A method of manufacturing a semiconductor integrated circuit device, comprising steps of:providing a semiconductor substrate having a first conductivity type and having a first impurity concentration at a whole of a principal surface of said semiconductor substrate; forming an epitaxial layer of said first conductivity type on said principal surface; forming a well region of said first conductivity type in said epitaxial layer by introducing an impurity in said epitaxial layer through a surface of said epitaxial layer; forming a gate oxide film on a surface of said epitaxial layer; forming a floating gate electrode on said gate oxide film on said well region; and forming a control gate electrode over said floating gate electrode, wherein an impurity concentration of said well region is greater than both an impurity concentration of said epitaxial layer and said first impurity concentration.
- 2. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said epitaxial layer has substantially a same impurity concentration as a designed impurity concentration of said first impurity concentration.
- 3. A method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said semiconductor substrate is a relatively lightly doped semiconductor substrate.
- 4. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein an impurity concentration of said semiconductor substrate is about 1015 atoms/cm3.
- 5. A method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein a thickness of said epitaxial layer is within a range of 0.3 μm to 5 μm.
- 6. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a thickness of said epitaxial layer is within a range of 0.3 μm to 5 μm.
- 7. A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein said well region extends into said semiconductor substrate, such that an impurity concentration of said well region gradually decreases from said epitaxial layer into said semiconductor substrate through an interface portion therebetween.
- 8. A method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein said well region extends into said semiconductor substrate, such that an impurity concentration of said well region gradually decreases from said epitaxial layer into said semiconductor substrate through an interface portion therebetween.
- 9. A method of manufacturing a semiconductor integrated circuit device, comprising steps of:forming an epitaxial layer of a first conductivity type on a semiconductor substrate having said first conductivity type and having a first impurity concentration at a whole of said principal surface of said semiconductor substrate, such that said epitaxial layer is formed on said principal surface of said first impurity concentration, wherein a thickness of said epitaxial layer is within a range of 0.3 μm to 5 μm; forming a well region in said epitaxial layer by introducing an impurity in said epitaxial layer through a surface of said epitaxial layer; forming a gate oxide film of a MISFET on a surface of said epitaxial layer; forming a floating gate electrode of said MISFET on said gate oxide film on said well region; and forming a control gate electrode of said MISFET over said floating gate electrode, wherein said first impurity concentration is lower than an impurity concentration of a portion of said well region where a channel region of said MISFET is formed.
- 10. A method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein said epitaxial layer has substantially a same impurity concentration as a designed impurity concentration of said first impurity concentration.
- 11. A method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein a memory cell of an EEPROM comprises said MISFET.
- 12. A method of manufacturing a semiconductor integrated circuit device including a memory cell having a floating gate electrode and a control gate electrode, comprising steps of:providing a semiconductor substrate having a first conductivity type and having a first impurity concentration at a whole of a principal surface of said substrate; forming an epitaxial layer of said first conductivity type on said principal surface such that said epitaxial layer has a thickness within a range of 0.3μ to 5μ; forming a well region of said first conductivity type in said epitaxial layer by introducing an impurity in said epitaxial layer through a surface of said epitaxial layer such that an impurity concentration of said well region is greater than both an impurity concentration of said epitaxial layer and said first impurity concentration; forming a gate oxide film of said memory cell on a surface of said epitaxial layer by oxidation of said surface of said epitaxial layer; and forming a floating gate electrode of said memory cell on said gate oxide film on said well region.
- 13. A method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein said semiconductor substrate provided includes a gettering layer formed on a back surface of a semiconductor substrate body.
- 14. A method of manufacturing a semiconductor integrated circuit device including an MISFET, of a memory cell, having a floating gate electrode and a control gate electrode, comprising steps of:providing a semiconductor substrate having a first conductivity type and having a first impurity concentration at a whole of a principal surface of said substrate; forming an epitaxial layer of said first conductivity type on said principal surface such that said epitaxial layer has a thickness within a range of 0.3μ to 5μ; forming a well region of said first conductivity type in said epitaxial layer by introducing an impurity in said epitaxial layer through a surface of said epitaxial layer such that said first impurity concentration is lower than an impurity concentration of a portion of said well region where a channel region of said MISFET is to be formed; forming a gate oxide film of said memory cell on a surface of said epitaxial layer by oxidation of said surface of said epitaxial layer; and forming a floating gate electrode of said memory cell on said gate oxide film on said well region.
- 15. A method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein said semiconductor substrate provided includes a gettering layer formed on a back surface of a semiconductor substrate body.
- 16. A method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein said semiconductor substrate provided includes a gettering layer formed on a back surface of a semiconductor substrate body.
- 17. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said semiconductor substrate provided includes a gettering layer formed on a back surface of a semiconductor substrate body.
Priority Claims (2)
Number |
Date |
Country |
Kind |
6-176872 |
Jul 1994 |
JP |
|
6-265529 |
Oct 1994 |
JP |
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Parent Case Info
This application is a Continuation application of application Ser. No. 08/934,774, filed Sep. 22, 1997, U.S. Pat. No. 6,043,114 which is a Divisional application of application Ser. No. 08/508,483, filed Jul. 28, 1995 abandoned.
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Non-Patent Literature Citations (3)
Entry |
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Yamaguchi, et al., “Process integration and device performance of a submicrometer BiCMOS with 16-GHz f (t) double Poly-Bipolar devices”, IEEE Transactions on Electron Devices, vol. 36, No. 5, pp. 890-896. |
Continuations (1)
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Number |
Date |
Country |
Parent |
08/934774 |
Sep 1997 |
US |
Child |
09/513349 |
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US |