Claims
- 1. A method of manufacturing a semiconductor integrated circuit device, comprising steps of:providing a semiconductor substrate having a first conductivity type and having a predetermined impurity concentration at a whole of a principal surface of said substrate, wherein said semiconductor substrate has a size as large as 300 mm; forming an epitaxial layer of said first conductivity type on said principal surface, such that said epitaxial layer contacts said principal surface of said predetermined impurity concentration and has a same impurity concentration as a designed impurity concentration of said predetermined impurity concentration, said epitaxial layer being formed to have a thickness within a range of 0.3μ to 5μ; forming a well region of said first conductivity type in said epitaxial layer by introducing an impurity in said epitaxial layer through a surface of said epitaxial layer, such that an impurity concentration of said well region is greater than both an impurity concentration of said epitaxial layer and said predetermined impurity concentration; forming a gate oxide film of an MISFET on a surface of said epitaxial layer by oxidation of said surface of said epitaxial layer; and forming a gate electrode of said MISFET on said gate oxide film on said well region.
- 2. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first conductivity type is p-type conductivity.
- 3. A method of manufacturing a semiconductor integrated circuit device, comprising steps of:providing a semiconductor substrate having a first conductivity type and having a first impurity concentration at a whole of a principal surface of said substrate, wherein said semiconductor substrate has a size as large as 300 mm; forming an epitaxial layer of said first conductivity type on said principal surface, such that said epitaxial layer has a thickness within a range of 0.3μ to 5μ; forming a well region of said first conductivity type in said epitaxial layer by introducing an impurity in said epitaxial layer through a surface of said epitaxial layer, such that an impurity concentration of said well region is greater than both an impurity concentration of said epitaxial layer and said first impurity concentration; forming a gate oxide film of an MISFET on a surface of said epitaxial layer by oxidation of said surface of said epitaxial layer; and forming a gate electrode of said MISFET on said gate oxide film on said well region.
- 4. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first conductivity type is p-type conductivity.
Priority Claims (2)
Number |
Date |
Country |
Kind |
6-176872 |
Jul 1994 |
JP |
|
6-265529 |
Oct 1994 |
JP |
|
Parent Case Info
This application is a Continuation application of application Ser. No. 09/513,349, filed Feb. 25, 2000, which is a Continuation application of application Ser. No. 08/934,774, filed Sep. 22, 1997, now U.S. Pat. No. 6,043,114, which is a Divisional application of application Ser. No. 08/508,483, filed Jul. 28, 1995 now ABN.
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Continuations (2)
|
Number |
Date |
Country |
Parent |
09/513349 |
Feb 2000 |
US |
Child |
10/002147 |
|
US |
Parent |
08/934774 |
Sep 1997 |
US |
Child |
09/513349 |
|
US |