1. Field of the Invention
The present invention discloses a process monitoring system, and more particularly, a process monitoring circuit and process monitoring method to be used for applications such as generation of threshold voltage for non-volatile memory.
2. Description of the Prior Art
For non-volatile memory, each memory cell stores one bit of information. A way to store the one bit is by supporting two states of the memory cell—one state represents a logical “0” and the other state represents a logical “1”. The two states are implemented by having a floating gate above the channel of the memory cell and having two valid states for the amount of charge stored within the floating gate. Typically, one state with zero charge in the floating gate represents the logical “1” and another state with some amount of negative charge in the floating gate represents the logical “0”. Having negative charge in the floating gate causes the threshold voltage of a transistor of the cell to increase. The threshold voltage is the voltage applied to the gate of the transistor in order to cause the transistor to conduct. The stored bit is read by checking the threshold voltage of the memory cell: if the threshold voltage is at a high state then the bit value is “0” and if the threshold voltage is at a low state then the bit value is “1”. If the memory cell stores a value of “1”, the cell typically has a negative threshold voltage. Similarly, if the cell stores a value of “0”, the cell typically has a positive threshold voltage. To correctly identify in which of the two states the memory cell is currently located, a comparison is made against a reference voltage value that is in the middle of the two states, and thus determining if the threshold voltage is below or above the reference value.
Non-volatile memories are not exactly identical in their characteristics and behavior due to variation of fabrication parameters. The variations are referred to as process corner. A group of non-volatile memories having been fabricated at the same time does produce non-volatile memories having the same process corner and thus affecting the threshold voltage of each of the non-volatile memories. Therefore, same programming operation may not be applied to the non-volatile memories. If an incompatible threshold voltage is used for the programming operation, though the cell may work properly in the beginning, after a large number of programming cycles, i.e., 100 times, the non-volatile memory has a tendency to have a spurious programming operation due to the buildup of offset in the threshold voltage.
A first embodiment of a process monitoring circuit is disclosed. The process monitoring circuit comprises a bandgap reference circuit configured to generate a bandgap reference voltage; a clock generator configured to generate a first clock, a negative bias circuit coupled between the bandgap reference circuit and the clock generator and configured to generate a negative bias voltage according to the bandgap reference voltage for stabilizing operation of the clock generator, a temperature insensitive oscillator configured to generate a second clock, a low dropout voltage regulator coupled to the temperature insensitive oscillator and configured to generate a zero temperature coefficient voltage for stabilizing operation of the temperature insensitive oscillator, a counter coupled to the clock generator and the temperature insensitive oscillator and configured to count number of pulses of the second clock within each duty cycle of the first clock so as to generate a counted number, a comparison circuit coupled to the counter and configured to compare the counted number with at least one reference number to generate a comparison result, and a charge pump coupled to the comparison circuit and configured to generate an output voltage according to the comparison result.
A second embodiment of the process monitoring circuit is disclosed. The process monitoring circuit comprises a bandgap reference circuit configured to generate a bandgap reference voltage, a clock generator configured to generate a first clock, a negative bias circuit coupled between the bandgap reference circuit and the clock generator and configured to generate a negative bias voltage according to the bandgap reference voltage for stabilizing operation of the clock generator, a pulse width generator coupled to the clock generator and configured to generate a third clock according to the first clock, a temperature insensitive oscillator configured to generate a second clock, a low dropout voltage regulator coupled to the temperature insensitive oscillator and configured to generate a zero temperature coefficient voltage for stabilizing operation of the temperature insensitive oscillator, a counter coupled to the pulse width generator and the temperature insensitive oscillator and configured to count number of pulses of the second clock within each duty cycle of the third clock so as to generate a counted number, a comparison circuit coupled to the counter and configured to compare the counted number with at least one reference number to generate a comparison result, and a charge pump coupled to the comparison circuit and configured to generate an output voltage according to the comparison result.
A method of process monitoring according to the embodiment of the present invention is disclosed. The method of process monitoring comprises generating a bandgap reference voltage, generating a negative bias voltage according to the bandgap reference voltage, generating a first reference current for a clock generator according to the negative bias voltage, generating a first clock according to the first reference current, generating a zero temperature coefficient voltage according to the negative bias voltage, generating a second clock by the temperature insensitive oscillator according to the zero temperature coefficient voltage, generating a counted number according to the first clock and the second clock, comparing the counted number with at least one reference number to generate a comparison result, and generating an output voltage according to the comparison result.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
For an integrated circuit, three parameters that affect operation include process corner, voltage variation and temperature variation. Process corner is the variation of fabrication parameters applied to semiconductor wafer during fabrication of an integrated circuit. Possible corners may include: typical-typical (TT), fast-fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). The present invention discloses a process monitoring system for generating an output voltage that is not affected by voltage variation and temperature variation. The process monitoring circuit shall generate the output voltage for the integrated circuit with respect to the process corner that the integrated circuit belongs to.
Please refer to
Please refer to
The difference between the first embodiment and the second embodiment of the process monitoring system is the use of the pulse width generator 210. The pulse width generator 210 is to be used if first clock does not generate a clock period having twice the length of clock period of the second clock. The pulse width generator 210 shall generate the third clock according to number of pulses of the first clock. The third clock generated will have clock period at least two times longer than that of the second clock.
The bandgap reference circuit 110 is a temperature independent voltage reference circuit. The reference voltage produced is fixed and is regardless to power supply variation, temperature variation and load variation. A typical bandgap reference circuit may have an output voltage of 1.25V which is close to the theoretical bandgap of silicon at 0 Kelvin.
The negative bias circuit 120 is a type of circuit that can be used to establish a predetermined voltage or current at various points of an integrated circuit to establish proper operating conditions for a sub-circuit. The word biasing means a systematic deviation of a value from a reference value. For the present invention, the negative bias circuit 120 is set to generate the negative bias voltage VNB corresponding from a reference value, the bandgap reference voltage Vbg. The negative bias circuit 120 supplies the clock generator 130 and the low dropout regulator 140 with a steady voltage, the negative bias voltage VNB.
Please refer to
As shown in
As shown in
According to the second embodiment of the present invention as shown in
The low dropout regulator 140 is a circuit used to generate the zero temperature coefficient voltage VZTC according to the negative bias voltage VNB. The low dropout regulator 140 is a DC linear voltage regulator which can operate with a very small input-output differential voltage. The advantage of using the low dropout regulator 140 includes a low operating voltage, high operation efficiency and low heat dissipation. The main components of the low dropout regulator 140 are a power FET and a differential amplifier. If the zero temperature coefficient voltage VZTC rises too high relative to the negative bias voltage VNB, the drive to the power FET changes to maintain the zero temperature coefficient voltage VZTC at a constant value. The bandgap reference voltage Vbg may also be used by the low dropout regulator 140 as a reference voltage in order to generate the zero temperature coefficient voltage VZTC.
The temperature insensitive oscillator 150 may include a bias current generator 310 and a ring oscillator 320. The temperature insensitive oscillator 150 is configured to generate the second clock that has a zero temperature coefficient. The temperature insensitive oscillator 150 can generate the second clock with constant frequency regardless of change in temperature according to the zero temperature coefficient voltage VZTC generated by the low dropout regulator 140.
The counter 160 is a circuit which stores the number of times a particular event has occurred in relation to a reference clock signal. For the process monitoring system, the particular event to be counted are pulses produced by the second clock. And the reference clock signal to be used for the first embodiment of the process monitoring system is the first clock generated using the clock generator 130. For the second embodiment of the process monitoring system, the reference clock signal to be used by the counter 160 is the third clock signal generated by the pulse width generator 210 according to the first clock. The counter 160 will generate the counted number which is the number of times the pulse of the second clock occurs during a period of time according to the reference clock signal, which may be the first clock or the third clock. The count number is a number generated by the process monitoring system that corresponds to the process corner of the circuit regardless of the voltage variation and the temperature variation.
The comparison circuit 170 may be a lookup table (LUT) component which is used to generate a specific set of outputs according to a particular input combination. The lookup table can be implemented using universal data blocks (UDB) with programmable logic devices. For the process monitoring circuit, the count number generated by the counter 160 is compared to a plurality of number ranges with each range corresponding to a process corner to which the circuit operates under. Result of the comparison circuit 170 is a binary address that corresponds to the process corner of the circuit.
The charge pump 180 is a kind of DC to DC converter that uses capacitors as energy elements to create either a higher or lower voltage power source. The charge pump 180 may include a controller, a plurality of switches, and a plurality of capacitors. An external voltage source, a clock signal and a control signal can be coupled to the charge pump 180. The charge pump 180 uses at least one switching device to control connections of voltages to capacitors. Depending on the controller and circuit topology of the charge pump 180, the charge pump 180 can double voltages, triple voltages, halve voltages, invert voltages, fractionally multiply or scale voltages such as ×3/2, ×4/3, ×2/3, etc. and generate arbitrary voltages. The control signal is the binary address resulting from the comparison circuit 170. Value of the output voltage VO is generated by the charge pump 180 corresponding to the binary address from the comparison circuit 170. Note that the external voltage source may be the bandgap reference voltage Vbg and the clock signal for the charge pump 180 may be the first clock.
The operation of the process monitoring system is further illustrated in
The second clock signal is generated corresponding to the low dropout regulator 140 and the temperature insensitive oscillator 150. Compensation for the voltage variation and temperature is addressed in generating the second clock. Compensation for the process variation is addressed in generating the first clock. The frequency of the second clock shall correspond to a process corner of a monitored circuit.
Please refer to
As shown in
As shown in
As shown in
As shown in
As shown in
The binary address which is the comparison result from the comparison circuit 170 is then inputted to the charge pump 180. The binary address will allow the charge pump 180 to generate the output voltage VO according to the process corner of the monitored circuit.
Note that illustrated waveforms and look up table above are only examples to illustrate the aspects of the present invention for clarity and not intended to limit the scope of the invention.
Please refer to
Step 1002: The bandgap reference circuit 110 generates the bandgap reference voltage Vbg;
Step 1004: The negative bias circuit 120 generates the negative bias voltage VNB according to the bandgap reference voltage Vbg;
Step 1006: The current generator 310 generates the process insensitive current Ibias for the clock generator 130 according to the negative bias voltage VNB;
Step 1008: The ring oscillator 320 generates the first clock according to the process insensitive current Ibias;
Step 1010: The low dropout regulator 140 generates the zero temperature coefficient voltage VZTC according to the negative bias voltage VNB;
Step 1012: The temperature insensitive oscillator 150 generates the second clock according to the zero temperature coefficient voltage VZTC
Step 1014: The counter 160 generates the counted number according to the first clock and the second clock;
Step 1016: The comparison circuit 160 compares the counted number with the plurality of reference numbers corresponding to the plurality of respective process corners to generate the comparison result according to the process corner of the monitored circuit; and
Step 1018: The charge pump 180 generates the output voltage VO according to the comparison result.
Please refer to
Step 1102: The bandgap reference circuit 110 generates the bandgap reference voltage Vbg;
Step 1104: The negative bias circuit 120 generates the negative bias voltage VNB according to the bandgap reference voltage Vbg;
Step 1106: The current generator 310 generates the process insensitive current Ibias for the clock generator 130 according to the negative bias voltage VNB;
Step 1108: The ring oscillator 320 generates the first clock according to the process insensitive current Ibias;
Step 1110: The pulse width generator 210 generates the third clock according to the first clock;
Step 1112: The low dropout regulator 140 generates the zero temperature coefficient voltage VZTC according to the negative bias voltage VNB;
Step 1114: The temperature insensitive oscillator 150 generates the second clock according to the zero temperature coefficient voltage VZTC
Step 1116: The counter 160 generates the counted number according to the third clock and the second clock;
Step 1118: The comparison circuit 160 compares the counted number with the plurality of reference numbers corresponding to the plurality of respective process corners to generate the comparison result according to the process corner of the monitored circuit; and
Step 1120: The charge pump 180 generates the output voltage VO according to the comparison result.
The present invention discloses a process monitoring system that determines the process corner of a monitored circuit. The monitored circuit may be a non-volatile memory. And an output voltage VO generated by the process monitoring system may be used as a threshold voltage for programming of the non-volatile memory. The use of the process monitoring system will eliminate occurrence of spurious programming operation since the threshold voltage applied to the non-volatile memory has been generated according to process corner the non-volatile memory falls under. The process monitoring system has also accounted for voltage variation, and temperature variation when generating the threshold voltage for the non-volatile memory.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
3663828 | Low | May 1972 | A |
3818402 | Golaski | Jun 1974 | A |
4163944 | Chambers | Aug 1979 | A |
4245355 | Pascoe | Jan 1981 | A |
4409608 | Yoder | Oct 1983 | A |
4816784 | Rabjohn | Mar 1989 | A |
5159205 | Gorecki | Oct 1992 | A |
5208725 | Akcasu | May 1993 | A |
5212653 | Tanaka | May 1993 | A |
5315230 | Cordoba | May 1994 | A |
5406447 | Miyazaki | Apr 1995 | A |
5446309 | Adachi | Aug 1995 | A |
5499214 | Mori | Mar 1996 | A |
5583359 | Ng | Dec 1996 | A |
5637900 | Ker | Jun 1997 | A |
5638418 | Douglass et al. | Jun 1997 | A |
5760456 | Grzegorek | Jun 1998 | A |
5808330 | Rostoker | Sep 1998 | A |
5899570 | Darmawaskita et al. | May 1999 | A |
5923225 | De Los Santos | Jul 1999 | A |
5959820 | Ker | Sep 1999 | A |
6008102 | Alford | Dec 1999 | A |
6011386 | Li | Jan 2000 | A |
6081146 | Shiochi | Jun 2000 | A |
6172378 | Hull | Jan 2001 | B1 |
6194739 | Ivanov | Feb 2001 | B1 |
6246271 | Takada | Jun 2001 | B1 |
6285578 | Huang | Sep 2001 | B1 |
6291872 | Wang | Sep 2001 | B1 |
6370372 | Molnar | Apr 2002 | B1 |
6407412 | Iniewski | Jun 2002 | B1 |
6427226 | Mallick | Jul 2002 | B1 |
6448858 | Helms | Sep 2002 | B1 |
6452442 | Laude | Sep 2002 | B1 |
6456221 | Low | Sep 2002 | B2 |
6461914 | Roberts | Oct 2002 | B1 |
6480137 | Kulkarni | Nov 2002 | B2 |
6483188 | Yue | Nov 2002 | B1 |
6486765 | Katayanagi | Nov 2002 | B1 |
6509805 | Ochiai | Jan 2003 | B2 |
6518165 | Yoon | Feb 2003 | B1 |
6521939 | Yeo | Feb 2003 | B1 |
6545547 | Fridi | Apr 2003 | B2 |
6560306 | Duffy | May 2003 | B1 |
6588002 | Lampaert | Jul 2003 | B1 |
6593838 | Yue | Jul 2003 | B2 |
6603360 | Kim | Aug 2003 | B2 |
6608363 | Fazelpour | Aug 2003 | B1 |
6611223 | Low | Aug 2003 | B2 |
6625077 | Chen | Sep 2003 | B2 |
6630897 | Low | Oct 2003 | B2 |
6639298 | Chaudhry | Oct 2003 | B2 |
6653868 | Oodaira | Nov 2003 | B2 |
6668358 | Friend | Dec 2003 | B2 |
6700771 | Bhattacharyya | Mar 2004 | B2 |
6720608 | Lee | Apr 2004 | B2 |
6724677 | Su | Apr 2004 | B1 |
6756656 | Lowther | Jun 2004 | B2 |
6795001 | Roza | Sep 2004 | B2 |
6796017 | Harding | Sep 2004 | B2 |
6798011 | Adan | Sep 2004 | B2 |
6806698 | Gauthier et al. | Oct 2004 | B2 |
6810242 | Molnar | Oct 2004 | B2 |
6814485 | Gauthier et al. | Nov 2004 | B2 |
6822282 | Randazzo | Nov 2004 | B2 |
6822312 | Sowlati | Nov 2004 | B2 |
6833756 | Ranganathan | Dec 2004 | B2 |
6841847 | Sia | Jan 2005 | B2 |
6847572 | Lee | Jan 2005 | B2 |
6853272 | Hughes | Feb 2005 | B1 |
6876056 | Tilmans | Apr 2005 | B2 |
6885534 | Ker | Apr 2005 | B2 |
6893154 | Gold et al. | May 2005 | B2 |
6901126 | Gu | May 2005 | B1 |
6905889 | Lowther | Jun 2005 | B2 |
6909149 | Russ | Jun 2005 | B2 |
6927664 | Nakatani | Aug 2005 | B2 |
6958522 | Clevenger | Oct 2005 | B2 |
7009252 | Lin | Mar 2006 | B2 |
7027276 | Chen | Apr 2006 | B2 |
7205612 | Cai | Apr 2007 | B2 |
7262069 | Chung | Aug 2007 | B2 |
7365627 | Yen | Apr 2008 | B2 |
7368761 | Lai | May 2008 | B1 |
7388447 | Potanin | Jun 2008 | B1 |
7391276 | Sakaguchi | Jun 2008 | B2 |
7405642 | Hsu | Jul 2008 | B1 |
7619486 | Lesea | Nov 2009 | B1 |
7672100 | Van Camp | Mar 2010 | B2 |
7961027 | Chen et al. | Jun 2011 | B1 |
8369170 | Chen | Feb 2013 | B2 |
8662747 | Yeh | Mar 2014 | B2 |
20020019123 | Ma | Feb 2002 | A1 |
20020036545 | Fridi | Mar 2002 | A1 |
20020188920 | Lampaert | Dec 2002 | A1 |
20030076636 | Ker | Apr 2003 | A1 |
20030127691 | Yue | Jul 2003 | A1 |
20030155903 | Gauthier et al. | Aug 2003 | A1 |
20030156622 | Gold et al. | Aug 2003 | A1 |
20030183403 | Kluge | Oct 2003 | A1 |
20050068112 | Glenn | Mar 2005 | A1 |
20050068113 | Glenn | Mar 2005 | A1 |
20050087787 | Ando | Apr 2005 | A1 |
20060006431 | Jean | Jan 2006 | A1 |
20060108694 | Hung | May 2006 | A1 |
20060267102 | Cheng | Nov 2006 | A1 |
20070102745 | Hsu | May 2007 | A1 |
20070210416 | Hsu | Sep 2007 | A1 |
20070234554 | Hung | Oct 2007 | A1 |
20070246801 | Hung | Oct 2007 | A1 |
20070249294 | Wu | Oct 2007 | A1 |
20070296055 | Yen | Dec 2007 | A1 |
20080084249 | Noguchi | Apr 2008 | A1 |
20080094166 | Hsu | Apr 2008 | A1 |
20080185679 | Hsu | Aug 2008 | A1 |
20080189662 | Nandy | Aug 2008 | A1 |
20080200132 | Hsu | Aug 2008 | A1 |
20080299738 | Hsu | Dec 2008 | A1 |
20080303623 | Hsu | Dec 2008 | A1 |
20090029324 | Clark | Jan 2009 | A1 |
20090201625 | Liao | Aug 2009 | A1 |
20100279484 | Wang | Nov 2010 | A1 |