The present invention relates generally to integrated circuit design and in particular to an automatic design translation tool.
The use of computer design simulation programs to aid in the design of integrated circuits is commonly used in the electronic design automation (EDA) industry. Typically a design simulates a process in forming a desired integrated circuit. Often it is desired to migrate analog and RF intellectual Property (IP) from one process to another process for various reasons. Such reasons include, cost reduction, performance improvement, capacity improvement and IP up-integration into other systems.
Traditionally, the migration of analog and RF IP across different processes is accomplished with conventional hand translation, manual circuit retuning and calibration, and drawing layouts from scratch by analog and RF design engineers. These are very time consuming, tedious and costly tasks. There is a need in the art for an improved method of migrating analog and RF IP across different processes in designing integrated circuits.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved method of migrating analog and RF IP across different processes in designing integrated circuits
The above-mentioned problems and other problems are resolved by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method of designing devices in integrated circuits is disclosed. The method comprises translating select device parameters in a first database associated with a first process to device parameters in a second database associated with a second process and displaying a design based on the device parameters in the second database.
In another embodiment, a method of translating an integrated circuit design in a first process to a second process is disclosed. The method comprises setting translations options. Reading original schematic information. Translating schematic information. Reading original layout information. Translating layout information and outputting parameters of translated schematic and layout information.
In further another embodiment, a computer-readable medium including instructions for simulating the design of an integrated circuit from one process to another process is disclosed. The computer-readable medium includes instructions for processing translation options. Reading original schematic information. Translating schematic information. Reading original layout information. Translating layout information and outputting parameters of translated schematic and layout information.
The present invention can be more easily understood and further advantages and uses thereof more readily apparent, when considered in view of the description of the preferred embodiments and the following figures in which:
In accordance with common practice, the various described features are not drawn to scale but are drawn to emphasize specific features relevant to the present invention. Reference characters denote like elements throughout Figures and text.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims and equivalents thereof.
Embodiments of the present invention provide a translation tool that migrates analog and RF (intellectual property) IP across integrated circuits processes to boost design productivity. This is accomplished by translating all databases including schematic and layout designs from one process to another. For example, the translation tool can translate original schematic and layout that were designed in one process to a schematic and layout database in another process. The new schematic database preserves almost all critical component parameters such as resistance, capacitance, transistor size and all original connectivity and is simulation ready right after the translation. In one embodiment of the present invention, the translated layout database preserves all mapped layers and devices with proper location and conductivity and is ready to restore the layout connectivity from schematic by using a connectivity-based layout tool. The translation tools of the present invention also provide means for designers to probe and compare the original design component parameters easily in the new design database and environment without having to open the original design. An example of a translation process in which the current invention is applicable is the translation of one wireless local area network (WLAN) transceiver from an internal pure silicon BiCMOS process “process 1” to another SiGe BiCMOS process “process 2” with exact product specification requirements.
The present invention maps similar devices and mask layers from one process to another. The device characteristics, models and component description format (CDF) parameters have to be carefully evaluated so that similar components and CDF parameters can be mapped. Also, the processes have to be carefully examined so similar mask layers can be mapped as well.
One common problem is resistor sheet rho (or area resistance) and capacitor area capacitance normally doesn't match between processes, so in one embodiment of the present invention there are options to preserve either resistance/capacitance or geometry. In particular, in order to keep electrical consistency of the schematic design, the resistance and capacitance are typically preserved and in regards to layouts, the geometry, such as length and width, are preserved.
In various embodiments of the present invention, higher-level schematic requirements are included to keep conductivity in the schematic with correct device rotation, polarity, program node and inherited connection as well as adding extra or removing redundant wires automatically. These higher level embodiments, layout requirements typically include correct device layout placement location and rotation, ability to use connectivity-based layout editing tool to restore the conductivity from the schematic after translation, and automatic grid and diagonal line mode check correction.
After translation, there are times designers want to go back to check the original design CDF parameters. Embodiments of the present invention allow the designers to do this without launching a separate design session and opening the original design in a different window. Instead, in other embodiments, the original device CDF parameters are preserved in the translated design as data base properties. These properties can then be displayed side by side with the new CDF parameters for comparison reasons without opening a separate design session.
Limitations are generally identified before implementation, so they can be dealt with later. Limitations may include unmatched devices, CDF parameters, nodes and mask layers. In one embodiment, reports are generated when a limitation is encountered during the translation process.
An example of a process translation is the translation between process 1 and process 2. Examples of devices translated between process 1 and process 2 are provided in Table 1.
Examples of layers translated between process 1 and process 2 are shown in Table 2.
Know limitations of process 1 to process 2 include: 1. The device parameter limits are different between process 1 and process 2. For example, capacitor minimum 1/w in process 1 is 5 um, while in process 2 they are 8 um, so all process 1 min caps with 1/w less than 5 um will be set to 8 um after translation. The npn device maximum number of stripes in process 1 is 6, while in process 2 it is 2. So any number of strips larger than 2 in process 1 will be set to 2 in process 2. There is no limitation in npn emitter width, but process 2 imposes a 50 um maximum, so any emitter width larger than 50 um in process 1 will be set to 50 um in process 2. 2. All Pwell, NBL and substrate nodes will be mapped between process 1 and process 2 devices if applicable, however, in some cases, there are no correspondence, then the process 2 device will use the default Pwell, NBL and substrate node connection. In one embodiment you must manually connect them for the design.
Referring to
An example of a graphical user interface (GUI) 300 to initiate a translation of one embodiment of the present invention is illustrated in
An example of a layout 800 before translation is illustrated in
As described above, embodiments of the present invention map mask layers and map device parameters between two different processes. Some embodiments have callbacks that can be triggered. Some embodiments provide an option to add extra interconnect layers. Further embodiments, allow for the addition and deletion of wires automatically to keep the schematic design electrically correct. Moreover, other embodiments preserve instance names in both schematic and layout so that layout conductivity can be restored after translation. Still further embodiments, automatically grid and line mode (diagonal) check and provide corrections.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.