Processor and Methods Configured to Provide a Low-Complexity Input/Output Pruning Fast Fourier Transform

Abstract

In some embodiments, a circuit may include an input configured to receive a signal and a radix-r input/output pruning fast Fourier transform (FFT) processing element coupled to the input. The radix-r input/output pruning FFT processing element may be configured to remove FFT operations on input values of zero within the signal and to determine a discrete Fourier Transform (DFT) output having fewer output values than a number of input values of the signal.

Description

FIELD

The present disclosure is generally related to digital signal processing systems configured to perform fast Fourier transformations (FFT), and more particularly to a low-complexity input/output pruning FFT.

BACKGROUND

Input pruning FFTs are commonly used in the padded FFT process which is known as the up-sampling process in digital signal processing that consists of extending a signal (or spectrum) with zeros. By doing so, this can increase the time sampling which is known as the time domain interpolation that people commonly use, and which is translated into forcing the FFT algorithm to sample the spectrum at smaller frequency intervals.

SUMMARY

FFTs algorithms are used in digital signal processing which break down complex signals into elementary components and where the transform length N, is decomposed into arbitrary factors (N=r1, r2, . . . , rk). Input Pruning FFT's are efficient Fast Fourier Transform (FFT), where the efficiency can be increased by removing operations on input values which are zero. Furthermore, Output pruning FFT is a method used to compute a discrete Fourier transform (DFT) where only a subset of the outputs is needed. In this embodiments, we will propose a generalized radix-r input-output pruning FFT, which will compute efficiently the selected spectrum's bin of a sequence of size N that contains M consecutive non-zero input points from which only Lo outputs are desired.

In some embodiments, a circuit may include an input configured to receive a signal and a radix-r input/output pruning fast Fourier transform (FFT) processing element coupled to the input. The radix-r input/output pruning FFT processing element may be configured to remove FFT operations on input values of zero within the signal and to determine a discrete Fourier Transform (DFT) output having fewer output values than a number of input values of the signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a portion of a system including a digital signal processor configured to provide a generalized radix-r input/output pruning FFT, in accordance with certain embodiments of the present disclosure.

FIG. 2 depicts a graph of real operations reduction versus input pruning for the generalized radix-r input/output pruning FFT of FIG. 1.

FIG. 3 depicts a graph of a complexity ratio of the generalized radix-r input/output pruning FFT according to some embodiments of the present disclosure versus a conventional input pruning FFT.

FIG. 4 depicts a graph of a number of operations versus a number of output elements for the generalized radix-r input/output pruning FFT according to some embodiments of the present disclosure versus a pruning FFT implementation.

FIG. 5 depicts a graph of a reduction ratio of operations versus a number of output elements, for the generalized radix-r input/output pruning FFT according to some embodiments of the present disclosure versus a pruning FFT implementation.

FIG. 6 depicts a graph representing a magnified version of the graph of FIG. 5.

FIG. 7 depicts a graph of signal-to-quantization-noise ratio (SQNR) in decibels versus number of output elements without filtering for the generalized radix-r input/output pruning FFT, in accordance with some embodiments of the present disclosure.

FIG. 8 depicts a graph of signal-to-quantization-noise ratio (SQNR) in decibels versus number of output elements with filtering for the generalized radix-r input/output pruning FFT, in accordance with some embodiments of the present disclosure.

FIG. 9 depicts a graph of a number of operations versus number of input/output elements for the generalized radix-r input/output pruning FFT according to some embodiments of the present disclosure versus a pruning FFT implementation.

FIG. 10 depicts a graph of the reduction ratio of operations versus the number of output elements for the generalized radix-r input/output pruning FFT, in accordance with some embodiments of the present disclosure.

FIGS. 11 and 12 depict the software implementation of sequences that have L_i (multiple of the FFT radix-r) consecutive non-zero input points at any position n (n is multiple of the FFT radix-r) within the sequence and not necessarily at the beginning.

In the following discussion, the same reference numbers are used in the various embodiments to indicate the same or similar elements.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Theoretical aspects of the Pruning FFT (PFFT) have mainly concentrated on sequences that have L_i consecutive non-zero input points at the beginning. In many applications, such as the Orthogonal Frequency-Division Multiplexing (OFDM)-based Cognitive Radio may utilize FFT pruning, which can apply zeros efficiently to the inputs with arbitrary distributions.

In many applications, the percentage of required input/output bins may be very small. For instance, in the Third Generation Partnership Project (3GPP) LTE (Long Term Evolution) where the Orthogonal Frequency-Division Multiple Access OFDMA's symbol size is 1024 in which 12 users equally share the available 600 sub-carriers, only fifty of the 1024 FFT output bins (4.88%) may be used for each mobile terminal. These partial output/input cases are extraordinarily important for the future wireless systems and due to the fact that the pruning FFT (PFFT) can potentially achieve a significant speed improvement, which is desirable for a wide variety of applications such as: OFDMA (Orthogonal Frequency Division Multiplexing Access) cognitive radio, Very long instruction word (VLIW) digital signal processing (DSP) for mobile Applications, multi-channel OFDM systems, Multiple Input Multiple Output—Orthogonal Frequency Division Multiplexing (MIMO-OFDM) systems, and other applications.

Embodiments of a generalized radix-r input-output pruning FFT are described below that can be used to determine efficiently a selected spectrum's bin of a sequence input values of size N that contains M consecutive non-zero input points from which only L_o outputs are desired. In certain embodiments, the FFT may be used to compute a discrete Fourier transform (DFT) where only a subset of the outputs are needed, such that for a transform of size M which has been zero padded to a size N and where only L_o≤P consecutive outputs of the sized N transform are desired, the FFT can produce P consecutive outputs determined from the L_i non-zero consecutive inputs and where it is assumed that L_o/D_ip≈P=M/D_op. Other embodiments are also possible.

It should be appreciated that the generalized radix-r input/output pruning FFT disclosed herein may be implemented in a digital signal processor executing instructions, in a field-programmable gate array circuit, or in other hardware or software. Further, the operation or execution of the operations defined by the generalized radix-r input/output pruning FFT may improve the speed of the processing of the input data values, while reducing the number of operations and improving the overall efficiency of the circuit. Further, the resulting FFT output values may be used in a variety of contexts, including image processing, audio processing, encryption and decryption, and so on. One possible implementation of the FFT algorithm in a digital signal processor is described below with respect to FIG. 1.

FIG. 1 depicts a portion of a system 100 including a digital signal processor 102 configured to provide a generalized radix-r input/output pruning FFT, in accordance with certain embodiments of the present disclosure. The digital signal processor (DSP) 102 may include an input 104 to receive input data and may include an output 106 configured to provide FFT data as an ordered output.

In some embodiments, the DSP 102 may be configured to execute instructions including a generalized radix-r input/output pruning FFT 108, which may be configured to reduce the overall number of computations and memory accesses needed to determine the ordered FFT output. The FFT 108 is depicted as a block within the DSP 102 to indicate that the instructions were previously loaded by the DSP 102; however, the FFT 108 may be stored as instructions within a memory (read-only memory, random access memory, solid state memory, hard disc device, or any combination thereof) and may be loaded and executed by the DSP 102 as needed.

The basis of the radix-2 FFT is that a DFT can be divided into two smaller DFTs, each of which can be divided into two smaller DFTs, and so on, resulting in a combination of two points DFTs. Several methods can be used repeatedly to split the DFTs into smaller (two or four-point) core calculations. By appropriately breaking the DFT into partial DFTs in this way, the number of multiplications and the number of stages of the DFT calculation may be controlled. The number of stages often corresponds to the amount of global communication and/or memory accesses, and thus, a reduction in the number of stages is beneficial (in terms of speed and complexity).

The DSP 102 of FIG. 1 may be configured to apply a recursive general radix-r pruned FFT that is suitable for pruned FFTs at the input 104 where the pruning FFT applied by the DSP 102 has fewer complex multiplications than conventional pruning FFT algorithms. The recursive generalized radix-r pruned FFT shows substantial gain in the computational load and a significant increase in speed due to the reduction of the number of stages, which translates to a reduction in the number of data transfers and address computations.

The generalized radix-r pruned FFT can formulate the radix-r as composed engines with identical structures and a systematic means of accessing the corresponding multiplier coefficients. This formulation may enable the design of an engine with the lowest rate of complex multipliers and adders, which utilizes r or r−1 complex multipliers in parallel to implement each of the butterfly computations. There can be a simple mapping from the three indices (FFT stage, butterfly, and element) to the addresses of the multiplier coefficients needed in the DFT computation.

The DFT computation may be expressed as follows:

X _(k)=Σ_n=0^N-1x_(n)w_N^nk for k=0,1, . . . ,N−1,  (Equation 1)

where

$w_N^k=e^{-j\frac{2\pi k}{N}}.$

Considering that the number of consecutive input elements L_i that can be different from zero is L_i≤M=N/D_ip, where the variable N represents a number of input bits and the variable D_ip represents a threshold value. Equation 1 could be factorized as follows:

$\begin{array}{cc}\begin{array}{c}{X}_{\left(k\right)}=\sum _{n=0}^{N-1}x_{\left(n\right)}w_N^{\mathrm{nk}}\\ =\sum _{n_2=0}^{D_{\mathrm{ip}}-1}\sum _{n_1=0}^{M-1}x_{\left(n_1+{\mathrm{Mn}}_2\right)}w_N^{\left(n_1+{\mathrm{Mn}}_2\right)k}\\ =\sum _{n_2=0}^{D_{\mathrm{ip}}-1}w_N^{{\mathrm{Mn}}_2k}\sum _{n_1=0}^{M-1}x_{\left(n_1+{\mathrm{Mn}}_2\right)}w_N^{n_1k},\end{array}& \left(\mathrm{Equation}2\right)\end{array}$

with the following identities:

n=n ₁ +Mn ₂ k=k ₁ +D _ip k ₂

n ₁=0,1, . . . ,M−1 k₁=0,1, . . . ,D_ip−1

n ₂=0,1, . . . ,D_ip−1 k₂=0,1, . . . ,M−1.  (Equation 3)

The indices n₂ may determine the position of the nonzero consecutive inputs into the sequence where zeroes have been applied efficiently to the inputs with arbitrary distributions. With respect to input data sequences that have L_i consecutive non-zero input points at the beginning, the index n₂ can be set to zero. As a result, Equation 3 may be rewritten as follows:

X _(k)=Σ_n=0^M-1x_(n)w_N^n(k1+Dipk2)=Σ_n=0^M-1x_(n)w_N^nk1w_M^k2.  (Equation 4)

The computational complexity of Equation 4 can be performed in two ways. The following paragraphs elaborate on a comparison between these two methods.

A first method may be referred to as the “direct way” or “direct method” in which Equation 3 can be expressed as follows:

X _(k)=Σ_n=0^M-1x_(n)w_N^nk1w_M^k2=Σ_n=0^M-1y_(n)w_M^k2.  (Equation 5)

where y_(n) can be expressed as follows:

y _(n) =x _(n) w _N ^{nk 1} .  (Equation 6)

The computational complexity of Equation 4 can be determined as follows:

t _c-input =D _ip M(t_cFFTM+t_cm)=N(t_cFFTM+t_cm),  (Equation 7)

where the variable t_cFFT represents the complexity of the FFT algorithm of size M, and the variable t_cm is the complexity of the complex multiplier.

Logically, the optimal solution of Equation 5 may be obtained by optimizing the complexity of the FFT algorithm, where conventional researchers have been oriented in the optimization of the FFT algorithm, and not the complexity. According to embodiments of the present disclosure, a method of optimizing Equation 5 could be achieved by incorporating the twiddle factors w_N^nk1 and the adder tree matrices into a single stage of calculation.

In the following discussion, this simplification is demonstrated relative to a radix-2 FFT in which the split radix algorithm has been excluded. The complexity of the Cooley-Tukey (radix-2 FFT) algorithm in term of complex multiplication can be determined as follows:

$\begin{array}{cc}{t}_{cm\text{-}\mathrm{cooley}\text{-}\mathrm{tukey}}=\frac{M}{2}\left({\log }_2M\right)=\frac{M}{2}S_M,& \left(\mathrm{Equation}8\right)\end{array}$

where the variable S_M=log₂ M. On the other hand, each radix-2 butterfly may require two complex additions/subtractions. As a result, the total number of complex of additions/subtractions in t_ca/s DIT process may be determined as follows:

$\begin{array}{cc}{t}_{\mathrm{ca}/s\text{-}\mathrm{cooley}\text{-}\mathrm{tukey}}=\left(\frac{M}{2}\right){\log }_2M.& \left(\mathrm{Equation}9\right)\end{array}$

It should be appreciated that each complex multiplication can require six arithmetic operations, and each addition/subtraction can require two arithmetic operations. Therefore, the total number t_o of the arithmetic operations in the DIT Cooley-Tukey algorithm can be estimated as follows:

$\begin{array}{cc}{t}_{o\text{-}\mathrm{cooley}\text{-}\mathrm{tukey}}=6\left(\frac{M}{2}\right)S_M+2\left(\frac{M}{2}\right)\left(S_M\right)=4{\mathrm{MS}}_M=4M{\log }_2M,& \left(\mathrm{Equation}10\right)\end{array}$

Accordingly, the total amount of arithmetic operations required to compute the input pruning FFT can be determined as follows:

t _{c-input-Puning_Medina} =D _ip M(4MS_M+M+6)=N(4M log₂ M−3M+6).   (Equation 11)

According to some embodiments, the low-complexity input/output (I/O) pruning FFT utilizes radix-r DFT factorization, and Equation 5 can be re-written as follows:

$\begin{array}{cc}{X}_{\left(k_1,k_2\right)}={\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}\right)}w_N^{{\mathrm{rnk}}_1}w_M^{{\mathrm{rnk}}_2}+\dots +{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left({\mathrm{rn}}_1+\left(r-1\right)\right)}w_N^{\left(\mathrm{rn}+\left(r-1\right)\right)k_1}w_M^{\left(\mathrm{rn}+\left(r-1\right)\right)k_2}.& \left(\mathrm{Equation}12\right)\end{array}$

In the summations, the variables r, k₁ and k₂ are independents of the variable n₂. The variable w_M^rk2 in Equation 12 and be factorized, and, considering that w_M^rnk2=w_M/r^nk2, Equation 12 can be rewritten as follows:

$\begin{array}{cc}{X}_{\left(k_1,k_2\right)}={\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}\right)}w_{\frac{M}{r}}^{{\mathrm{nk}}_2}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}+w_M^{k_2}w_N^{k_1}{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}+1\right)}w_{\frac{M}{r}}^{{\mathrm{nk}}_2}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}+\dots +w_M^{\left(r-1\right)k_2}w_N^{\left(r-1\right)k_1}{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}+\left(r-1\right)\right)}w_{\frac{M}{r}}^{{\mathrm{nk}}_2}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}.& \left(\mathrm{Equation}13\right)\end{array}$

To subdivide the axis k₂ in Equation 13 in two new axes (v and l), it is assumed that k₂=v+lV with v=0, 1, . . . , V−1 and l=0, 1, . . . , r−1 where V=M/r. Therefore, the variable X_(k1+Dipk2) can be replaced using new indices v and l with k₁=0, 1, . . . , D_ip−1. As a result, Equation 13 can be rewritten in r equations as shown below in Equation 14, Equation 15, and Equation 16.

$\begin{array}{cc}{X}_{\left(k_1,v\right)}=\left[\begin{array}{c}{w}_M^0{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}\right)}w_{M/r}^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}+\\ \dots +w_M^{\left(r-1\right)v}w_N^{\left(r-1\right)k_1}{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}+\left(r-1\right)\right)}w_{M/r}^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}\end{array}\right]X_{\left(k_1,2v\right)}=\left[\begin{array}{c}{w}_M^0\sum _{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}\right)}w_{M/r}^{2\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}+\\ \dots +w_M^{\left(r-1\right)v}w_N^{\left(r-1\right)k_1}\sum _{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}+\left(r-1\right)\right)}w_{M/r}^{2\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}\end{array}\right]⋮X_{\left(k_1,\left(v+\left(r-1\right)V\right)\right)}=\hspace{1em}\hspace{1em}[\begin{array}{c}{w}_M^0{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}\right)}w_{M/r}^{n\left(v+\left(r-1\right)V\right)}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}+\\ \dots +w_M^{\left(r-1\right)\left(v+\left(r-1\right)V\right)}w_N^{\left(r-1\right)k_1}\\ {\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}+\left(r-1\right)\right)}w_{M/r}^{n\left(v+\left(r-1\right)V\right)}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}\end{array}].& \left(\mathrm{Equation}14\right)\end{array}$

Considering that the variable w_V^αV=(w_V^V)^α=1^α=1 and V=M/r, Equation 14 could be expressed as follows:

$\begin{array}{cc}{X}_{\left(k_1,\left(v+V\right)\right)}=\hspace{1em}[\begin{array}{c}{w}_M^0{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}\right)}w_{M/r}^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}+\dots \\ +W_M^{\left(r-1\right)\frac{M}{r}}w_M^{\left(r-1\right)v}w_N^{\left(r-1\right)k_1}{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}+\left(r-1\right)\right)}w_{M/r}^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}\end{array}]⋮X_{\left(k_1,\left(v+\left(r-1\right)V\right)\right)}=\hspace{1em}[\begin{array}{c}{w}_M^0{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}\right)}w_{M/r}^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}+\\ \dots +w_M^{{\left(r-1\right)}^2\frac{M}{r}}w_M^{\left(r-1\right)v}w_N^{\left(r-1\right)k_1}{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}+\left(r-1\right)\right)}w_{M/r}^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}\end{array}],& \left(\mathrm{Equation}15\right)\\ X_{\left(k_1,v\right)}=\left(\begin{array}{c}{X}_{\left(v\right)}\\ X_{\left(v+V\right)}\\ ⋮\\ X_{\left(v+\left(r-1\right)V\right)}\end{array}\right)=\left(\begin{array}{cccc}{w}_N^0& w_N^0& \dots & w_N^0\\ w_N^0& w_N^{N/r}& \dots & w_N^{\left(r-1\right)\left(N/r\right)}\\ ⋮& ⋮& \ddots & ⋮\\ w_N^0& w_N^{\left(r-1\right)\left(N/r\right)}& \dots & w_N^{{\left(r-1\right)}^2\left(N/r\right)}\end{array}\right)\times \left(\begin{array}{cccc}{w}_N^0& 0& \dots & 0\\ 0& w_N^{D_{\mathrm{ip}}v}w_N^{k_1}& ⋮& ⋮\\ ⋮& ⋮& \ddots & ⋮\\ 0& \dots & 0& w_N^{D_{\mathrm{ip}}\left(r-1\right)v}w_N^{\left(r-1\right)k_1}\end{array}\right)\times \hspace{1em}[\begin{array}{c}{\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}\right)}w_{\frac{M}{r}}^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}\\ {\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}+1\right)}w_{\frac{M}{r}}^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}\\ ⋮\\ {\sum }_{n=0}^{\frac{M}{r}-1}x_{\left(\mathrm{rn}+\left(r-1\right)\right)}w_{\frac{M}{r}}^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nk}}_1}\end{array}].& \left(\mathrm{Equation}16\right)\end{array}$

The first matrix, the well-known adder tree matrix T_r, and the second matrix can be known collectively as an Input Pruning FFT twiddle factor matrix W_N, respectively. Equation 16 can be expressed in a compact form as follows:

$\begin{array}{cc}{x}_{\left(k_1+D_{\mathrm{ip}}\left(v+\mathrm{lV}\right)\right)}=X_{\left(k_1,k_2\right)}=T_MW_N\mathrm{col}\left({\sum }_{n=0}^{V-1}x_{\left(\mathrm{rn}+l\right)}w_V^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nlk}}_1}|l=0,1,\dots ,r-1\right),& \left(\mathrm{Equation}17\right)\end{array}$

fork₁=0, 1, . . . , D_ip−1 and v=0, 1, . . . , V−1, where the variable X_(k1,k2) can be expressed as follows:

$\begin{array}{cc}{X}_{\left(k_1,k_2\right)}={\left[{\sum }_{n=0}^{V-1}x_{\left(\mathrm{rn}+l\right)}w_V^{\mathrm{nv}}w_{\frac{N}{r}}^{{\mathrm{nlk}}_1}|l=0,1,\dots ,r-1\right]}^T.& \left(\mathrm{Equation}18\right)\end{array}$

Further, the variable (W_N) can be expressed as follows:

W _N=diag(w_N^Diplvw_N^lk1|l=0,1, . . . ,r−1),  (Equation 19)

and the matrix T_M can be expressed as follows:

$\begin{array}{cc}{T}_M=\left(\begin{array}{cccccc}{w}_M^0& w_M^0& w_M^0& \dots & \dots & w_M^0\\ w_M^0& w_M^{M/r}& w_M^{2M/r}& \dots & \dots & w_M^{\left(r-1\right)M/r}\\ w_M^0& w_M^{2M/r}& w_M^{4M/r}& \dots & \dots & w_M^{2\left(r-1\right)M/r}\\ ⋮& ⋮& ⋮& \ddots & ⋮& ⋮\\ ⋮& ⋮& ⋮& \ddots & \ddots & ⋮\\ w_M^0& w_M^{\left(r-1\right)M/r}& w_M^{2\left(r-1\right)M/r}& \dots & \dots & w_M^{{\left(r-1\right)}^2M/r}\end{array}\right)& \left(\mathrm{Equation}20\right)\end{array}$

In terms of the digital signal processor, the factorization of the FFT can be interpreted as dataflow, which depicts the arithmetic operations and their dependencies. When Equation 16 is read from left to right, the decimation in frequency (DIF) algorithm can be obtained. When Equation 16 is read from right to left, the decimation in time (Equation DIT) algorithm can be determined. It should be noted that the DIF algorithm may require one shuffling stage in order to obtain ordered output data.

The write address generator (WAG) can be determined as follows:

WAG=lV+v.  (Equation 21)

The read address generator zRAG) can be determined as follows:

$\begin{array}{cc}\mathrm{RAD}=n_1\left(\frac{m}{r^{\left(s+1\right)}}\right)+{〚v〛}_{r^{\left(S_M-s\right)}}+\lfloor \frac{v}{r^{\left(S_M-s\right)}}\rfloor r^{\left(S_M+1-s\right)}.& \left(\mathrm{Equation}22\right)\end{array}$

Further, the DIT Coefficient address generator (CAG) can be determined as follows:

$\begin{array}{cc}\mathrm{CAG}={〚n_1\left(D_{\mathrm{ip}}\left(\mathrm{lV}+\lfloor \frac{v}{r^{\left(S_M-s\right)}}\rfloor r^{\left(S_M-s\right)}\right)+\left(r^{\left(S_M-s\right)}k_1\right)\right)〛}_N,& \left(\mathrm{Equation}23\right)\end{array}$

where the variable [[x]]_N can represent the operation x modulo N; the variable └x┘ may represent the integer part operator of x; the indices are v=0, 1, . . . , V−1; the variable s=0, 1, . . . , S_M; the variable r is the radix-r, the variable V is the number of words

$\left(V=\frac{M}{r}\right),$

and the variable S_M is the number of stages (S_M=log_r M−1). Accordingly, the low-complexity I/O pruning FFT can be determined as follows:

X _{(k 1 +D ip ×k 2 )} =X _{(k 1 +D ip ×k 2 ,s+1,v,w ag )}=Σ_n=0^r-1[X_{(k1+Dip×k2,s,v,Rad)}w_M^CAG]   (Equation 24)

FIG. 2 depicts a graph 200 of real operations reduction versus input pruning for the generalized radix-r input/output pruning FFT of FIG. 1 compared to a conventional DIT radix-2 Cooley-Tukey algorithm. The graph 200 reveals that the complexity ratio is approximately the same.

The computational complexity of the algorithm of Equation 24 may be similar to the complexity of the DIT Cooley-Tukey algorithm. Therefore; the complexity of Equation 17 in terms of arithmetic operations for Equation 24 can be expressed as follows:

t _{c-input-IPJMFFT} =D _ip M(4MS_M)=N(4MS_M)=N(4M log₂M).  (Equation 25)

For real value arithmetic operations, the complexity ratio between the low-complexity I/O pruning FFT and a conventional input pruning FFT as taught by Medina-Melendrez, et al. (M. Medina-Melendrez, M. Arias-Estrada and A. Castro, “Input and/or Output Pruning of Composite Length FFTs Using a DIF-DIT Transform Decomposition”, IEEE Transactions on Signal Processing, Vol. 57, No. 10, pp. 4124-4128, October 2009) (hereinafter “Medina”) can be determined as follows:

$\begin{array}{cc}{G}_{\mathrm{IPJMFFT}/\mathrm{input}\text{-}\mathrm{Puning}\_\mathrm{Medina}}=\frac{\left(4{\mathrm{MS}}_M\right)}{\left(4{\mathrm{MS}}_M+8\right)}=\frac{\left(4M{\log }_2M\right)}{\left(4M{\log }_2M+8\right)},& \left(\mathrm{Equation}26\right)\end{array}$

This ratio is sketched in FIG. 3 for N=8192, and the input pruning, M, changes from 2 to N.

FIG. 3 depicts a graph 300 of a complexity ratio of the generalized radix-r input/output pruning FFT according to some embodiments of the present disclosure versus the Medina FFT. In the graph 300, a complexity reduction for M<26 can be observed. In some embodiments, the complexity of the generalized radix-r I/O pruning FFT algorithm t_c can be computed as follows:

t _{c-Iimput/Output-JMIOPFFT} =t _cm(L_oD_op)+D_ipD_opFFT_P+t_ca/s(D_ipD_op+2L_oD_op),   (Equation 27)

Therefore, the complexity of the generalized radix-r I/O pruning FFT algorithm can be determined as follows:

$\begin{array}{cc}{t}_{c\text{-}\mathrm{Iimput}/\mathrm{Output}-\mathrm{JMIOPFFT}}=6N+\frac{N}{P}\left(4{\mathrm{PS}}_P+P+6\right)+2\left(\frac{N}{P}+2N\right)=10N+\frac{N}{P}\left(4{\mathrm{PS}}_P+P+8\right)=N\left(4{\mathrm{PS}}_P+11P+8\right).& \left(\mathrm{Equation}28\right)\end{array}$

The complexity comparison between the generalized radix-r I/O pruning FFT and the Medina FFT reveals that both methods have the same complexity for L_i=8192. Further, the graph 200 reveals that, for L_i=307, the complexity of the generalized radix-r I/O pruning FFT algorithm is approximately equivalent to the Medina FFT algorithm for L_i=33 for a number of outputs greater than 2⁸. The operation's reduction ratio between the generalized radix-r I/O pruning FFT algorithm and the Medina FFT is presented in FIG. 4.

FIG. 4 depicts a graph 400 of a number of operations versus a number of output elements for the generalized radix-r input/output pruning FFT according to some embodiments of the present disclosure versus a pruning FFT implementation. The graph 400 depicts the complexity comparison of the graph 300 of FIG. 3, but on a logarithmic scale.

FIG. 5 depicts a graph 500 of a number of operations versus a number of output elements for the generalized radix-r input/output pruning FFT according to some embodiments of the present disclosure versus a pruning FFT implementation showing a gain.

FIG. 6 depicts a graph 600 of a reduction ratio of operations versus a number of output elements, for the generalized radix-r input/output pruning FFT according to some embodiments of the present disclosure versus a pruning FFT implementation. The graph 600 is an expanded version of the graph 500 of FIG. 5.

It should be appreciated from the graphs 500 and 600 of FIGS. 4 and 6 that the generalized radix-r input/output pruning FFT demonstrates a gain that ranges between 1.4 and 1.2 for L_i=307 and L_o>2⁸ as compared to the Medina FFT.

According to Equation 33, it seems that the output stage would be costly in implementation for L_o>D_ip. The direct method and the 2 BF filtering method proposed by Sorensen, et al. (H. V. Sorensen and C. S. Burrus, “Efficient computation of the DFT with only a subset of input or output points,” IEEE Transactions on Signal Processing, vol. 41, no. 3, pp. 1184-1199, March 1993.) can be combined for 1<Dop≤4 in order to achieve a gain estimated at 30% for large N, which can be weighed against the loss in precision as shown in FIGS. 7 and 8.

FIG. 7 depicts a graph 700 of signal-to-quantization-noise ratio (SQNR) in decibels versus number of output elements without filtering for the generalized radix-r input/output pruning FFT, in accordance with some embodiments of the present disclosure. The graph 700 shows that the generalized radix-r I/O pruning FFT of the present disclosure provides an SQNR that represents an improvement in some instances over the Medina FFT.

FIG. 8 depicts a graph 800 of signal-to-quantization-noise ratio (SQNR) in decibels versus number of output elements with filtering for the generalized radix-r input/output pruning FFT, in accordance with some embodiments of the present disclosure. With 2 BF filtering employed, the graph 800 shows that the generalized radix-r I/O pruning FFT of the present disclosure provides an SQNR that represents an improvement in some instances over the Medina FFT.

FIG. 9 depicts a graph 900 of a number of operations versus number of input/output elements for the generalized radix-r input/output pruning FFT according to some embodiments of the present disclosure versus a radix-2 Cooley-Tukey FFT implementation. In terms of complexity, the graph 900 shows that the generalized radix-r I/O pruning FFT represents an improvement over the Medina FFT.

FIG. 10 depicts a graph 1000 of the reduction ratio of operations versus the number of output elements for the generalized radix-r input/output pruning FFT, in accordance with some embodiments of the present disclosure. The graph 1000 shows an operation's reduction ratio of the percentage versus the number of output elements for the FFT using a 2BF method where L_i=L₀ and N=1024.

FIGS. 11 and 12 depict the software implementation of sequences that have L_i (multiple of the FFT radix-r) consecutive non-zero input points at any position n (n is multiple of the FFT radix-r) within the sequence and not necessarily at the beginning. In FIG. 11, a code portion 1100 is disclosed that configures the pruning algorithm. FIG. 12 depicts a code portion 1200 that discloses the recursive computation.

It should be appreciated that the code example provided in FIGS. 11 and 12 depicts one possible implementation of the algorithm. Other implementations are also possible.

In conjunction with the systems, circuits, devices, and methods described above with respect to FIGS. 1-12, an efficient input pruning FFT is disclosed that can reduce the complexity and the computational effort used to produce the FFT outputs, as compared to conventional approaches. Further, the input pruning FFT may be used in image processing (reducing the number of operations) and in wireless communications (reducing complexity and computational effort), providing a key contribution to advances in wireless communications. In an example, reduction in computational time that can be achieved by the generalized radix-r input/output pruning FFT finds applications in the wireless communications industry, such as orthogonal frequency-division multiple access (OFDMA) applications, long-term evolution (LTE) technologies, other communications technologies, or any combination thereof.

In some implementations, an efficient radix-r input pruning FFT is disclosed that can reduce the complexity and the computational effort to produce the FFT outputs as compared to conventional approaches. Further, this approach is applied on sequences that will have L_i (multiple of the FFT radix-r) consecutive non-zero input points at any position n (n is multiple of the fft radix-r) within the sequence and not necessarily at the beginning. It is an indispensable tool for the orthogonal frequency division multiplexing (OFDM) based Cognitive Radio that will be mainly based on FFT pruning, which applies efficiently zeros to the inputs with arbitrary distributions within the sequence.

Implementations that may be used within the scope of the present disclosure may be illustrated by way of the following clauses:

Clause 1: A circuit comprises an input configured to receive a signal including a plurality of input values and a radix-r input/output pruning fast Fourier transform (FFT) processing element coupled to the input. The radix-r input/output pruning FFT processing element prunes FFT operations related to a subset of the plurality of input values having a value of zero and determines, based on others of the plurality of input values, discrete Fourier Transform (DFT) output having fewer output values than a number of the plurality of input values.

Clause 2: The circuit of clause 1, wherein the circuit determines, from the signal, a sequence of the input values that includes a number of consecutive non-zero input points to determine the DFT output having a selected number of output values.

Clause 3: The circuit of any of the preceding clauses, wherein the selected number of output values is less than a total number of input values of the signal.

Clause 4: The circuit of any of the preceding clauses, wherein the radix-r input/output pruning FFT processing element is configured to provide a number (r) complex multipliers in parallel to implement each of a plurality of butterfly computations of the FFT operations.

Clause 5: The circuit of any of the preceding clauses, wherein the plurality of input values includes a number (M) of consecutive non-zero input values.

Clause 6: The circuit of any of the preceding clauses, wherein the radix-r input/output pruning FFT processing element to determine the subset of the plurality of input values from the number (M) of the consecutive non-zero input values.

Clause 7: The circuit of any of the preceding clauses, where the radix-r input/output pruning FFT processing element incorporates twiddle factors and adder tree matrices of the FFT operations into a single stage.

Clause 8: A method comprises receiving a plurality of input values and determining a subset of a plurality of input values having non-zero values. The method further includes determining a discrete Fourier Transformer (DFT) output based on the subset of the plurality of input values using a radix-r input/output pruning fast Fourier transform (FFT) and providing the DFT output including a plurality of output values to an output interface.

Clause 9. The method of clause 8, wherein a number of the plurality of output values is less than a number of the plurality of input values.

Clause 10. The method of claim 7, further comprising determining a sequence of the plurality of input values that includes a number of consecutive non-zero input points.

Clause 11. The method of claim 9, wherein the DFT output is determined from the sequence of the plurality of input values.

Clause 12: The method of claim 7, further comprising providing a number (r) of complex multipliers in parallel to determine a plurality of butterfly computations of the FFT operations.

Clause 13: The method of claim 7, wherein the plurality of input values includes a number (M) of consecutive non-zero input values.

Clause 14: The method of claim 12, further comprising determining the subset of the plurality of input values based on the number (M) of the consecutive non-zero input values.

Clause 15: The method of claim 7, further comprising incorporating twiddle factors and adder tree matrices of the FFT into a single stage.

Clause 16: A circuit comprises an input interface to receive a signal including a plurality of input values, an output interface to provide a discrete Fourier Transform (DFT) output including a plurality of output values, and a processing element to perform radix-r input/output pruning fast Fourier transform (FFT) operations on the plurality of input values to produce the DFT output. The processing element prunes FFT operations related to a subset of the plurality of input values having a value of zero and determines, based on others of the plurality of input values, the plurality of output values comprising the DFT output having fewer values than a number of the plurality of input values.

Clause 17: The circuit of clause 16, wherein the processing element determines the DFT output based on a number of consecutive non-zero input values.

Clause 18: The circuit of any of the clauses 16 through 17, wherein number of the plurality of output values are less than the plurality of input values.

Clause 19: The circuit of any of the clauses 16 through 18 wherein the processing element provides a number (r) of complex multipliers in parallel to implement each of a plurality of butterfly computations of the FFT operations.

Clause 20: The circuit of any of the clauses 16 through 19 wherein the plurality of input values includes a number (M) of consecutive non-zero input values and the processing element determines the subset of the plurality of input values from the number (M) of the consecutive non-zero input values.

Clause 21: The circuit of any of the clauses 16 through 20, where the processing element incorporates twiddle factors and adder tree matrices of the FFT operations into a single stage.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the scope of the invention.

Claims

1. A circuit comprising: an input configured to receive a signal including a plurality of input values; anda radix-r input/output pruning fast Fourier transform (FFT) processing element coupled to the input, the radix-r input/output pruning FFT processing element to: prune FFT operations related to a subset of the plurality of input values having a value of zero; anddetermine, based on others of the plurality of input values, discrete Fourier Transform (DFT) output having fewer output values than a number of the plurality of input values.

2. The circuit of claim 1, wherein the circuit determines, from the signal, a sequence of the input values that includes a number of consecutive non-zero input points to determine the DFT output having a selected number of output values.

3. The circuit of claim 2, wherein the selected number of output values is less than a total number of input values of the signal.

4. The circuit of claim 1, wherein the radix-r input/output pruning FFT processing element is configured to provide a number (r) complex multipliers in parallel to implement each of a plurality of butterfly computations of the FFT operations.

5. The circuit of claim 1, wherein the plurality of input values includes a number (M) of consecutive non-zero input values.

6. The circuit of claim 5, the radix-r input/output pruning FFT processing element to determine the subset of the plurality of input values from the number (M) of the consecutive non-zero input values.

7. The circuit of claim 1, where the radix-r input/output pruning FFT processing element incorporates twiddle factors and adder tree matrices of the FFT operations into a single stage.

8. A method comprising: receiving a plurality of input values;determining a subset of a plurality of input values having non-zero values;determining a discrete Fourier Transformer (DFT) output based on the subset of the plurality of input values using a radix-r input/output pruning fast Fourier transform (FFT); andproviding the DFT output including a plurality of output values to an output interface.

9. The method of claim 8, wherein a number of the plurality of output values is less than a number of the plurality of input values.

10. The method of claim 8, further comprising determining a sequence of the plurality of input values that includes a number of consecutive non-zero input points.

11. The method of claim 9, wherein the DFT output is determined from the sequence of the plurality of input values.

12. The method of claim 8, further comprising providing a number (r) of complex multipliers in parallel to determine a plurality of butterfly computations of the FFT operations.

13. The method of claim 8, wherein the plurality of input values includes a number (M) of consecutive non-zero input values.

14. The method of claim 13, further comprising determining the subset of the plurality of input values based on the number (M) of the consecutive non-zero input values.

15. The method of claim 8, further comprising incorporating twiddle factors and adder tree matrices of the FFT into a single stage.

16. A circuit comprising: an input interface to receive a signal including a plurality of input values;an output interface to provide a discrete Fourier Transform (DFT) output including a plurality of output values; anda processing element to perform radix-r input/output pruning fast Fourier transform (FFT) operations on the plurality of input values to produce the DFT output, the processing element to: prune FFT operations related to a subset of the plurality of input values having a value of zero; anddetermine, based on others of the plurality of input values, the plurality of output values comprising the DFT output having fewer values than a number of the plurality of input values.

17. The circuit of claim 16, wherein number of the plurality of output values are less than the plurality of input values.

18. The circuit of claim 16, wherein the processing element provides a number (r) of complex multipliers in parallel to implement each of a plurality of butterfly computations of the FFT operations.

19. The circuit of claim 16, wherein: the plurality of input values includes a number (M) of consecutive non-zero input values; andthe processing element determines the subset of the plurality of input values from the number (M) of the consecutive non-zero input values.

20. The circuit of claim 16, where the processing element incorporates twiddle factors and adder tree matrices of the FFT operations into a single stage.