Claims
- 1. A processor, comprising:a monitor for measuring the relative amount of Input/Output (I/O) within said processor, results of said measuring being used by said processor for controlling a clock speed of said processor.
- 2. The processor of claim 1, wherein said controlling a clock speed of said processor is responsive to usage of said processor being below a preselected level.
- 3. The processor of claim 1, wherein said clock speed of said processor is controlled to reduce processor idle time.
- 4. The processor of claim 1, wherein said clock speed of said processor is controlled to minimize the relative amount of processor idle time.
- 5. The processor of claim 1, wherein said clock speed of said processor is modified in response to a utilization percentage of said processor being below a preselected level.
- 6. The processor of claim 1, wherein said clock speed of said processor is modified to control a utilization percentage of said processor.
- 7. The processor of claim 1, wherein said results of said measuring are used by said processor for providing a signal for circuitry for controlling periods of time a processor clock is in an OFF state.
- 8. The processor of claim 7, wherein energy consumption in said processor is at a maximum when the length of each period of time said clock is in an OFF state is at zero.
- 9. The processor of claim 7, wherein energy consumption in said processor decreases as the length of each period of time said clock is in an OFF state increases.
- 10. The processor of claim 7, wherein said periods of time said clock is in an OFF state are constantly being adjusted to optimize said utilization percentage of said processor.
- 11. The processor of claim 7, wherein said OFF state represents the minimum clock rate at which said processor can operate.
- 12. The processor of claim 11, wherein said minimum clock rate may be zero for processors that can have their clocks stopped.
- 13. The processor of claim 1, wherein said monitor inhibits modification of said clock speed while said processor is processing critical I/O.
- 14. The processor of claim 1, wherein said processor releases control of said clock speed in response to said monitor detecting a critical I/O request.
- 15. The processor of claim 1, wherein said monitor is self-tuning.
- 16. The processor of claim 15, wherein said monitor uses a control system of continuous feedback loops.
- 17. The processor of claim 1, wherein said processor is a central processing unit (CPU).
- 18. The processor of claim 1, wherein said monitor is a program installed on said processor.
- 19. A processor, comprising:a monitor for measuring the relative importance of Input/Output (I/O) within said processor, results of said measuring being used by said processor for controlling a clock speed of said processor.
- 20. The processor of claim 19, wherein said controlling a clock speed of said processor is responsive to usage of said processor being below a preselected level.
- 21. The processor of claim 19, wherein said clock speed of said processor is controlled to reduce processor idle time.
- 22. The processor of claim 19, wherein said clock speed of said processor is controlled to minimize the relative amount of processor idle time.
- 23. The processor of claim 19, wherein said clock speed of said processor is modified in response to a utilization percentage of said processor being below a preselected level.
- 24. The processor of claim 19, wherein said clock speed of said processor is modified to control a utilization percentage of said processor.
- 25. The processor of claim 19, wherein said results of said measuring are used by said processor for providing a signal for circuitry for controlling periods of time a processor clock is in an OFF state.
- 26. The processor of claim 25, wherein energy consumption in said processor is at a maximum when the length of each period of time said clock is in an OFF state is at zero.
- 27. The processor of claim 25, wherein energy consumption in said processor decreases as the length of each period of time said clock is in an OFF state increases.
- 28. The processor of claim 25, wherein said periods of time said clock is in an OFF state are constantly being adjusted to optimize said utilization percentage of said processor.
- 29. The processor of claim 25, wherein said OFF state represents the minimum clock rate at which said processor can operate.
- 30. The processor of claim 29, wherein said minimum clock rate may be zero for processors that can have their clocks stopped.
- 31. The processor of claim 19, wherein said monitor inhibits modification of said clock speed while said processor is processing critical I/O.
- 32. The processor of claim 19, wherein said processor releases control of said clock speed in response to said monitor detecting a critical I/O request.
- 33. The processor of claim 19, wherein said monitor is self-tuning.
- 34. The processor of claim 33, wherein said monitor uses a control system of continuous feedback loops.
- 35. The processor of claim 19, wherein said processor is a central processing unit (CPU).
- 36. The processor of claim 19, wherein said monitor is a program installed on said processor.
- 37. A processor, comprising:a monitor for measuring the relative amount of time between Input/Output (I/O) within said processor, results of said measuring being used by said processor for controlling a clock speed of said processor.
- 38. The processor of claim 37, wherein said controlling a clock speed of said processor is responsive to usage of said processor being below a preselected level.
- 39. The processor of claim 37, wherein said clock speed of said processor is controlled to reduce processor idle time.
- 40. The processor of claim 37, wherein said clock speed of said processor is controlled to minimize the relative amount of processor idle time.
- 41. The processor of claim 37, wherein said clock speed of said processor is modified in response to a utilization percentage of said processor being below a preselected level.
- 42. The processor of claim 37, wherein said clock speed of said processor is modified to control a utilization percentage of said processor.
- 43. The processor of claim 37, wherein said results of said measuring are used by said processor for providing a signal for circuitry for controlling periods of time a processor clock is in an OFF state.
- 44. The processor of claim 43, wherein energy consumption in said processor is at a maximum when the length of each period of time said clock is in an OFF state is at zero.
- 45. The processor of claim 43, wherein energy consumption in said processor decreases as the length of each period of time said clock is in an OFF state increases.
- 46. The processor of claim 43, wherein said periods of time said clock is in an OFF state are constantly being adjusted to optimize said utilization percentage of said processor.
- 47. The processor of claim 43, wherein said OFF state represents the minimum clock rate at which said processor can operate.
- 48. The processor of claim 47, wherein said minimum clock rate may be zero for processors that can have their clocks stopped.
- 49. The processor of 37, claim wherein said monitor inhibits modification of said clock speed while said processor is processing critical I/O.
- 50. The processor of claim 37, wherein said processor releases control of said clock speed in response to said monitor detecting a critical I/O request.
- 51. The processor of claim 37, wherein said monitor is self-tuning.
- 52. The processor of claim 51, wherein said monitor uses a control system of continuous feedback loops.
- 53. The processor of claim 37, wherein said processor is a central processing unit (CPU).
- 54. The processor of claim 37, wherein said monitor is a program installed on said processor.
Parent Case Info
This application is a Continuation of application Ser. No. 09/756,838, filed Jan. 9, 2001, now U.S. Pat. No. 6,397,340 which is a Continuation of application Ser. No. 09/392,205, filed Sep. 8, 1999, now U.S. Pat. No. 6,173,409 which is a Continuation of application Ser. No. 08/023,831, filed Feb. 23, 1993, now U.S. Pat. No. 6,006,336 which is a Continuation of application Ser. No. 07/429,270 filed Oct. 30, 1989, now U.S. Pat. No. 5,218,704.
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Jan 1990 |
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Continuations (4)
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Number |
Date |
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Parent |
09/756838 |
Jan 2001 |
US |
Child |
10/074739 |
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US |
Parent |
09/392205 |
Sep 1999 |
US |
Child |
09/756838 |
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US |
Parent |
08/023831 |
Feb 1993 |
US |
Child |
09/392205 |
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US |
Parent |
07/429270 |
Oct 1989 |
US |
Child |
08/023831 |
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US |