Patent Application
20190004878
The disclosure relates generally to electronics, and, more specifically, an embodiment of the disclosure relates to a configurable spatial accelerator.
A processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction herein may refer to a macro-instruction, e.g., an instruction that is provided to the processor for execution, or to a micro-instruction, e.g., an instruction that results from a processor's decoder decoding macro-instructions.
The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
In the following description, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
A processor (e.g., having one or more cores) may execute instructions (e.g., a thread of instructions) to operate on data, for example, to perform arithmetic, logic, or other functions. For example, software may request an operation and a hardware processor (e.g., a core or cores thereof) may perform the operation in response to the request. One non-limiting example of an operation is a blend operation to input a plurality of vectors elements and output a vector with a blended plurality of elements. In certain embodiments, multiple operations are accomplished with the execution of a single instruction.
Exascale performance, e.g., as defined by the Department of Energy, may require system-level floating point performance to exceed 10̂18 floating point operations per second (exaFLOPs) or more within a given (e.g., 20 MW) power budget. Certain embodiments herein are directed to a configurable spatial accelerator (CSA) that targets high performance computing (HPC). Certain embodiments of a CSA target the direct execution of a dataflow graph to yield a computationally dense yet energy-efficient spatial microarchitecture which far exceeds conventional roadmap architectures. Below includes a description of the architectural philosophy of embodiments of a CSA and certain features thereof. As with any revolutionary architecture, programmability may be a risk. To mitigate this issue, embodiments of the CSA architecture have been co-designed with a compilation tool chain, which is also discussed below.
Exascale computing goals may require enormous system-level floating point performance (e.g., 1 ExaFLOPs) within an aggressive power budget (e.g., 20 MW). However, simultaneously improving the performance and energy efficiency of program execution with classical von Neumann architectures has become difficult: out-of-order scheduling, simultaneous multi-threading, complex register files, and other structures provide performance, but at high energy cost. Certain embodiments herein achieve performance and energy requirements simultaneously. Exascale computing power-performance targets may demand both high throughput and low energy consumption per operation. Certain embodiments herein provide this by providing for large numbers of low-complexity, energy-efficient processing (e.g., computational) elements which largely eliminate the control overheads of previous processor designs. Guided by this observation, certain embodiments herein include a configurable spatial accelerator (CSA), e.g., comprising an array of processing elements (PEs) connected by a set of light-weight, back-pressured networks. One example of a CSA tile is depicted in
Performance increases may result from parallel execution within a (e.g., dense) CSA where each PE may execute simultaneously, e.g., if input data is available. Efficiency increases may result from the efficiency of each PE, e.g., where each PE's operation (e.g., behavior) is fixed once per configuration (e.g., mapping) step and execution occurs on local data arrival at the PE, e.g., without considering other fabric activity. In certain embodiments, a PE is (e.g., each a single) dataflow operator, for example, a dataflow operator that only processes input data when both (i) the input data has arrived at the dataflow operator and (ii) there is space available for storing the output data, e.g., otherwise no processing is occurring. These properties enable embodiments of the CSA to provide paradigm-shifting levels of performance and tremendous improvements in energy efficiency across a broad class of existing single-stream and parallel programs, e.g., all while preserving familiar HPC programming models. Certain embodiments of a CSA may target HPC such that floating point energy efficiency is extremely important. Certain embodiments of the CSA not only deliver compelling improvements in performance and reductions in energy, they also deliver these gains to existing HPC programs written in mainstream HPC languages and for mainstream HPC frameworks. Certain embodiments of the CSA architecture (e.g., with compilation in mind) provide several extensions in direct support of the control-dataflow internal representations generated by modern compilers. Certain embodiments herein are direct to a CSA dataflow compiler, e.g., which can accept C, C++, and Fortran programming languages, to target a CSA architecture.
Section 2 below discloses embodiments of CSA architecture. In particular, novel embodiments of integrating memory within the dataflow execution model are disclosed. Section 3 delves into the microarchitectural details of embodiments of a CSA. In one embodiment, the main goal of a CSA is to support compiler produced programs. Section 4 below examines embodiments of a CSA compilation tool chain. The advantages of embodiments of a CSA are compared to other architectures in the execution of compiled codes in Section 5. Finally the performance of embodiments of a CSA microarchitecture is discussed in Section 6, further CSA details are discussed in Section 7, and a summary is provided in Section 8.
The goal of certain embodiments of a CSA is to rapidly and efficiently execute programs, e.g., programs produced by compilers. Certain embodiments of the CSA architecture provide programming abstractions that support the needs of compiler technologies and programming paradigms. Embodiments of the CSA execute dataflow graphs, e.g., a program manifestation that closely resembles the compiler's own internal representation (IR) of compiled programs. In this model, a program is represented as a dataflow graph comprised of nodes (e.g., vertices) drawn from a set of architecturally-defined dataflow operators (e.g., that encompass both computation and control operations) and edges which represent the transfer of data between dataflow operators. Execution may proceed by injecting dataflow tokens (e.g., that are or represent data values) into the dataflow graph. Tokens may flow between and be transformed at each node (e.g., vertex), for example, forming a complete computation. A sample dataflow graph and its derivation from high-level source code is shown in
Embodiments of the CSA are configured for dataflow graph execution by providing exactly those dataflow-graph-execution supports required by compilers. In one embodiment, the CSA is an accelerator (e.g., an accelerator in
The key architectural interface of embodiments of the accelerator (e.g., CSA) is the dataflow operator, e.g., as a direct representation of a node in a dataflow graph. From an operational perspective, dataflow operators behave in a streaming or data-driven fashion. Dataflow operators may execute as soon as their incoming operands become available. CSA dataflow execution may depend (e.g., only) on highly localized status, for example, resulting in a highly scalable architecture with a distributed, asynchronous execution model. Dataflow operators may include arithmetic dataflow operators, for example, one or more of floating point addition and multiplication, integer addition, subtraction, and multiplication, various forms of comparison, logical operators, and shift. However, embodiments of the CSA may also include a rich set of control operators which assist in the management of dataflow tokens in the program graph. Examples of these include a “pick” operator, e.g., which multiplexes two or more logical input channels into a single output channel, and a “switch” operator, e.g., which operates as a channel demultiplexor (e.g., outputting a single channel from two or more logical input channels). These operators may enable a compiler to implement control paradigms such as conditional expressions. Certain embodiments of a CSA may include a limited dataflow operator set (e.g., to relatively small number of operations) to yield dense and energy efficient PE microarchitectures. Certain embodiments may include dataflow operators for complex operations that are common in HPC code. The CSA dataflow operator architecture is highly amenable to deployment-specific extensions. For example, more complex mathematical dataflow operators, e.g., trigonometry functions, may be included in certain embodiments to accelerate certain mathematics-intensive HPC workloads. Similarly, a neural-network tuned extension may include dataflow operators for vectorized, low precision arithmetic.
Communications arcs are the second major component of the dataflow graph. Certain embodiments of a CSA describes these arcs as latency insensitive channels, for example, in-order, back-pressured (e.g., not producing or sending output until there is a place to store the output), point-to-point communications channels. As with dataflow operators, latency insensitive channels are fundamentally asynchronous, giving the freedom to compose many types of networks to implement the channels of a particular graph. Latency insensitive channels may have arbitrarily long latencies and still faithfully implement the CSA architecture. However, in certain embodiments there is strong incentive in terms of performance and energy to make latencies as small as possible. Section 3.2 herein discloses a network microarchitecture in which dataflow graph channels are implemented in a pipelined fashion with no more than one cycle of latency. Embodiments of latency-insensitive channels provide a critical abstraction layer which may be leveraged with the CSA architecture to provide a number of runtime services to the applications programmer. For example, a CSA may leverage latency-insensitive channels in the implementation of the CSA configuration (the loading of a program onto the CSA array).
Dataflow architectures generally focus on communication and data manipulation with less attention paid to state. However, enabling real software, especially programs written in legacy sequential languages, requires significant attention to interfacing with memory. Certain embodiments of a CSA use architectural memory operations as their primary interface to (e.g., large) stateful storage. From the perspective of the dataflow graph, memory operations are similar to other dataflow operations, except that they have the side effect of updating a shared store. In particular, memory operations of certain embodiments herein have the same semantics as every other dataflow operator, for example, they “execute” when their operands, e.g., an address, are available and, after some latency, a response is produced. Certain embodiments herein explicitly decouple the operand input and result output such that memory operators are naturally pipelined and have the potential to produce many simultaneous outstanding requests, e.g., making them exceptionally well suited to the latency and bandwidth characteristics of a memory subsystem. Embodiments of a CSA provide basic memory operations such as load, which takes an address channel and populates a response channel with the values corresponding to the addresses, and a store. Embodiments of a CSA may also provide more advanced operations such as in-memory atomics and consistency operators. These operations may have similar semantics to their von Neumann counterparts. Embodiments of a CSA may accelerate existing programs described using sequential languages such as C and Fortran. A consequence of supporting these language models is addressing program memory order, e.g., the serial ordering of memory operations typically prescribed by these languages.
A primary architectural considerations of embodiments of the CSA involve the actual execution of user-level programs, but it may also be desirable to provide several support mechanisms which underpin this execution. Chief among these are configuration (in which a dataflow graph is loaded into the CSA), extraction (in which the state of an executing graph is moved to memory), and exceptions (in which mathematical, soft, and other types of errors in the fabric are detected and handled, possibly by an external entity). Section 3.6 below discusses the properties of a latency-insensitive dataflow architecture of an embodiment of a CSA to yield efficient, largely pipelined implementations of these functions. Conceptually, configuration may load the state of a dataflow graph into the interconnect and processing elements (e.g., fabric), e.g., generally from memory. During this step, all structures in the CSA may be loaded with a new dataflow graph and any dataflow tokens live in that graph, for example, as a consequence of a context switch. The latency-insensitive semantics of a CSA may permit a distributed, asynchronous initialization of the fabric, e.g., as soon as PEs are configured, they may begin execution immediately. Unconfigured PEs may backpressure their channels until they are configured, e.g., preventing communications between configured and unconfigured elements. The CSA configuration may be partitioned into privileged and user-level state. Such a two-level partitioning may enable primary configuration of the fabric to occur without invoking the operating system (OS). Embodiments of the invention providing for direct user-level configuration may substantially reduce configuration overhead. During one embodiment of extraction, a logical view of the dataflow graph is captured and committed into memory, e.g., including all live control and dataflow tokens and state in the graph.
Extraction may also play a role in providing reliability guarantees through the creation of fabric checkpoints. Exceptions in a CSA may generally be caused by the same events that cause exceptions in processors, such as illegal operator arguments or reliability, availability, and serviceability (RAS) events. In certain embodiments, exceptions are detected at the level of dataflow operators, for example, checking argument values or through modular arithmetic schemes. Upon detecting an exception, a dataflow operator (e.g., circuit) may halt and emit an exception message, e.g., which contains both an operation identifier and some details of the nature of the problem that has occurred. In one embodiment, the dataflow operator will remain halted until it has been reconfigured. The exception message may then be communicated to an associated processor (e.g., core) for service, e.g., which may include extracting the graph for software analysis.
Embodiments of the CSA computer architectures (e.g., targeting HPC and datacenter uses) are tiled.
In one embodiment, the goal of the CSA microarchitecture is to provide a high quality implementation of each dataflow operator specified by the CSA architecture. Embodiments of the CSA microarchitecture provide that each processing element of the microarchitecture corresponds to approximately one node (e.g., entity) in the architectural dataflow graph. In certain embodiments, this results in microarchitectural elements that are not only compact, resulting in a dense computation array, but also energy efficient, for example, where processing elements (PEs) are both simple and largely unmultiplexed, e.g., executing a single dataflow operator for a configuration (e.g., programming) of the CSA. To further reduce energy and implementation area, a CSA may include a configurable, heterogeneous fabric style in which each PE thereof implements only a subset of dataflow operators. Peripheral and support subsystems, such as the CSA cache, may be provisioned to support the distributed parallelism incumbent in the main CSA processing fabric itself. Implementation of CSA microarchitectures may utilize dataflow and latency-insensitive communications abstractions present in the architecture. In certain embodiments, there is (e.g., substantially) a one-to-one correspondence between nodes in the compiler generated graph and the dataflow operators (e.g., dataflow operator compute elements) in a CSA.
Below is a discussion of an example CSA, followed by a more detailed discussion of the microarchitecture. Certain embodiments herein provide a CSA that allows for easy compilation, e.g., in contrast to an existing FPGA compilers that handle a small subset of a programming language (e.g., C or C++) and require many hours to compile even small programs.
Certain embodiments of a CSA architecture admits of heterogeneous coarse-grained operations, like double precision floating point. Programs may be expressed in fewer coarse grained operations, e.g., such that the disclosed compiler runs faster than traditional spatial compilers. Certain embodiments include a fabric with new processing elements to support sequential concepts like program ordered memory accesses. Certain embodiments implement hardware to support coarse-grained dataflow-style communication channels. This communication model is abstract, and very close to the control-dataflow representation used by the compiler. Certain embodiments herein include a network implementation that supports single-cycle latency communications, e.g., utilizing (e.g., small) PEs which support single control-dataflow operations. In certain embodiments, not only does this improve energy efficiency and performance, it simplifies compilation because the compiler makes a one-to-one mapping between high-level dataflow constructs and the fabric. Certain embodiments herein thus simplify the task of compiling existing (e.g., C, C++, or Fortran) programs to a CSA (e.g., fabric).
Energy efficiency may be a first order concern in modern computer systems. Certain embodiments herein provide a new schema of energy-efficient spatial architectures. In certain embodiments, these architectures form a fabric with a unique composition of a heterogeneous mix of small, energy-efficient, data-flow oriented processing elements (PEs) with a lightweight circuit-switched communications network (e.g., interconnect), e.g., with hardened support for flow control. Due to the energy advantages of each, the combination of these two components may form a spatial accelerator (e.g., as part of a computer) suitable for executing compiler-generated parallel programs in an extremely energy efficient manner. Since this fabric is heterogeneous, certain embodiments may be customized for different application domains by introducing new domain-specific PEs. For example, a fabric for high-performance computing might include some customization for double-precision, fused multiply-add, while a fabric targeting deep neural networks might include low-precision floating point operations.
An embodiment of a spatial architecture schema, e.g., as exemplified in
Programs may be converted to dataflow graphs that are mapped onto the architecture by configuring PEs and the network to express the control-dataflow graph of the program. Communication channels may be flow-controlled and fully back-pressured, e.g., such that PEs will stall if either source communication channels have no data or destination communication channels are full. In one embodiment, at runtime, data flow through the PEs and channels that have been configured to implement the operation (e.g., an accelerated algorithm). For example, data may be streamed in from memory, through the fabric, and then back out to memory.
Embodiments of such an architecture may achieve remarkable performance efficiency relative to traditional multicore processors: compute (e.g., in the form of PEs) may be simpler, more energy efficient, and more plentiful than in larger cores, and communications may be direct and mostly short-haul, e.g., as opposed to occurring over a wide, full-chip network as in typical multicore processors. Moreover, because embodiments of the architecture are extremely parallel, a number of powerful circuit and device level optimizations are possible without seriously impacting throughput, e.g., low leakage devices and low operating voltage. These lower-level optimizations may enable even greater performance advantages relative to traditional cores. The combination of efficiency at the architectural, circuit, and device levels yields of these embodiments are compelling. Embodiments of this architecture may enable larger active areas as transistor density continues to increase.
Embodiments herein offer a unique combination of dataflow support and circuit switching to enable the fabric to be smaller, more energy-efficient, and provide higher aggregate performance as compared to previous architectures. FPGAs are generally tuned towards fine-grained bit manipulation, whereas embodiments herein are tuned toward the double-precision floating point operations found in HPC applications. Certain embodiments herein may include a FPGA in addition to a CSA according to this disclosure.
Certain embodiments herein combine a light-weight network with energy efficient dataflow processing elements to form a high-throughput, low-latency, energy-efficient HPC fabric. This low-latency network may enable the building of processing elements with fewer functionalities, for example, only one or two instructions and perhaps one architecturally visible register, since it is efficient to gang multiple PEs together to form a complete program.
Relative to a processor core, CSA embodiments herein may provide for more computational density and energy efficiency. For example, when PEs are very small (e.g., compared to a core), the CSA may perform many more operations and have much more computational parallelism than a core, e.g., perhaps as many as 16 times the number of FMAs as a vector processing unit (VPU). To utilize all of these computational elements, the energy per operation is very low in certain embodiments.
The energy advantages our embodiments of this dataflow architecture are many. Parallelism is explicit in dataflow graphs and embodiments of the CSA architecture spend no or minimal energy to extract it, e.g., unlike out-of-order processors which must re-discover parallelism each time an instruction is executed. Since each PE is responsible for a single operation in one embodiment, the register files and ports counts may be small, e.g., often only one, and therefore use less energy than their counterparts in core. Certain CSAs include many PEs, each of which holds live program values, giving the aggregate effect of a huge register file in a traditional architecture, which dramatically reduces memory accesses. In embodiments where the memory is multi-ported and distributed, a CSA may sustain many more outstanding memory requests and utilize more bandwidth than a core. These advantages may combine to yield an energy level per watt that is only a small percentage over the cost of the bare arithmetic circuitry. For example, in the case of an integer multiply, a CSA may consume no more than 25% more energy than the underlying multiplication circuit. Relative to one embodiment of a core, an integer operation in that CSA fabric consumes less than 1/30th of the energy per integer operation.
From a programming perspective, the application-specific malleability of embodiments of the CSA architecture yields significant advantages over a vector processing unit (VPU). In traditional, inflexible architectures, the number of functional units, like floating divide or the various transcendental mathematical functions, must be chosen at design time based on some expected use case. In embodiments of the CSA architecture, such functions may be configured (e.g., by a user and not a manufacturer) into the fabric based on the requirement of each application. Application throughput may thereby be further increased. Simultaneously, the compute density of embodiments of the CSA improves by avoiding hardening such functions, and instead provision more instances of primitive functions like floating multiplication. These advantages may be significant in HPC workloads, some of which spend 75% of floating execution time in transcendental functions.
Certain embodiments of the CSA represents a significant advance as a dataflow-oriented spatial architectures, e.g., the PEs of this disclosure may be smaller, but also more energy-efficient. These improvements may directly result from the combination of dataflow-oriented PEs with a lightweight, circuit-switched interconnect, for example, which has single-cycle latency, e.g., in contrast to a packet-switched network (e.g., with, at a minimum, a 300% higher latency). Certain embodiments of PEs support 32-bit or 64-bit operation. Certain embodiments herein permit the introduction of new application-specific PEs, for example, for machine learning or security, and not merely a homogeneous combination. Certain embodiments herein combine lightweight dataflow-oriented processing elements with a lightweight, low-latency network to form an energy efficient computational fabric.
In order for certain spatial architectures to be successful, programmers are to configure them with relatively little effort, e.g., while obtaining significant power and performance superiority over sequential cores. Certain embodiments herein provide for a CSA (e.g., spatial fabric) that is easily programmed (e.g., by a compiler), power efficient, and highly parallel. Certain embodiments herein provide for a (e.g., interconnect) network that achieves these three goals. From a programmability perspective, certain embodiments of the network provide flow controlled channels, e.g., which correspond to the control-dataflow graph (CDFG) model of execution used in compilers. Certain network embodiments utilize dedicated, circuit switched links, such that program performance is easier to reason about, both by a human and a compiler, because performance is predictable. Certain network embodiments offer both high bandwidth and low latency. Certain network embodiments (e.g., static, circuit switching) provides a latency of 0 to 1 cycle (e.g., depending on the transmission distance.) Certain network embodiments provide for a high bandwidth by laying out several networks in parallel, e.g., and in low-level metals. Certain network embodiments communicate in low-level metals and over short distances, and thus are very power efficient.
Certain embodiments of networks include architectural support for flow control. For example, in spatial accelerators composed of small processing elements (PEs), communications latency and bandwidth may be critical to overall program performance. Certain embodiments herein provide for a light-weight, circuit-switched network which facilitates communication between PEs in spatial processing arrays, such as the spatial array shown in
Spatial architectures, such as the one shown in
Operations may be executed based on the availability of their inputs and the status of the PE. A PE may obtain operands from input channels and write results to output channels, although internal register state may also be used. Certain embodiments herein include a configurable dataflow-friendly PE.
Instruction registers may be set during a special configuration step. During this step, auxiliary control wires and state, in addition to the inter-PE network, may be used to stream in configuration across the several PEs comprising the fabric. As result of parallelism, certain embodiments of such a network may provide for rapid reconfiguration, e.g., a tile sized fabric may be configured in less than about 10 microseconds.
Implementing distributed data channels may include two paths, illustrated in
The network may be statically configured, e.g., in addition to PEs being statically configured. During the configuration step, configuration bits may be set at each network component. These bits control, for example, the mux selections and flow control functions. A network may comprise a plurality of networks, e.g., a data path network and a flow control path network. A network or plurality of networks may utilize paths of different widths (e.g., a first width, and a narrower or wider width). In one embodiment, a data path network has a wider (e.g., bit transport) width than the width of a flow control path network. In one embodiment, each of a first network and a second network includes their own data path network and flow control path network, e.g., data path network A and flow control path network A and wider data path network B and flow control path network B.
Certain embodiments of a network are bufferless, and data is to move between producer and consumer in a single cycle. Certain embodiments of a network are also boundless, that is, the network spans the entire fabric. In one embodiment, one PE is to communicate with any other PE in a single cycle. In one embodiment, to improve routing bandwidth, several networks may be laid out in parallel between rows of PEs.
Relative to FPGAs, certain embodiments of networks herein have three advantages: area, frequency, and program expression. Certain embodiments of networks herein operate at a coarse grain, e.g., which reduces the number configuration bits, and thereby the area of the network. Certain embodiments of networks also obtain area reduction by implementing flow control logic directly in circuitry (e.g., silicon). Certain embodiments of hardened network implementations also enjoys a frequency advantage over FPGA. Because of an area and frequency advantage, a power advantage may exist where a lower voltage is used at throughput parity. Finally, certain embodiments of networks provide better high-level semantics than FPGA wires, especially with respect to variable timing, and thus those certain embodiments are more easily targeted by compilers. Certain embodiments of networks herein may be thought of as a set of composable primitives for the construction of distributed, point-to-point data channels.
In certain embodiments, a multicast source may not assert its data valid unless it receives a ready signal from each sink. Therefore, an extra conjunction and control bit may be utilized in the multicast case.
Like certain PEs, the network may be statically configured. During this step, configuration bits are set at each network component. These bits control, for example, the mux selection and flow control function. The forward path of our network requires some bits to swing its muxes. In the example shown in
For the third flow control box from the left in
In embodiments, CSA 802 may be partitioned to two or more regions to protect a system-level program (e.g., an OS) from user-level programs and/or to protect user-level programs from each other. A privileged configuration mechanism, described below, may be used to assign different portions (e.g., portions 802A and 802B) of the spatial fabric to different programs (e.g., based on a process identifier or PID (e.g., PID0 and PID1)) for their exclusive use, such that programs cannot observe or interfere with the operation of other programs residing in the same spatial fabric. PIDs may also be loaded into the fabric memory interface using the privileged configuration mechanism.
In certain embodiments, a CSA includes an array of heterogeneous PEs, in which the fabric is composed of several types of PEs each of which implement only a subset of the dataflow operators. By way of example,
PE execution may proceed in a dataflow style. Based on the configuration microcode, the scheduler may examine the status of the PE ingress and egress buffers, and, when all the inputs for the configured operation have arrived and the egress buffer of the operation is available, orchestrates the actual execution of the operation by a dataflow operator (e.g., on the ALU). The resulting value may be placed in the configured egress buffer. Transfers between the egress buffer of one PE and the ingress buffer of another PE may occur asynchronously as buffering becomes available. In certain embodiments, PEs are provisioned such that at least one dataflow operation completes per cycle. Section 2 discussed dataflow operator encompassing primitive operations, such as add, xor, or pick. Certain embodiments may provide advantages in energy, area, performance, and latency. In one embodiment, with an extension to a PE control path, more fused combinations may be enabled. In one embodiment, the width of the processing elements is 64 bits, e.g., for the heavy utilization of double-precision floating point computation in HPC and to support 64-bit memory addressing.
Embodiments of the CSA microarchitecture provide a hierarchy of networks which together provide an implementation of the architectural abstraction of latency-insensitive channels across multiple communications scales. The lowest level of CSA communications hierarchy may be the local network. The local network may be statically circuit switched, e.g., using configuration registers to swing multiplexor(s) in the local network data-path to form fixed electrical paths between communicating PEs. In one embodiment, the configuration of the local network is set once per dataflow graph, e.g., at the same time as the PE configuration. In one embodiment, static, circuit switching optimizes for energy, e.g., where a large majority (perhaps greater than 95%) of CSA communications traffic will cross the local network. A program may include terms which are used in multiple expressions. To optimize for this case, embodiments herein provide for hardware support for multicast within the local network. Several local networks may be ganged together to form routing channels, e.g., which are interspersed (as a grid) between rows and columns of PEs. As an optimization, several local networks may be included to carry control tokens. In comparison to a FPGA interconnect, a CSA local network may be routed at the granularity of the data-path, and another difference may be a CSA's treatment of control. One embodiment of a CSA local network is explicitly flow controlled (e.g., back-pressured). For example, for each forward data-path and multiplexor set, a CSA is to provide a backward-flowing flow control path that is physically paired with the forward data-path. The combination of the two microarchitectural paths may provide a low-latency, low-energy, low-area, point-to-point implementation of the latency-insensitive channel abstraction. In one embodiment, a CSA's flow control lines are not visible to the user program, but they may be manipulated by the architecture in service of the user program. For example, the exception handling mechanisms described in Section 2.2 may be achieved by pulling flow control lines to a “not present” state upon the detection of an exceptional condition. This action may not only gracefully stalls those parts of the pipeline which are involved in the offending computation, but may also preserve the machine state leading up the exception, e.g., for diagnostic analysis. The second network layer, e.g., the mezzanine network, may be a shared, packet-switched network. The mezzanine network (e.g., the network schematically indicated by the dotted box in
The composability of channels across network layers may be extended to higher level network layers at the inter-tile, inter-die, and fabric granularities.
For example, suppose the operation of this processing (e.g., compute) element is (or includes) what is called call a pick in
For example, suppose the operation of this processing (e.g., compute) element is (or includes) what is called call a switch in
Multiple networks (e.g., interconnects) may be connected to a processing element, e.g., (input) networks 902, 904, 906 and (output) networks 908, 910, 912. The connections may be switches, e.g., as discussed in reference to
Data input buffer 924 and data input buffer 926 may perform similarly, e.g., local network 904 (e.g., set up as a data (as opposed to control) interconnect) is depicted as being switched (e.g., connected) to data input buffer 924. In this embodiment, a data path (e.g., network as in
A processing element 900 may be stalled from execution until its operands (e.g., a control input value and its corresponding data input value or values) are received and/or until there is room in the output buffer(s) of the processing element 900 for the data that is to be produced by the execution of the operation on those operands.
The request address file (RAF) circuit, a simplified version of which is shown in
However, spatial programs may not require any ordering for correct operation, or may self-order requests and responses outside of the memory subsystem. Therefore, embodiments of the invention provide for bypassing the memory system re-order buffer (ROB).
Processors typically allow multiple memory load requests to be in-flight simultaneously in order to reduce the performance lost due to the latency of memory responses. On general purpose machines, loads are tracked using registers: load instructions specify target registers and consumers of the load read the targeted register. Spatial accelerators such as coarse grained reconfigurable arrays do not use registers. Instead, memory reads are initiated on a request channel and responses arrive on a response channel. For correct computation, accelerators must have some mechanism for matching responses with their corresponding requests. One way to accomplish this is by returning responses in the order they were requested. On complex memory subsystems with caches or banks, this is not the most efficient approach. Read requests that hit in high levels of the cache return with lower latency and are thus available before older requests that miss in caches. At least two approaches have been developed in response to this problem. One approach to insert a ROB to track outstanding read requests. The ROB consumes read responses and sorts them so that read responses are returned to the accelerator in the order they were requested. Another approach is to add a unique tag field to each read request and return the tag with the read responses, making it possible to match requests with responses. Both methods have advantages: the first is less complex, and the second is higher performance since reads are returned to the accelerator as they become available.
In an embodiment of the invention, a hybrid of the first and second approach is to add a flag to indicate whether a read response should be sorted before being returned. Accelerator client code indicates whether read responses should be ordered. This selection to order or not to reorder may be either static, with a single choice for the lifetime of a configuration, or dynamic, with the choice provided as part of the memory system command.
The second major functionality of the RAF circuit may be to provide support in the form of address translation and a page walker. Incoming virtual addresses may be translated to physical addresses using a channel-associative translation lookaside buffer (TLB). In an embodiment, RAF circuitry may include a path to bypass address translation hardware (e.g., the page walker and/or TLB) such that the memory interface may operate with reduced power consumption. Requests from the CSA to the memory interface may include a tag to indicate whether the requested address is a physical address or a virtual address. The tag may be used to bypass and/or disable the address translation hardware if no address translation is needed (e.g., the requested address is a physical address).
In various embodiments, the selection of using or bypassing the address translation hardware may be dynamic or static (e.g., with a single choice made for the lifetime of a configuration. In various embodiments, the selection mechanism may select between different translation mechanisms (not simple on or off). For example, any of a TLB-style translation mechanism, a ranged or segmented translation scheme, or no translation may be selected.
To provide ample memory bandwidth, each CSA tile may include multiple RAF circuits. Like the various PEs of the fabric, the RAF circuits may operate in a dataflow-style by checking for the availability of input arguments and output buffering, if required, before selecting a memory operation to execute. Unlike some PEs, however, the RAF circuit is multiplexed among several co-located memory operations. A multiplexed RAF circuit may be used to minimize the area overhead of its various subcomponents, e.g., to share the Accelerator Cache Interface (ACI) port (described in more detail in Section 3.4), shared virtual memory (SVM) support hardware, mezzanine network interface, and other hardware management facilities. However, there are some program characteristics that may also motivate this choice. In one embodiment, a (e.g., valid) dataflow graph is to poll memory in a shared virtual memory system. Memory-latency-bound programs, like graph traversals, may utilize many separate memory operations to saturate memory bandwidth due to memory-dependent control flow. Although each RAF may be multiplexed, a CSA may include multiple (e.g., between 8 and 32) RAFs at a tile granularity to ensure adequate cache bandwidth. RAFs may communicate with the rest of the fabric via both the local network and the mezzanine network. Where RAFs are multiplexed, each RAF may be provisioned with several ports into the local network. These ports may serve as a minimum-latency, highly-deterministic path to memory for use by latency-sensitive or high-bandwidth memory operations. In addition, a RAF may be provisioned with a mezzanine network endpoint, e.g., which provides memory access to runtime services and distant user-level memory accessors.
As an example for a load, an address arrives into queue 1022 which the scheduler 1012 matches up with a load in 1010. A completion buffer slot for this load is assigned in the order the address arrived. Assuming this particular load in the graph has no dependencies specified, the address and completion buffer slot are sent off to the memory system by the scheduler (e.g., via memory command 1042). When the result returns to mux 1040 (shown schematically), it is stored into the completion buffer slot it specifies (e.g., as it carried the target slot all along though the memory system). The completion buffer sends results back into local network (e.g., local network 1002, 1004, 1006, or 1008) in the order the addresses arrived.
Stores may be similar except both address and data have to arrive before any operation is sent off to the memory system.
As shown in
RAF 1070 includes a programmable allocator, a hardware architecture that permits developers to implement memory allocation policies. Policies are implemented by setting programmable registers in the allocator. Policies may examine state within the memory subsystem and memory clients in deciding which requests are accepted. Policies may be adaptive and include state elements which track the behavior of the memory subsystem over time. Policies may be changed dynamically by re-programming the allocator and may be changed while the accelerator is operating.
In embodiments, a RAF allocator may consist of the following state elements, replicated per client channel: two bound registers and a client occupancy counter tracking the number of in-flight requests associated with that channel. Bound registers specify the maximum allowable number of requests outstanding for a channel, and are programmer configurable. In addition, the allocator may include regional state elements: the regional occupancy counter tracks the number of requests in-flight for all channels sharing the RAF and programmer configurable threshold register. The threshold register and regional counter are used to select between bound registers, permitting the allocator to dynamically adapt to changing regional behavior in the memory system. If the regional usage is below the threshold, the ‘light’ bound register is used. Otherwise, the ‘heavy’ bound register is used.
The programmer configurable registers of the general allocator may be set by programmers statically, at configuration time, or dynamically, in response to changing program behavior at run time to implement any of policies A through E, as described below. Each policy may alternatively be implemented in fixed hardware, as described.
Policy A: Greedy Allocation
A greedy policy allocates RAF slots to requests as soon as the requests arrive, without consideration of other activity within the memory subsystem. To achieve a greedy policy using the allocator, all ‘light’ bounds are set to infinity and the regional threshold register is also set to infinity. In a fixed embodiment, since the greedy policy does not require any state, its optimized implementation requires no logic. Greedy allocation handles bursty requests well, since a single client can theoretically obtain all the buffering in the RAF. However, the policy may experience significant performance degradation in the presence of long-latency cache misses.
Policy B: Static Allocation
In this policy, each memory channel is given a fixed number of slots to use by setting the ‘light’ bound registers and the regional threshold to infinity. The number of slots given to each client need not be the same, but the sum total of slots for all clients must be less than the total number of slots in the RAF. In a fixed embodiment, the policy may be minimally implemented as branch and bound registers. Although the pointer-based RAF structure can be used to implement static allocation, simpler policies based on array indexing may also be used. In the extreme, the size of the buffers allocated to each channel may be fixed in hardware. This yields simplicity, but permits no programmer configuration. This policy guarantees some slots, and therefore QoS, to each memory client. However, the policy does not cope with dynamic behaviors such as large request bursts from a single client.
Policy C: Prioritized Allocation
This policy relaxes the constraint on policy B that the sum of slots for all clients be equal to total number of buffer slots. Unlike policy B, this policy requires the pointer-based RAF structure because slots may be dynamically allocated to different channels. However, the policy does not require the ‘heavy’ bound registers or the regional counter. This policy may guarantee some slots, and therefore QoS, to each memory client depending on the setting of the bound registers. However, the policy does support request bursts from a single client, if that client has a high bound set.
Policy D: Basic Waterlevel
This policy leverages regional usage to improve overall performance of the memory subsystem. In this policy, the threshold counter is set to some “waterlevel” value. The ‘light’ bound registers are set to infinity, while the ‘heavy’ bound registers are set to 1. In a fixed embodiment, the minimal implementation of this policy is the threshold variable and some logic to observe the emptiness of each channel. The waterlevel policy guarantees minimal QoS to each client by shutting off clients with in-flight requests as the RAF gets full. The waterlevel policy circumvents many of the problem corner cases of Policy A, while retaining the capability to handle bursts of memory traffic. For example, if a memory client has a long-latency miss, it can partially fill the RAF, but other clients will be guaranteed at least some space. In a fixed embodiment, the waterlevel policy also requires minimal implementation area.
Policy E: Prioritized Waterlevel
The basic waterlevel policy guarantees a slot to each client channel in the case that the RAF is heavily utilized. The prioritized waterlevel policy instead guarantees one channel, or a small set of channels, all remaining slots in the RAF in the case of heavy utilization. To achieve this, high priority channels have their ‘heavy’ bound registers set to infinity, while all other channels have the ‘heavy’ bound registers set to 0. This policy does not require the ‘light’ bound registers. The prioritized waterlevel policy effectively grants a channel or set of channels guaranteed QoS, while permitting the handling of bursts in other channels under light utilization.
A feature of spatial architectures is that they are distributed. Memory subsystems of these architectures are no different: they are comprised of many distributed memory interfaces. In some cases, these interfaces may be multiplexed and many memory interfaces may share a single port to memory. By using the source of a memory request in combination with the request address to index into the TLB structure, a lower associativity TLB may be used to reduce power consumption while maintaining the performance of a high associativity TLB.
In the case of a translation miss, the requesting channel is marked as stalled. No further requests are issued from that channel until the outstanding request is satisfied. The missing request is placed in a miss status holding register (MSHR) for tracking. Requests from other channels may proceed, until the TLB runs out of MSHR resources.
When loading a translation, the page table or second-level TLB will contain information about whether the translation exists. If the translation is known to exist, then the channel translation is searched and the translation is optionally loaded in to the shared translation buffer.
Scheduling may not resume on a particular channel until it its head translation has resolved. Other channels may still participate in scheduling.
Dataflow graphs may be capable of generating a profusion of (e.g., word granularity) requests in parallel. Thus, certain embodiments of the CSA provide a cache subsystem with sufficient bandwidth to service the CSA. A heavily banked cache microarchitecture, e.g., as shown in
Certain HPC applications are characterized by their need for significant floating point bandwidth. To meet this need, embodiments of a CSA may be provisioned with multiple (e.g., between 128 and 256 each) of floating add and multiplication PEs, e.g., depending on tile configuration. A CSA may provide a few other extended precision modes, e.g., to simplify math library implementation. CSA floating point PEs may support both single and double precision, but lower precision PEs may support machine learning workloads. A CSA may provide an order of magnitude more floating point performance than a processor core. In one embodiment, in addition to increasing floating point bandwidth, in order to power all of the floating point units, the energy consumed in floating point operations is reduced. For example, to reduce energy, a CSA may selectively gate the low-order bits of the floating point multiplier array. In examining the behavior of floating point arithmetic, the low order bits of the multiplication array may often not influence the final, rounded product.
Given this maximum carry, if the result of the carry region is less than 2c-g, where the carry region is c bits wide, then the gated region may be ignored since it does not influence the result region. Increasing g means that it is more likely the gated region will be needed, while increasing c means that, under random assumption, the gated region will be unused and may be disabled to avoid energy consumption. In embodiments of a CSA floating multiplication PE, a two stage pipelined approach is utilized in which first the carry region is determined and then the gated region is determined if it is found to influence the result. If more information about the context of the multiplication is known, a CSA more aggressively tune the size of the gated region. In FMA, the multiplication result may be added to an accumulator, which is often much larger than either of the multiplicands. In this case, the addend exponent may be observed in advance of multiplication and the CSDA may adjust the gated region accordingly. One embodiment of the CSA includes a scheme in which a context value, which bounds the minimum result of a computation, is provided to related multipliers, in order to select minimum energy gating configurations.
In certain embodiment, a CSA includes a heterogeneous and distributed fabric, and consequently, runtime service implementations are to accommodate several kinds of PEs in a parallel and distributed fashion. Although runtime services in a CSA may be critical, they may be infrequent relative to user-level computation. Certain implementations, therefore, focus on overlaying services on hardware resources. To meet these goals, CSA runtime services may be cast as a hierarchy, e.g., with each layer corresponding to a CSA network. At the tile level, a single external-facing controller may accept or send service commands to an associated core with the CSA tile. A tile-level controller may serve to coordinate regional controllers at the RAFs, e.g., using the ACI network. In turn, regional controllers may coordinate local controllers at certain mezzanine network stops. At the lowest level, service specific micro-protocols may execute over the local network, e.g., during a special mode controlled through the mezzanine controllers. The micro-protocols may permit each PE (e.g., PE class by type) to interact with the runtime service according to its own needs. Parallelism is thus implicit in this hierarchical organization, and operations at the lowest levels may occur simultaneously. This parallelism may enable the configuration of a CSA tile in between hundreds of nanoseconds to a few microseconds, e.g., depending on the configuration size and its location in the memory hierarchy. Embodiments of the CSA thus leverage properties of dataflow graphs to improve implementation of each runtime service. One key observation is that runtime services may need only to preserve a legal logical view of the dataflow graph, e.g., a state that can be produced through some ordering of dataflow operator executions. Services may generally not need to guarantee a temporal view of the dataflow graph, e.g., the state of a dataflow graph in a CSA at a specific point in time. This may permit the CSA to conduct most runtime services in a distributed, pipelined, and parallel fashion, e.g., provided that the service is orchestrated to preserve the logical view of the dataflow graph. The local configuration micro-protocol may be a packet-based protocol overlaid on the local network. Configuration targets may be organized into a configuration chain, e.g., which is fixed in the microarchitecture. Fabric (e.g., PE) targets may be configured one at a time, e.g., using a single extra register per target to achieve distributed coordination. To start configuration, a controller may drive an out-of-band signal which places all fabric targets in its neighborhood into an unconfigured, paused state and swings multiplexors in the local network to a pre-defined conformation. As the fabric (e.g., PE) targets are configured, that is they completely receive their configuration packet, they may set their configuration microprotocol registers, notifying the immediately succeeding target (e.g., PE) that it may proceed to configure using the subsequent packet. There is no limitation to the size of a configuration packet, and packets may have dynamically variable length. For example, PEs configuring constant operands may have a configuration packet that is lengthened to include the constant field (e.g., X and Y in
Since CSA is a ‘channel-based’ architecture, in the sense that all communications are implicitly flow controlled, embodiments of the invention may create partitions in the CSA by manipulating only the ready/enable signals of the channel communications protocol. In particular, minor modifications may be made to the network to make it possible to pull these signals to inactive values.
The partitionable regions may be coarse or fine, depending on the level of protection desired versus the overhead to be tolerated. In embodiments, boundary bits may be at any number of network crossings to provide for configuring boundaries at those points in the fabric, with any number of network crossings and/or PEs between potential boundaries.
Extraction may proceed in much the same way as configuration. The local network may be conformed to extract data from one target at a time, and state bits used to achieve distributed coordination. A CSA may orchestrate extraction to be non-destructive, that is, at the completion of extraction each extractable target has returned to its starting state. In this implementation, all state in the target may be circulated to an egress register tied to the local network in a scan-like fashion. Although in-place extraction may be achieved by introducing new paths at the register-transfer level (RTL), or using existing lines to provide the same functionalities with lower overhead. Like configuration, hierarchical extraction is achieved in parallel.
The ability to compile programs written in high-level languages onto a CSA may be essential for industry adoption. This section gives a high-level overview of compilation strategies for embodiments of a CSA. First is a proposal for a CSA software framework that illustrates the desired properties of an ideal production-quality toolchain. Next, a prototype compiler framework is discussed. A “control-to-dataflow conversion” is then discussed, e.g., to converts ordinary sequential control-flow code into CSA dataflow assembly code.
A key portion of the compiler may be implemented in the control-to-dataflow conversion pass, or dataflow conversion pass for short. This pass takes in a function represented in control flow form, e.g., a control-flow graph (CFG) with sequential machine instructions operating on virtual registers, and converts it into a dataflow function that is conceptually a graph of dataflow operations (instructions) connected by latency-insensitive channels (LICs). This section gives a high-level description of this pass, describing how it conceptually deals with memory operations, branches, and loops in certain embodiments.
First, consider the simple case of converting straight-line sequential code to dataflow. The dataflow conversion pass may convert a basic block of sequential code, such as the code shown in
To convert programs with multiple basic blocks and conditionals to dataflow, the compiler generates special dataflow operators to replace the branches. More specifically, the compiler uses switch operators to steer outgoing data at the end of a basic block in the original CFG, and pick operators to select values from the appropriate incoming channel at the beginning of a basic block. As a concrete example, consider the code and corresponding dataflow graph in
Control Equivalence: Consider a single-entry-single-exit control flow graph G with two basic blocks A and B. A and B are control-equivalent if all complete control flow paths through G visit A and B the same number of times.
LIC Replacement: In a control flow graph G, suppose an operation in basic block A defines a virtual register x, and an operation in basic block B that uses x. Then a correct control-to-dataflow transformation can replace x with a latency-insensitive channel only if A and B are control equivalent. The control-equivalence relation partitions the basic blocks of a CFG into strong control-dependence regions.
Another important class of CFGs in dataflow conversion are CFGs for single-entry-single-exit loops, a common form of loop generated in (LLVM) IR. These loops may be almost acyclic, except for a single back edge from the end of the loop back to a loop header block. The dataflow conversion pass may use same high-level strategy to convert loops as for branches, e.g., it inserts switches at the end of the loop to direct values out of the loop (either out the loop exit or around the back-edge to the beginning of the loop), and inserts picks at the beginning of the loop to choose between initial values entering the loop and values coming through the back edge.
In one embodiment, the core writes a command into a memory queue and a CSA (e.g., the plurality of processing elements) monitors the memory queue and begins executing when the command is read. In one embodiment, the core executes a first part of a program and a CSA (e.g., the plurality of processing elements) executes a second part of the program. In one embodiment, the core does other work while the CSA is executing its operations.
In certain embodiments, the CSA architecture and microarchitecture provides profound energy, performance, and usability advantages over roadmap processor architectures and FPGAs. In this section, these architectures are compared to embodiments of the CSA and highlights the superiority of CSA in accelerating parallel dataflow graphs relative to each.
The choice of dataflow operators as the fundamental architecture of embodiments of a CSA differentiates those CSAs from a FGPA, and particularly the CSA is as superior accelerator for HPC dataflow graphs arising from traditional programming languages. Dataflow operators are fundamentally asynchronous. This enables embodiments of a CSA not only to have great freedom of implementation in the microarchitecture, but it also enables them to simply and succinctly accommodate abstract architectural concepts. For example, embodiments of a CSA naturally accommodate many memory microarchitectures, which are essentially asynchronous, with a simple load-store interface. One need only examine an FPGA DRAM controller to appreciate the difference in complexity. Embodiments of a CSA also leverage asynchrony to provide faster and more-fully-featured runtime services like configuration and extraction, which are believed to be four to six orders of magnitude faster than an FPGA. By narrowing the architectural interface, embodiments of a CSA provide control over most timing paths at the microarchitectural level. This allows embodiments of a CSA to operate at a much higher frequency than the more general control mechanism offered in a FPGA. Similarly, clock and reset, which may be architecturally fundamental to FPGAs, are microarchitectural in the CSA, e.g., obviating the need to support them as programmable entities. Dataflow operators may be, for the most part, coarse-grained. By only dealing in coarse operators, embodiments of a CSA improve both the density of the fabric and its energy consumption: CSA executes operations directly rather than emulating them with look-up tables. A second consequence of coarseness is a simplification of the place and route problem. CSA dataflow graphs are many orders of magnitude smaller than FPGA net-lists and place and route time are commensurately reduced in embodiments of a CSA. The significant differences between embodiments of a CSA and a FPGA make the CSA superior as an accelerator, e.g., for dataflow graphs arising from traditional programming languages.
The CSA is a novel computer architecture with the potential to provide enormous performance and energy advantages relative to roadmap processors. Consider the case of computing a single strided address for walking across an array. This case may be important in HPC applications, e.g., which spend significant integer effort in computing address offsets. In address computation, and especially strided address computation, one argument is constant and the other varies only slightly per computation. Thus, only a handful of bits per cycle toggle in the majority of cases. Indeed, it may be shown, using a derivation similar to the bound on floating point carry bits described in Section 3.5, that less than two bits of input toggle per computation in average for a stride calculation, reducing energy by 50% over a random toggle distribution. Were a time-multiplexed approach used, much of this energy savings may be lost. In one embodiment, the CSA achieves approximately 3× energy efficiency over a core while delivering an 8× performance gain. The parallelism gains achieved by embodiments of a CSA may result in reduced program run times, yielding a proportionate, substantial reduction in leakage energy. At the PE level, embodiments of a CSA are extremely energy efficient. A second important question for the CSA is whether the CSA consumes a reasonable amount of energy at the tile level. Since embodiments of a CSA are capable of exercising every floating point PE in the fabric at every cycle, it serves as a reasonable upper bound for energy and power consumption, e.g., such that most of the energy goes into floating point multiply and add.
This section discusses further details for configuration and exception handling.
This section discloses examples of how to configure a CSA (e.g., fabric), how to achieve this configuration quickly, and how to minimize the resource overhead of configuration. Configuring the fabric quickly may be of preeminent importance in accelerating small portions of a larger algorithm, and consequently in broadening the applicability of a CSA. The section further discloses features that allow embodiments of a CSA to be programmed with configurations of different length.
Embodiments of a CSA (e.g., fabric) may differ from traditional cores in that they make use of a configuration step in which (e.g., large) parts of the fabric are loaded with program configuration in advance of program execution. An advantage of static configuration may be that very little energy is spent at runtime on the configuration, e.g., as opposed to sequential cores which spend energy fetching configuration information (an instruction) nearly every cycle. The previous disadvantage of configuration is that it was a coarse-grained step with a potentially large latency, which places an under-bound on the size of program that can be accelerated in the fabric due to the cost of context switching. This disclosure describes a scalable microarchitecture for rapidly configuring a spatial array in a distributed fashion, e.g., that avoids the previous disadvantages.
As discussed above, a CSA may include light-weight processing elements connected by an inter-PE network. Programs, viewed as control-dataflow graphs, are then mapped onto the architecture by configuring the configurable fabric elements (CFEs), for example PEs and the interconnect (fabric) networks. Generally, PEs may be configured as dataflow operators and once all input operands arrive at the PE, some operation occurs, and the results are forwarded to another PE or PEs for consumption or output. PEs may communicate over dedicated virtual circuits which are formed by statically configuring the circuit-switched communications network. These virtual circuits may be flow controlled and fully back-pressured, e.g., such that PEs will stall if either the source has no data or destination is full. At runtime, data may flow through the PEs implementing the mapped algorithm. For example, data may be streamed in from memory, through the fabric, and then back out to memory. Such a spatial architecture may achieve remarkable performance efficiency relative to traditional multicore processors: compute, in the form of PEs, may be simpler and more numerous than larger cores and communications may be direct, as opposed to an extension of the memory system.
Embodiments of a CSA may not utilize (e.g., software controlled) packet switching, e.g., packet switching that requires significant software assistance to realize, which slows configuration. Embodiments of a CSA include out-of-band signaling in the network (e.g., of only 2-3 bits, depending on the feature set supported) and a fixed configuration topology to avoid the need for significant software support.
One key difference between embodiments of a CSA and the approach used in FPGAs is that a CSA approach may use a wide data word, is distributed, and includes mechanisms to fetch program data directly from memory. Embodiments of a CSA may not utilize JTAG-style single bit communications in the interest of area efficiency, e.g., as that may require milliseconds to completely configure a large FPGA fabric.
Embodiments of a CSA include a distributed configuration protocol and microarchitecture to support this protocol. Initially, configuration state may reside in memory. Multiple (e.g., distributed) local configuration controllers (boxes) (LCCs) may stream portions of the overall program into their local region of the spatial fabric, e.g., using a combination of a small set of control signals and the fabric-provided network. State elements may be used at each CFE to form configuration chains, e.g., allowing individual CFEs to self-program without global addressing.
Embodiments of a CSA include specific hardware support for the formation of configuration chains, e.g., not software establishing these chains dynamically at the cost of increasing configuration time. Embodiments of a CSA are not purely packet-switched and do include extra out-of-band control wires (e.g., control is not sent through the data path requiring extra cycles to strobe this information and reserialize this information). Embodiments of a CSA decreases configuration latency by fixing the configuration ordering and by providing explicit out-of-band control (e.g., by at least a factor of two), while not significantly increasing network complexity.
Embodiments of a CSA do not use a serial mechanism for configuration in which data is streamed bit by bit into the fabric using a JTAG-like protocol. Embodiments of a CSA utilize a coarse-grained fabric approach. In certain embodiments, adding a few control wires or state elements to a 64 or 32-bit-oriented CSA fabric has a lower cost relative to adding those same control mechanisms to a 4 or 6 bit fabric.
Embodiments of a CSA include hardware that provides for efficient, distributed, low-latency configuration of a heterogeneous spatial fabric. This may be achieved according to four techniques. First, a hardware entity, the local configuration controller (LCC) is utilized, for example, as in
LCC operation may begin when it receives a pointer to a code segment. Depending on the LCC microarchitecture, this pointer (e.g., stored in pointer register 2406) may come either over a network (e.g., from within the CSA (fabric) itself) or through a memory system access to the LCC. When it receives such a pointer, the LCC optionally drains relevant state from its portion of the fabric for context storage, and then proceeds to immediately reconfigure the portion of the fabric for which it is responsible. The program loaded by the LCC may be a combination of configuration data for the fabric and control commands for the LCC, e.g., which are lightly encoded. As the LCC streams in the program portion, it may interprets the program as a command stream and perform the appropriate encoded action to configure (e.g., load) the fabric.
Two different microarchitectures for the LCC are shown in
In certain embodiments, configuration relies on 2-8 extra, out-of-band control channels to improve configuration speed, as defined below, and/or to enable privileged configuration. For example, configuration controller 2402 may include the following control channels, e.g., CFG_START control channel 2408, CFG_VALID control channel 2410, CFG_DONE control channel 2412, and CFG_PRIV 2414, with examples of each discussed in Table 2 below.
Generally, the handling of configuration information may be left to the implementer of a particular CFE. For example, a selectable function CFE may have a provision for setting registers using an existing data path, while a fixed function CFE might simply set a configuration register.
Due to long wire delays when programming a large set of CFEs, the CFG_VALID signal may be treated as a clock/latch enable for CFE components. Since this signal is used as a clock, in one embodiment the duty cycle of the line is at most 50%. As a result, configuration throughput is approximately halved. Optionally, a second CFG_VALID signal may be added to enable continuous programming.
In one embodiment, only CFG_START is strictly communicated on an independent coupling (e.g., wire), for example, CFG_VALID and CFG_DONE may be overlaid on top of other network couplings.
In embodiments, the CFG_PRIV signal may be used to indicate the beginning of privileged configuration and to indicate to configurable privileged state elements (such as boundary bits, as described above) that they should accept incoming values according to the configuration micro-protocol. The use of the CFG_PRIV signal for privileged configuration may resemble the use of the CFG_START signal for user mode (non-privileged) configuration, as described above.
In embodiments, the privileged configuration mode may be invoked by a privileged program, such as an OS, to modify security modes within the fabric, for example, to set dynamic partitions in the fabric in the case of multiprogramming, as described above in connection with
Upon invocation of privileged configuration, the tile-level controller sends the appropriate configuration messages to the configuration units, which will then invoke a privileged configuration on their respective sub-regions. Depending on the choice of micro-protocol (described below), the memory interface unit may require additional virtual memory translation mechanisms to support any privileged address spaces used by the invoking program. In embodiments, various privileged configuration modes and/or micro-protocols may be used.
In embodiments with separate configuration modes, privileged configuration may be separate from user mode configuration, but may use the same configuration control bits used in the user mode configuration micro-protocol. Thus, privileged configuration is analogous to user mode configuration, except that CFG_PRIV is asserted to indicate that it is the privileged configuration bits that are being modified. Since, in general, this form of privileged configuration may be non-destructive to most existing configuration bits, it may be invoked at runtime if a few modifications are made. In particular, when this configuration mode is entered, the local network multiplexors are swung to form a path between the configuration controller and the configuration target. If the local multiplexor state is retained, then no additional configuration will be required. The muxes revert to their original configuration once their use in his configuration mode is complete. Therefore, it may be possible to set privilege bits without the need to reconfigure or even halt a running user program. Alternatively, without these modifications, a separate configuration may be used to place the CSA fabric into a no-op state before attempting privileged configuration.
In embodiments with a unified configuration mode, privileged configuration and user mode configuration may use the same micro-protocol. According to a first approach, privileged configuration occurs separately from normal user configuration. In this case, the user portion of the privileged configuration would be a no-op configuration. During subsequent user configurations, the privileged configuration mode is not used, and the configuration associated with the privilege bits is either ignored or not included in the user configuration binary. According to a second approach, the privileged configuration state will include a state bit to automatically bypass its configuration.
To partition the CSA, the OS or other privileged code, may first determine the appropriate settings for the desired user workloads and construct a privileged configuration file based on the desired partitioning, and then dispatch the privileged configuration file to the CSA based on the above techniques.
In embodiments in which the forward data path and backwards control path are separately configurable, a security vulnerability may exist if malicious code configures its data path in one direction and its control path in another direction, in that the data path may arise from a different partition, while the control path may arise from the local partition. To mitigate this vulnerability, a single configuration state may be used to control both the data path and the control path switching. In this manner, the two paths are physically paired by the hardware, enabling partitioning to be achieved by simply manipulating the control path.
Thus, user-visible architecture may be separated from privileged architecture, so as to minimize the trusted code base and to permit user-level reconfiguration.
To reduce the overhead of configuration, certain embodiments of a CSA make use of existing network infrastructure to communicate configuration data. A LCC may make use of both a chip-level memory hierarchy and a fabric-level communications networks to move data from storage into the fabric. As a result, in certain embodiments of a CSA, the configuration infrastructure adds no more than 2% to the overall fabric area and power.
Reuse of network resources in certain embodiments of a CSA may cause a network to have some hardware support for a configuration mechanism. Circuit switched networks of embodiments of a CSA cause an LCC to set their multiplexors in a specific way for configuration when the ‘CFG_START’ signal is asserted. Packet-switched networks do not require extension, although LCC endpoints (e.g., configuration terminators) use a specific address in the packet switched network. Network reuse is optional, and some embodiments may find dedicated configuration buses to be more convenient.
Each CFE may maintain a bit denoting whether or not it has been configured (see, e.g.,
Internal to the CFE, this bit may be used to drive flow control ready signals. For example, when the configuration bit is de-asserted, network control signals may automatically be clamped to a value that prevent data from flowing, while, within PEs, no operations or other actions will be scheduled.
Dealing with High-Delay Configuration Paths
One embodiment of an LCC may drive a signal over a long distance, e.g., through many multiplexors and with many loads. Thus, it may be difficult for a signal to arrive at a distant CFE within a short clock cycle. In certain embodiments, configuration signals are at some division (e.g., fraction of) of the main (e.g., CSA) clock frequency to ensure digital timing discipline at configuration. Clock division may be utilized in an out-of-band signaling protocol, and does not require any modification of the main clock tree.
Since certain configuration schemes are distributed and have non-deterministic timing due to program and memory effects, different portions of the fabric may be configured at different times. As a result, certain embodiments of a CSA provide mechanisms to prevent inconsistent operation among configured and unconfigured CFEs. Generally, consistency is viewed as a property required of and maintained by CFEs themselves, e.g., using the internal CFE state. For example, when a CFE is in an unconfigured state, it may claim that its input buffers are full, and that its output is invalid. When configured, these values will be set to the true state of the buffers. As enough of the fabric comes out of configuration, these techniques may permit it to begin operation. This has the effect of further reducing context-switching latency, e.g., if long-latency memory requests are issued early.
Different CFEs may have different configuration word widths. For smaller CFE configuration words, implementers may balance delay by equitably assigning CFE configuration loads across the network wires. To balance loading on network wires, one option is to assign configuration bits to different portions of network wires to limit the net delay on any one wire. Wide data words may be handled by using serialization/deserialization techniques. These decisions may be taken on a per-fabric basis to optimize the behavior of a specific CSA (e.g., fabric). Network controller (e.g., one or more of network controller 2210 and network controller 2212 may communicate with each domain (e.g., subset) of the CSA (e.g., fabric), for example, to send configuration information to one or more LCCs.
Embodiments of a CSA may be an energy-efficient and high-performance means of accelerating user applications. When considering whether a program (e.g., a dataflow graph thereof) may be successfully accelerated by an accelerator, both the time to configure the accelerator and the time to run the program may be considered. If the run time is short, then the configuration time may play a large role in determining successful acceleration. Therefore, to maximize the domain of accelerable programs, in some embodiments the configuration time is made as short as possible. One or more configuration caches may be included in a CSA, e.g., such that the high bandwidth, low-latency store enables rapid reconfiguration. Next is a description of several embodiments of a configuration cache.
In one embodiment, during configuration, the configuration hardware (e.g., LCC) optionally accesses the configuration cache to obtain new configuration information. The configuration cache may operate either as a traditional address based cache, or in an OS managed mode, in which configurations are stored in the local address space and addressed by reference to that address space. If configuration state is located in the cache, then no requests to the backing store are to be made in certain embodiments. In certain embodiments, this configuration cache is separate from any (e.g., lower level) shared cache in the memory hierarchy.
In certain embodiments, a configuration cache may have the configuration data pre-loaded into it, e.g., either by external direction or internal direction. This may allow reduction in the latency to load programs. Certain embodiments herein provide for an interface to a configuration cache which permits the loading of new configuration state into the cache, e.g., even if a configuration is running in the fabric already. The initiation of this load may occur from either an internal or external source. Embodiments of a pre-loading mechanism further reduce latency by removing the latency of cache loading from the configuration path.
Certain embodiments of a CSA (e.g., a spatial fabric) include large amounts of instruction and configuration state, e.g., which is largely static during the operation of the CSA. Thus, the configuration state may be vulnerable to soft errors. Rapid and error-free recovery of these soft errors may be critical to the long-term reliability and performance of spatial systems.
Certain embodiments herein provide for a rapid configuration recovery loop, e.g., in which configuration errors are detected and portions of the fabric immediately reconfigured. Certain embodiments herein include a configuration controller, e.g., with reliability, availability, and serviceability (RAS) reprogramming features. Certain embodiments of CSA include circuitry for high-speed configuration, error reporting, and parity checking within the spatial fabric. Using a combination of these three features, and optionally, a configuration cache, a configuration/exception handling circuit may recover from soft errors in configuration. When detected, soft errors may be conveyed to a configuration cache which initiates an immediate reconfiguration of (e.g., that portion of) the fabric. Certain embodiments provide for a dedicated reconfiguration circuit, e.g., which is faster than any solution that would be indirectly implemented in the fabric. In certain embodiments, co-located exception and configuration circuit cooperates to reload the fabric on configuration error detection.
Some portions of an application targeting a CSA (e.g., spatial array) may be run infrequently or may be mutually exclusive with other parts of the program. To save area, to improve performance, and/or reduce power, it may be useful to time multiplex portions of the spatial fabric among several different parts of the program dataflow graph. Certain embodiments herein include an interface by which a CSA (e.g., via the spatial program) may request that part of the fabric be reprogrammed. This may enable the CSA to dynamically change itself according to dynamic control flow. Certain embodiments herein allow for fabric initiated reconfiguration (e.g., reprogramming). Certain embodiments herein provide for a set of interfaces for triggering configuration from within the fabric. In some embodiments, a PE issues a reconfiguration request based on some decision in the program dataflow graph. This request may travel a network to our new configuration interface, where it triggers reconfiguration. Once reconfiguration is completed, a message may optionally be returned notifying of the completion. Certain embodiments of a CSA thus provide for a program (e.g., dataflow graph) directed reconfiguration capability.
Configure-by-address—In this mode, the fabric makes a direct request to load configuration data from a particular address.
Configure-by-reference—In this mode the fabric makes a request to load a new configuration, e.g., by a pre-determined reference ID. This may simplify the determination of the code to load, since the location of the code has been abstracted.
A CSA may include a higher level configuration controller to support a multicast mechanism to cast (e.g., via network indicated by the dotted box) configuration requests to multiple (e.g., distributed or local) configuration controllers. This may enable a single configuration request to be replicated across larger portions of the fabric, e.g., triggering a broad reconfiguration.
Certain embodiments of a CSA may also experience an exception (e.g., exceptional condition), for example, floating point underflow. When these conditions occur, a special handlers may be invoked to either correct the program or to terminate it. Certain embodiments herein provide for a system-level architecture for handling exceptions in spatial fabrics. Since certain spatial fabrics emphasize area efficiency, embodiments herein minimize total area while providing a general exception mechanism. Certain embodiments herein provides a low area means of signaling exceptional conditions occurring in within a CSA (e.g., a spatial array). Certain embodiments herein provide an interface and signaling protocol for conveying such exceptions, as well as a PE-level exception semantics. Certain embodiments herein are dedicated exception handling capabilities, e.g., and do not require explicit handling by the programmer.
One embodiment of a CSA exception architecture consists of four portions, e.g., shown in
Processing element 3000 may include processing element 900 from
The initiation of the exception may either occur explicitly, by the execution of a programmer supplied instruction, or implicitly when a hardened error condition (e.g., a floating point underflow) is detected. Upon an exception, the PE 3000 may enter a waiting state, in which it waits to be serviced by the eventual exception handler, e.g., external to the PE 3000. The contents of the exception packet depend on the implementation of the particular PE, as described below.
A (e.g., local) exception network steers exception packets from PE 3000 to the mezzanine exception network. Exception network (e.g., 3013) may be a serial, packet switched network consisting of a (e.g., single) control wire and one or more data wires, e.g., organized in a ring or tree topology, e.g., for a subset of PEs. Each PE may have a (e.g., ring) stop in the (e.g., local) exception network, e.g., where it can arbitrate to inject messages into the exception network.
PE endpoints needing to inject an exception packet may observe their local exception network egress point. If the control signal indicates busy, the PE is to wait to commence inject its packet. If the network is not busy, that is, the downstream stop has no packet to forward, then the PE will proceed commence injection.
Network packets may be of variable or fixed length. Each packet may begin with a fixed length header field identifying the source PE of the packet. This may be followed by a variable number of PE-specific field containing information, for example, including error codes, data values, or other useful status information.
The mezzanine exception aggregator 2904 is responsible for assembling local exception network into larger packets and sending them to the tile-level exception aggregator 2902. The mezzanine exception aggregator 2904 may pre-pend the local exception packet with its own unique ID, e.g., ensuring that exception messages are unambiguous. The mezzanine exception aggregator 2904 may interface to a special exception-only virtual channel in the mezzanine network, e.g., ensuring the deadlock-freedom of exceptions.
The mezzanine exception aggregator 2904 may also be able to directly service certain classes of exception. For example, a configuration request from the fabric may be served out of the mezzanine network using caches local to the mezzanine network stop.
The final stage of the exception system is the tile-level exception aggregator 2902. The tile-level exception aggregator 2902 is responsible for collecting exceptions from the various mezzanine-level exception aggregators (e.g., 2904) and forwarding them to the appropriate servicing hardware (e.g., core). As such, the tile-level exception aggregator 2902 may include some internal tables and controller to associate particular messages with handler routines. These tables may be indexed either directly or with a small state machine in order to steer particular exceptions.
Like the mezzanine exception aggregator, the tile-level exception aggregator may service some exception requests. For example, it may initiate the reprogramming of a large portion of the PE fabric in response to a specific exception.
Certain embodiments of a CSA include an extraction controller(s) to extract data from the fabric. The below discusses embodiments of how to achieve this extraction quickly and how to minimize the resource overhead of data extraction. Data extraction may be utilized for such critical tasks as exception handling and context switching. Certain embodiments herein extract data from a heterogeneous spatial fabric by introducing features that allow extractable fabric elements (EFEs) (for example, PEs, network controllers, and/or switches) with variable and dynamically variable amounts of state to be extracted.
Embodiments of a CSA include a distributed data extraction protocol and microarchitecture to support this protocol. Certain embodiments of a CSA include multiple local extraction controllers (LECs) which stream program data out of their local region of the spatial fabric using a combination of a (e.g., small) set of control signals and the fabric-provided network. State elements may be used at each extractable fabric element (EFE) to form extraction chains, e.g., allowing individual EFEs to self-extract without global addressing.
Embodiments of a CSA do not use a local network to extract program data. Embodiments of a CSA include specific hardware support (e.g., an extraction controller) for the formation of extraction chains, for example, and do not rely on software to establish these chains dynamically, e.g., at the cost of increasing extraction time. Embodiments of a CSA are not purely packet-switched and do include extra out-of-band control wires (e.g., control is not sent through the data path requiring extra cycles to strobe and reserialize this information). Embodiments of a CSA decrease extraction latency by fixing the extraction ordering and by providing explicit out-of-band control (e.g., by at least a factor of two), while not significantly increasing network complexity.
Embodiments of a CSA do not use a serial mechanism for data extraction, in which data is streamed bit by bit from the fabric using a JTAG-like protocol. Embodiments of a CSA utilize a coarse-grained fabric approach. In certain embodiments, adding a few control wires or state elements to a 64 or 32-bit-oriented CSA fabric has a lower cost relative to adding those same control mechanisms to a 4 or 6 bit fabric.
Embodiments of a CSA include hardware that provides for efficient, distributed, low-latency extraction from a heterogeneous spatial fabric. This may be achieved according to four techniques. First, a hardware entity, the local extraction controller (LEC) is utilized, for example, as in
The following sections describe the operation of the various components of embodiments of an extraction network.
LEC operation may begin when it receives a pointer to a buffer (e.g., in virtual memory) where fabric state will be written, and, optionally, a command controlling how much of the fabric will be extracted. Depending on the LEC microarchitecture, this pointer (e.g., stored in pointer register 3304) may come either over a network or through a memory system access to the LEC. When it receives such a pointer (e.g., command), the LEC proceeds to extract state from the portion of the fabric for which it is responsible. The LEC may stream this extracted data out of the fabric into the buffer provided by the external caller.
Two different microarchitectures for the LEC are shown in
In certain embodiments, extraction relies on 2-8 extra, out-of-band signals to improve configuration speed, as defined below. Signals driven by the LEC may be labelled LEC. Signals driven by the EFE (e.g., PE) may be labelled EFE. Configuration controller 3302 may include the following control channels, e.g., LEC_EXTRACT control channel 3406, LEC_START control channel 3308, LEC_STROBE control channel 3310, and EFE_COMPLETE control channel 3312, with examples of each discussed in Table 3 below.
Generally, the handling of extraction may be left to the implementer of a particular EFE. For example, selectable function EFE may have a provision for dumping registers using an existing data path, while a fixed function EFE might simply have a multiplexor.
Due to long wire delays when programming a large set of EFEs, the LEC_STROBE signal may be treated as a clock/latch enable for EFE components. Since this signal is used as a clock, in one embodiment the duty cycle of the line is at most 50%. As a result, extraction throughput is approximately halved. Optionally, a second LEC_STROBE signal may be added to enable continuous extraction.
In one embodiment, only LEC_START is strictly communicated on an independent coupling (e.g., wire), for example, other control channels may be overlayed on existing network (e.g., wires).
To reduce the overhead of data extraction, certain embodiments of a CSA make use of existing network infrastructure to communicate extraction data. A LEC may make use of both a chip-level memory hierarchy and a fabric-level communications networks to move data from the fabric into storage. As a result, in certain embodiments of a CSA, the extraction infrastructure adds no more than 2% to the overall fabric area and power.
Reuse of network resources in certain embodiments of a CSA may cause a network to have some hardware support for an extraction protocol. Circuit switched networks require of certain embodiments of a CSA cause a LEC to set their multiplexors in a specific way for configuration when the ‘LEC_START’ signal is asserted. Packet-switched networks do not require extension, although LEC endpoints (e.g., extraction terminators) use a specific address in the packet switched network. Network reuse is optional, and some embodiments may find dedicated configuration buses to be more convenient.
Each EFE may maintain a bit denoting whether or not it has exported its state. This bit may de-asserted when the extraction start signal is driven, and then asserted once the particular EFE finished extraction. In one extraction protocol, EFEs are arranged to form chains with the EFE extraction state bit determining the topology of the chain. A EFE may read the extraction state bit of the immediately adjacent EFE. If this adjacent EFE has its extraction bit set and the current EFE does not, the EFE may determine that it owns the extraction bus. When an EFE dumps its last data value, it may drives the ‘EFE_DONE’ signal and sets its extraction bit, e.g., enabling upstream EFEs to configure for extraction. The network adjacent to the EFE may observe this signal and also adjust its state to handle the transition. As a base case to the extraction process, an extraction terminator (e.g., extraction terminator 3104 for LEC 3102 or extraction terminator 3108 for LEC 3106 in
Internal to the EFE, this bit may be used to drive flow control ready signals. For example, when the extraction bit is de-asserted, network control signals may automatically be clamped to a values that prevent data from flowing, while, within PEs, no operations or actions will be scheduled.
Dealing with High-delay Paths
One embodiment of a LEC may drive a signal over a long distance, e.g., through many multiplexors and with many loads. Thus, it may be difficult for a signal to arrive at a distant EFE within a short clock cycle. In certain embodiments, extraction signals are at some division (e.g., fraction of) of the main (e.g., CSA) clock frequency to ensure digital timing discipline at extraction. Clock division may be utilized in an out-of-band signaling protocol, and does not require any modification of the main clock tree.
Since certain extraction scheme are distributed and have non-deterministic timing due to program and memory effects, different members of the fabric may be under extraction at different times. While LEC_EXTRACT is driven, all network flow control signals may be driven logically low, e.g., thus freezing the operation of a particular segment of the fabric.
An extraction process may be non-destructive. Therefore a set of PEs may be considered operational once extraction has completed. An extension to an extraction protocol may allow PEs to optionally be disabled post extraction. Alternatively, beginning configuration during the extraction process will have similar effect in embodiments.
In some cases, it may be expedient to extract a single PE. In this case, an optional address signal may be driven as part of the commencement of the extraction process. This may enable the PE targeted for extraction to be directly enabled. Once this PE has been extracted, the extraction process may cease with the lowering of the LEC_EXTRACT signal. In this way, a single PE may be selectively extracted, e.g., by the local extraction controller.
In an embodiment where the LEC writes extracted data to memory (for example, for post-processing, e.g., in software), it may be subject to limited memory bandwidth. In the case that the LEC exhausts its buffering capacity, or expects that it will exhaust its buffering capacity, it may stops strobing the LEC_STROBE signal until the buffering issue has resolved.
Note that in certain figures (e.g.,
Supercomputing at the ExaFLOP scale may be a challenge in high-performance computing, a challenge which is not likely to be met by conventional von Neumann architectures. To achieve ExaFLOPs, embodiments of a CSA provide a heterogeneous spatial array that targets direct execution of (e.g., compiler-produced) dataflow graphs. In addition to laying out the architectural principles of embodiments of a CSA, the above also describes and evaluates embodiments of a CSA which showed performance and energy of larger than 10× over existing products. Compiler-generated code may have significant performance and energy gains over roadmap architectures. As a heterogeneous, parametric architecture, embodiments of a CSA may be readily adapted to all computing uses. For example, a mobile version of CSA might be tuned to 32-bits, while a machine-learning focused array might feature significant numbers of vectorized 8-bit multiplication units. The main advantages of embodiments of a CSA are high performance and extreme energy efficiency, characteristics relevant to all forms of computing ranging from supercomputing and datacenter to the internet-of-things.
In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of two dataflow graphs each comprising a plurality of nodes, wherein a first dataflow graph and a second dataflow graph are be overlaid into a first and second portion, respectively, of the interconnect network and a first and second subset, respectively, of the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the first and second subsets of the plurality of processing elements are to perform a first and second operation, respectively, when incoming first and second, respectively, operand sets arrive at the plurality of processing elements.
In an embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive a first input of a first dataflow graph comprising a first plurality of nodes, wherein the first dataflow graph is to be overlaid into a first portion of the interconnect network and a first subset of the plurality of processing elements with each of the first plurality of nodes represented as a dataflow operator in the first subset of the plurality of processing elements, and the first subset of the plurality of processing elements is to perform a first operation when a first incoming operand set arrives at the first subset of the plurality of processing elements; the interconnect network also to receive a second input of a second dataflow graph comprising a second plurality of nodes, wherein the second dataflow graph is to be overlaid into a second portion the interconnect network and a second subset of the plurality of processing elements with each of the second plurality of nodes represented as a dataflow operator in the second subset of the plurality of processing elements, and the second subset of the plurality of processing elements is to perform a second operation when a second incoming operand set arrives at the second subset of the plurality of processing elements.
The first subset of the plurality of processing elements may be assigned to a first program and the second subset of the plurality of processing elements may be assigned to a second program. The interconnect network may be partitioned into the first portion and the second portion to protect the first program and the second program from each other. The first program may be a user-level program. The second program may be a system-level program. The second program may be a user-level program. The first program and the second program may be protected from each other by a boundary to be implemented with configurable privileged state elements. The configurable privileged state elements may be configured to prevent communication across the boundary.
In an embodiment, a method includes partitioning, into a first portion and a second portion, a plurality of processing elements of a processor and an interconnect network between the plurality of processing elements; receiving a first input of a first dataflow graph comprising a first plurality of nodes; overlaying the first dataflow graph into the first portion with each of the first plurality of nodes represented as a dataflow operator in a first subset of the plurality of processing elements; receiving a second input of a second dataflow graph comprising a second plurality of nodes; overlaying the second dataflow graph into the second portion with each of the second plurality of nodes represented as a dataflow operator in a second subset of the plurality of processing elements; performing a first operation of the first dataflow graph with the first portion of the interconnect network and the first subset of the plurality of processing elements when a first incoming operand set arrives at the first subset of the plurality of processing elements; and performing a second operation of the second dataflow graph with the second portion of the interconnect network and the second subset of the plurality of processing elements when a second incoming operand set arrives at the second subset of the plurality of processing elements.
The method may also include assigning a first program to the first subset of the plurality of processing elements; and assigning a second program to the second subset of the plurality of processing elements. The interconnect network may be partitioned into the first portion and the second portion to protect the first program and the second program from each other. The first program may be a user-level program. The second program may be a system-level program. The second program may be a user-level program. The first program and the second program may be protected from each other by a boundary to be implemented with configurable privileged state elements. The partitioning may include configuring the configurable privileged state elements to prevent communication across the boundary.
In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
A processing element of the plurality of processing elements may stall execution when a backpressure signal from a downstream processing element indicates that storage in the downstream processing element is not available for an output of the processing element. The processor may include a flow control path network to carry the backpressure signal according to the dataflow graph. A dataflow token may cause an output from a dataflow operator receiving the dataflow token to be sent to an input buffer of a particular processing element of the plurality of processing elements. The operation may include a memory access and the plurality of processing elements comprises a memory-accessing dataflow operator that is not to perform the memory access until receiving a memory dependency token from a logically previous dataflow operator. The plurality of processing elements may include a first type of processing element and a second, different type of processing element.
In another embodiment, a method receiving an input of a dataflow graph comprising a plurality of nodes; overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements; and performing an operation of the dataflow graph with the interconnect network and the plurality of processing elements by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
The method may include stalling execution by a processing element of the plurality of processing elements when a backpressure signal from a downstream processing element indicates that storage in the downstream processing element is not available for an output of the processing element. The method may include sending the backpressure signal on a flow control path network according to the dataflow graph. A dataflow token may cause an output from a dataflow operator receiving the dataflow token to be sent to an input buffer of a particular processing element of the plurality of processing elements. The method may include not performing a memory access until receiving a memory dependency token from a logically previous dataflow operator, wherein the operation comprises the memory access and the plurality of processing elements comprises a memory-accessing dataflow operator. The method may include providing a first type of processing element and a second, different type of processing element of the plurality of processing elements.
In yet another embodiment, an apparatus includes a data path network between a plurality of processing elements; and a flow control path network between the plurality of processing elements, wherein the data path network and the flow control path network are to receive an input of a dataflow graph comprising a plurality of nodes, the dataflow graph is to be overlaid into the data path network, the flow control path network, and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
The flow control path network may carry backpressure signals to a plurality of dataflow operators according to the dataflow graph. A dataflow token sent on the data path network to a dataflow operator may cause an output from the dataflow operator to be sent to an input buffer of a particular processing element of the plurality of processing elements on the data path network. The data path network may be a static, circuit-switched network to carry the respective, input operand set to each of the dataflow operators according to the dataflow graph. The flow control path network may transmit a backpressure signal according to the dataflow graph from a downstream processing element to indicate that storage in the downstream processing element is not available for an output of the processing element. At least one data path of the data path network and at least one flow control path of the flow control path network may form a channelized circuit with backpressure control. The flow control path network may pipeline at least two of the plurality of processing elements in series.
In another embodiment, a method includes receiving an input of a dataflow graph comprising a plurality of nodes; and overlaying the dataflow graph into a plurality of processing elements of a processor, a data path network between the plurality of processing elements, and a flow control path network between the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
The method may include carrying backpressure signals with the flow control path network to a plurality of dataflow operators according to the dataflow graph. The method may include sending a dataflow token on the data path network to a dataflow operator to cause an output from the dataflow operator to be sent to an input buffer of a particular processing element of the plurality of processing elements on the data path network. The method may include setting a plurality of switches of the data path network and/or a plurality of switches of the flow control path network to carry the respective, input operand set to each of the dataflow operators according to the dataflow graph, wherein the data path network is a static, circuit-switched network. The method may include transmitting a backpressure signal with the flow control path network according to the dataflow graph from a downstream processing element to indicate that storage in the downstream processing element is not available for an output of the processing element. The method may include forming a channelized circuit with backpressure control with at least one data path of the data path network and at least one flow control path of the flow control path network.
In yet another embodiment, a processor includes a plurality of processing elements; and a network means between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the network means and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
In another embodiment, an apparatus includes a data path means between a plurality of processing elements; and a flow control path means between the plurality of processing elements, wherein the data path means and the flow control path means are to receive an input of a dataflow graph comprising a plurality of nodes, the dataflow graph is to be overlaid into the data path means, the flow control path means, and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
In one embodiment, a processor includes an array of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the array of processing elements with each node represented as a dataflow operator in the array of processing elements, and the array of processing elements is to perform an operation when an incoming operand set arrives at the array of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
The array of processing element may not perform the operation until the incoming operand set arrives at the array of processing elements and storage in the array of processing elements is available for output of the second operation. The array of processing elements may include a network (or channel(s)) to carry dataflow tokens and control tokens to a plurality of dataflow operators. The operation may include a memory access and the array of processing elements may include a memory-accessing dataflow operator that is not to perform the memory access until receiving a memory dependency token from a logically previous dataflow operator. Each processing element may perform only one or two operations of the dataflow graph.
In another embodiment, a method includes receiving an input of a dataflow graph comprising a plurality of nodes; overlaying the dataflow graph into an array of processing elements of the processor with each node represented as a dataflow operator in the array of processing elements; and performing an operation of the dataflow graph with the array of processing elements when an incoming operand set arrives at the array of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
The array of processing elements may not perform the operation until the incoming operand set arrives at the array of processing elements and storage in the array of processing elements is available for output of the second operation. The array of processing elements may include a network carrying dataflow tokens and control tokens to a plurality of dataflow operators. The operation may include a memory access and the array of processing elements comprises a memory-accessing dataflow operator that is not to perform the memory access until receiving a memory dependency token from a logically previous dataflow operator. Each processing element may perform only one or two operations of the dataflow graph.
In yet another embodiment, a non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method including receiving an input of a dataflow graph comprising a plurality of nodes; overlaying the dataflow graph into an array of processing elements of the processor with each node represented as a dataflow operator in the array of processing elements; and performing an operation of the dataflow graph with the array of processing elements when an incoming operand set arrives at the array of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
The array of processing element may not perform the operation until the incoming operand set arrives at the array of processing elements and storage in the array of processing elements is available for output of the second operation. The array of processing elements may include a network carrying dataflow tokens and control tokens to a plurality of dataflow operators. The operation may include a memory access and the array of processing elements comprises a memory-accessing dataflow operator that is not to perform the memory access until receiving a memory dependency token from a logically previous dataflow operator. Each processing element may perform only one or two operations of the dataflow graph.
In another embodiment, a processor includes means to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the means with each node represented as a dataflow operator in the means, and the means is to perform an operation when an incoming operand set arrives at the means. The plurality of processing elements is partitioned to protect programs from each other.
In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform a second operation when an incoming operand set arrives at the plurality of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
The processor may further comprise a plurality of configuration controllers, each configuration controller is coupled to a respective subset of the plurality of processing elements, and each configuration controller is to load configuration information from storage and cause coupling of the respective subset of the plurality of processing elements according to the configuration information. The processor may include a plurality of configuration caches, and each configuration controller is coupled to a respective configuration cache to fetch the configuration information for the respective subset of the plurality of processing elements. The first operation performed by the execution unit may prefetch configuration information into each of the plurality of configuration caches. Each of the plurality of configuration controllers may include a reconfiguration circuit to cause a reconfiguration for at least one processing element of the respective subset of the plurality of processing elements on receipt of a configuration error message from the at least one processing element. Each of the plurality of configuration controllers may a reconfiguration circuit to cause a reconfiguration for the respective subset of the plurality of processing elements on receipt of a reconfiguration request message, and disable communication with the respective subset of the plurality of processing elements until the reconfiguration is complete. The processor may include a plurality of exception aggregators, and each exception aggregator is coupled to a respective subset of the plurality of processing elements to collect exceptions from the respective subset of the plurality of processing elements and forward the exceptions to the core for servicing. The processor may include a plurality of extraction controllers, each extraction controller is coupled to a respective subset of the plurality of processing elements, and each extraction controller is to cause state data from the respective subset of the plurality of processing elements to be saved to memory.
In another embodiment, a method includes decoding an instruction with a decoder of a core of a processor into a decoded instruction; executing the decoded instruction with an execution unit of the core of the processor to perform a first operation; receiving an input of a dataflow graph comprising a plurality of nodes; overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements; and performing a second operation of the dataflow graph with the interconnect network and the plurality of processing elements when an incoming operand set arrives at the plurality of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
The method may include loading configuration information from storage for respective subsets of the plurality of processing elements and causing coupling for each respective subset of the plurality of processing elements according to the configuration information. The method may include fetching the configuration information for the respective subset of the plurality of processing elements from a respective configuration cache of a plurality of configuration caches. The first operation performed by the execution unit may be prefetching configuration information into each of the plurality of configuration caches. The method may include causing a reconfiguration for at least one processing element of the respective subset of the plurality of processing elements on receipt of a configuration error message from the at least one processing element. The method may include causing a reconfiguration for the respective subset of the plurality of processing elements on receipt of a reconfiguration request message; and disabling communication with the respective subset of the plurality of processing elements until the reconfiguration is complete. The method may include collecting exceptions from a respective subset of the plurality of processing elements; and forwarding the exceptions to the core for servicing. The method may include causing state data from a respective subset of the plurality of processing elements to be saved to memory.
In yet another embodiment, a non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method including decoding an instruction with a decoder of a core of a processor into a decoded instruction; executing the decoded instruction with an execution unit of the core of the processor to perform a first operation; receiving an input of a dataflow graph comprising a plurality of nodes; overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements; and performing a second operation of the dataflow graph with the interconnect network and the plurality of processing elements when an incoming operand set arrives at the plurality of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
The method may include loading configuration information from storage for respective subsets of the plurality of processing elements and causing coupling for each respective subset of the plurality of processing elements according to the configuration information. The method may include fetching the configuration information for the respective subset of the plurality of processing elements from a respective configuration cache of a plurality of configuration caches. The first operation performed by the execution unit may be prefetching configuration information into each of the plurality of configuration caches. The method may include causing a reconfiguration for at least one processing element of the respective subset of the plurality of processing elements on receipt of a configuration error message from the at least one processing element. The method may include causing a reconfiguration for the respective subset of the plurality of processing elements on receipt of a reconfiguration request message; and disabling communication with the respective subset of the plurality of processing elements until the reconfiguration is complete. The method may include collecting exceptions from a respective subset of the plurality of processing elements; and forwarding the exceptions to the core for servicing. The method may include causing state data from a respective subset of the plurality of processing elements to be saved to memory.
In another embodiment, a processor includes a plurality of processing elements; and means between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the m and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The plurality of processing elements is partitioned to protect programs from each other.
In yet another embodiment, an apparatus comprises a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform any method disclosed herein. An apparatus may be as described in the detailed description. A method may be as described in the detailed description.
In another embodiment, a non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising any method disclosed herein.
An instruction set (e.g., for execution by a core) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands. A set of SIMD extensions referred to as the Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX) coding scheme has been released and/or published (e.g., see Intel® 64 and IA-32 Architectures Software Developer's Manual, June 2016; and see Intel® Architecture Instruction Set Extensions Programming Reference, February 2016).
Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.
A vector friendly instruction format is an instruction format that is suited for vector instructions (e.g., there are certain fields specific to vector operations). While embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations the vector friendly instruction format.
While embodiments of the disclosure will be described in which the vector friendly instruction format supports the following: a 64 byte vector operand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) data element widths (or sizes) (and thus, a 64 byte vector consists of either 16 doubleword-size elements or alternatively, 8 quadword-size elements); a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit (1 byte) data element widths (or sizes); a 32 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); and a 16 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., 256 byte vector operands) with more, less, or different data element widths (e.g., 128 bit (16 byte) data element widths).
The class A instruction templates in
The generic vector friendly instruction format 3600 includes the following fields listed below in the order illustrated in
Format field 3640—a specific value (an instruction format identifier value) in this field uniquely identifies the vector friendly instruction format, and thus occurrences of instructions in the vector friendly instruction format in instruction streams. As such, this field is optional in the sense that it is not needed for an instruction set that has only the generic vector friendly instruction format.
Base operation field 3642—its content distinguishes different base operations.
Register index field 3644—its content, directly or through address generation, specifies the locations of the source and destination operands, be they in registers or in memory. These include a sufficient number of bits to select N registers from a P×Q (e.g. 32×512, 16×128, 32×1024, 64×1024) register file. While in one embodiment N may be up to three sources and one destination register, alternative embodiments may support more or less sources and destination registers (e.g., may support up to two sources where one of these sources also acts as the destination, may support up to three sources where one of these sources also acts as the destination, may support up to two sources and one destination).
Modifier field 3646—its content distinguishes occurrences of instructions in the generic vector instruction format that specify memory access from those that do not; that is, between no memory access 3605 instruction templates and memory access 3620 instruction templates. Memory access operations read and/or write to the memory hierarchy (in some cases specifying the source and/or destination addresses using values in registers), while non-memory access operations do not (e.g., the source and destinations are registers). While in one embodiment this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, less, or different ways to perform memory address calculations.
Augmentation operation field 3650—its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment of the disclosure, this field is divided into a class field 3668, an alpha field 3652, and a beta field 3654. The augmentation operation field 3650 allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions.
Scale field 3660—its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses 2scale* index+base).
Displacement Field 3662A—its content is used as part of memory address generation (e.g., for address generation that uses 2scale*index+base+displacement).
Displacement Factor Field 3662B (note that the juxtaposition of displacement field 3662A directly over displacement factor field 3662B indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2scale*index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 3674 (described later herein) and the data manipulation field 3654C. The displacement field 3662A and the displacement factor field 3662B are optional in the sense that they are not used for the no memory access 3605 instruction templates and/or different embodiments may implement only one or none of the two.
Data element width field 3664—its content distinguishes which one of a number of data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that it is not needed if only one data element width is supported and/or data element widths are supported using some aspect of the opcodes.
Write mask field 3670—its content controls, on a per data element position basis, whether that data element position in the destination vector operand reflects the result of the base operation and augmentation operation. Class A instruction templates support merging-writemasking, while class B instruction templates support both merging- and zeroing-writemasking. When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one embodiment, preserving the old value of each element of the destination where the corresponding mask bit has a 0. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the write mask field 3670 allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While embodiments of the disclosure are described in which the write mask field's 3670 content selects one of a number of write mask registers that contains the write mask to be used (and thus the write mask field's 3670 content indirectly identifies that masking to be performed), alternative embodiments instead or additional allow the mask write field's 3670 content to directly specify the masking to be performed.
Immediate field 3672—its content allows for the specification of an immediate. This field is optional in the sense that is it not present in an implementation of the generic vector friendly format that does not support immediate and it is not present in instructions that do not use an immediate.
Class field 3668—its content distinguishes between different classes of instructions. With reference to
In the case of the non-memory access 3605 instruction templates of class A, the alpha field 3652 is interpreted as an RS field 3652A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round 3652A.1 and data transform 3652A.2 are respectively specified for the no memory access, round type operation 3610 and the no memory access, data transform type operation 3615 instruction templates), while the beta field 3654 distinguishes which of the operations of the specified type is to be performed. In the no memory access 3605 instruction templates, the scale field 3660, the displacement field 3662A, and the displacement scale filed 3662B are not present.
In the no memory access full round control type operation 3610 instruction template, the beta field 3654 is interpreted as a round control field 3654A, whose content(s) provide static rounding. While in the described embodiments of the disclosure the round control field 3654A includes a suppress all floating point exceptions (SAE) field 3656 and a round operation control field 3658, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field 3658).
SAE field 3656—its content distinguishes whether or not to disable the exception event reporting; when the SAE field's 3656 content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler.
Round operation control field 3658—its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field 3658 allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the disclosure where a processor includes a control register for specifying rounding modes, the round operation control field's 3650 content overrides that register value.
In the no memory access data transform type operation 3615 instruction template, the beta field 3654 is interpreted as a data transform field 3654B, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast).
In the case of a memory access 3620 instruction template of class A, the alpha field 3652 is interpreted as an eviction hint field 3652B, whose content distinguishes which one of the eviction hints is to be used (in
Vector memory instructions perform vector loads from and vector stores to memory, with conversion support. As with regular vector instructions, vector memory instructions transfer data from/to memory in a data element-wise fashion, with the elements that are actually transferred is dictated by the contents of the vector mask that is selected as the write mask.
Temporal data is data likely to be reused soon enough to benefit from caching. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely.
Memory Access Instruction Templates—Non-Temporal
Non-temporal data is data unlikely to be reused soon enough to benefit from caching in the 1st-level cache and should be given priority for eviction. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely.
In the case of the instruction templates of class B, the alpha field 3652 is interpreted as a write mask control (Z) field 3652C, whose content distinguishes whether the write masking controlled by the write mask field 3670 should be a merging or a zeroing.
In the case of the non-memory access 3605 instruction templates of class B, part of the beta field 3654 is interpreted as an RL field 3657A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round 3657A.1 and vector length (VSIZE) 3657A.2 are respectively specified for the no memory access, write mask control, partial round control type operation 3612 instruction template and the no memory access, write mask control, VSIZE type operation 3617 instruction template), while the rest of the beta field 3654 distinguishes which of the operations of the specified type is to be performed. In the no memory access 3605 instruction templates, the scale field 3660, the displacement field 3662A, and the displacement scale filed 3662B are not present.
In the no memory access, write mask control, partial round control type operation 3610 instruction template, the rest of the beta field 3654 is interpreted as a round operation field 3659A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler).
Round operation control field 3659A—just as round operation control field 3658, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field 3659A allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the disclosure where a processor includes a control register for specifying rounding modes, the round operation control field's 3650 content overrides that register value.
In the no memory access, write mask control, VSIZE type operation 3617 instruction template, the rest of the beta field 3654 is interpreted as a vector length field 3659B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte).
In the case of a memory access 3620 instruction template of class B, part of the beta field 3654 is interpreted as a broadcast field 3657B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field 3654 is interpreted the vector length field 3659B. The memory access 3620 instruction templates include the scale field 3660, and optionally the displacement field 3662A or the displacement scale field 3662B.
With regard to the generic vector friendly instruction format 3600, a full opcode field 3674 is shown including the format field 3640, the base operation field 3642, and the data element width field 3664. While one embodiment is shown where the full opcode field 3674 includes all of these fields, the full opcode field 3674 includes less than all of these fields in embodiments that do not support all of them. The full opcode field 3674 provides the operation code (opcode).
The augmentation operation field 3650, the data element width field 3664, and the write mask field 3670 allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.
The combination of write mask field and data element width field create typed instructions in that they allow the mask to be applied based on different data element widths.
The various instruction templates found within class A and class B are beneficial in different situations. In some embodiments of the disclosure, different processors or different cores within a processor may support only class A, only class B, or both classes. For instance, a high performance general purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and/or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core that has some mix of templates and instructions from both classes but not all templates and instructions from both classes is within the purview of the disclosure). Also, a single processor may include multiple cores, all of which support the same class or in which different cores support different class. For instance, in a processor with separate graphics and general purpose cores, one of the graphics cores intended primarily for graphics and/or scientific computing may support only class A, while one or more of the general purpose cores may be high performance general purpose cores with out of order execution and register renaming intended for general-purpose computing that support only class B. Another processor that does not have a separate graphics core, may include one more general purpose in-order or out-of-order cores that support both class A and class B. Of course, features from one class may also be implement in the other class in different embodiments of the disclosure. Programs written in a high level language would be put (e.g., just in time compiled or statically compiled) into an variety of different executable forms, including: 1) a form having only instructions of the class(es) supported by the target processor for execution; or 2) a form having alternative routines written using different combinations of the instructions of all classes and having control flow code that selects the routines to execute based on the instructions supported by the processor which is currently executing the code.
It should be understood that, although embodiments of the disclosure are described with reference to the specific vector friendly instruction format 3700 in the context of the generic vector friendly instruction format 3600 for illustrative purposes, the disclosure is not limited to the specific vector friendly instruction format 3700 except where claimed. For example, the generic vector friendly instruction format 3600 contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format 3700 is shown as having fields of specific sizes. By way of specific example, while the data element width field 3664 is illustrated as a one bit field in the specific vector friendly instruction format 3700, the disclosure is not so limited (that is, the generic vector friendly instruction format 3600 contemplates other sizes of the data element width field 3664).
The generic vector friendly instruction format 3600 includes the following fields listed below in the order illustrated in
EVEX Prefix (Bytes 0-3) 3702—is encoded in a four-byte form.
Format Field 3640 (EVEX Byte 0, bits [7:0])—the first byte (EVEX Byte 0) is the format field 3640 and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in one embodiment of the disclosure).
The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fields providing specific capability.
REX field 3705 (EVEX Byte 1, bits [7-5])—consists of a EVEX.R bit field (EVEX Byte 1, bit [7]—R), EVEX.X bit field (EVEX byte 1, bit [6]—X), and 3657BEX byte 1, bit[5]—B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit fields, and are encoded using is complement form, i.e. ZMM0 is encoded as 1111B, ZMM15 is encoded as 0000B. Other fields of the instructions encode the lower three bits of the register indexes as is known in the art (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by adding EVEX.R, EVEX.X, and EVEX.B.
REX′ field 3610—this is the first part of the REX′ field 3610 and is the EVEX.R′ bit field (EVEX Byte 1, bit [4]—R′) that is used to encode either the upper 16 or lower 16 of the extended 32 register set. In one embodiment of the disclosure, this bit, along with others as indicated below, is stored in bit inverted format to distinguish (in the well-known x86 32-bit mode) from the BOUND instruction, whose real opcode byte is 62, but does not accept in the MOD R/M field (described below) the value of 11 in the MOD field; alternative embodiments of the disclosure do not store this and the other indicated bits below in the inverted format. A value of 1 is used to encode the lower 16 registers. In other words, R′Rrrr is formed by combining EVEX.R′, EVEX.R, and the other RRR from other fields.
Opcode map field 3715 (EVEX byte 1, bits [3:0] —mmmm)—its content encodes an implied leading opcode byte (0F, 0F 38, or 0F 3).
Data element width field 3664 (EVEX byte 2, bit [7]—W)—is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the datatype (either 32-bit data elements or 64-bit data elements).
EVEX.vvvv 3720 (EVEX Byte 2, bits [6:3]-vvvv)—the role of EVEX.vvvv may include the following: 1) EVEX.vvvv encodes the first source register operand, specified in inverted (1s complement) form and is valid for instructions with 2 or more source operands; 2) EVEX.vvvv encodes the destination register operand, specified in is complement form for certain vector shifts; or 3) EVEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. Thus, EVEX.vvvv field 3720 encodes the 4 low-order bits of the first source register specifier stored in inverted (1s complement) form. Depending on the instruction, an extra different EVEX bit field is used to extend the specifier size to 32 registers.
EVEX.U 3668 Class field (EVEX byte 2, bit [2]-U)—If EVEX.U=0, it indicates class A or EVEX.U0; if EVEX.U=1, it indicates class B or EVEX.U1.
Prefix encoding field 3725 (EVEX byte 2, bits [1:0]-pp)—provides additional bits for the base operation field. In addition to providing support for the legacy SSE instructions in the EVEX prefix format, this also has the benefit of compacting the SIMD prefix (rather than requiring a byte to express the SIMD prefix, the EVEX prefix requires only 2 bits). In one embodiment, to support legacy SSE instructions that use a SIMD prefix (66H, F2H, F3H) in both the legacy format and in the EVEX prefix format, these legacy SIMD prefixes are encoded into the SIMD prefix encoding field; and at runtime are expanded into the legacy SIMD prefix prior to being provided to the decoder's PLA (so the PLA can execute both the legacy and EVEX format of these legacy instructions without modification). Although newer instructions could use the EVEX prefix encoding field's content directly as an opcode extension, certain embodiments expand in a similar fashion for consistency but allow for different meanings to be specified by these legacy SIMD prefixes. An alternative embodiment may redesign the PLA to support the 2 bit SIMD prefix encodings, and thus not require the expansion.
Alpha field 3652 (EVEX byte 3, bit [7]—EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustrated with α)—as previously described, this field is context specific.
Beta field 3654 (EVEX byte 3, bits [6:4]-SSS, also known as EVEX.s2-0, EVEX.r2-0, EVEX.rr1, EVEX.LL0, EVEX.LLB; also illustrated with βββ)—as previously described, this field is context specific.
REX′ field 3610—this is the remainder of the REX′ field and is the EVEX.V′ bit field (EVEX Byte 3, bit [3]—V′) that may be used to encode either the upper 16 or lower 16 of the extended 32 register set. This bit is stored in bit inverted format. A value of 1 is used to encode the lower 16 registers. In other words, V′VVVV is formed by combining EVEX.V′, EVEX.vvvv.
Write mask field 3670 (EVEX byte 3, bits [2:0]-kkk)—its content specifies the index of a register in the write mask registers as previously described. In one embodiment of the disclosure, the specific value EVEX.kkk=000 has a special behavior implying no write mask is used for the particular instruction (this may be implemented in a variety of ways including the use of a write mask hardwired to all ones or hardware that bypasses the masking hardware).
Real Opcode Field 3730 (Byte 4) is also known as the opcode byte. Part of the opcode is specified in this field.
MOD R/M Field 3740 (Byte 5) includes MOD field 3742, Reg field 3744, and R/M field 3746. As previously described, the MOD field's 3742 content distinguishes between memory access and non-memory access operations. The role of Reg field 3744 can be summarized to two situations: encoding either the destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field 3746 may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.
Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, the scale field's 3650 content is used for memory address generation. SIB.xxx 3754 and SIB.bbb 3756—the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.
Displacement field 3662A (Bytes 7-10)—when MOD field 3742 contains 10, bytes 7-10 are the displacement field 3662A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity.
Displacement factor field 3662B (Byte 7)—when MOD field 3742 contains 01, byte 7 is the displacement factor field 3662B. The location of this field is that same as that of the legacy x86 instruction set 8-bit displacement (disp8), which works at byte granularity. Since disp8 is sign extended, it can only address between −128 and 127 bytes offsets; in terms of 64 byte cache lines, disp8 uses 8 bits that can be set to only four really useful values −128, −64, 0, and 64; since a greater range is often needed, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 3662B is a reinterpretation of disp8; when using displacement factor field 3662B, the actual displacement is determined by the content of the displacement factor field multiplied by the size of the memory operand access (N). This type of displacement is referred to as disp8*N. This reduces the average instruction length (a single byte of used for the displacement but with a much greater range). Such compressed displacement is based on the assumption that the effective displacement is multiple of the granularity of the memory access, and hence, the redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field 3662B substitutes the legacy x86 instruction set 8-bit displacement. Thus, the displacement factor field 3662B is encoded the same way as an x86 instruction set 8-bit displacement (so no changes in the ModRM/SIB encoding rules) with the only exception that disp8 is overloaded to disp8*N. In other words, there are no changes in the encoding rules or encoding lengths but only in the interpretation of the displacement value by hardware (which needs to scale the displacement by the size of the memory operand to obtain a byte-wise address offset). Immediate field 3672 operates as previously described.
When U=1, the alpha field 3652 (EVEX byte 3, bit [7]—EH) is interpreted as the write mask control (Z) field 3652C. When U=1 and the MOD field 3742 contains 11 (signifying a no memory access operation), part of the beta field 3654 (EVEX byte 3, bit [4]—S0) is interpreted as the RL field 3657A; when it contains a 1 (round 3657A.1) the rest of the beta field 3654 (EVEX byte 3, bit [6-5]—S2-1) is interpreted as the round operation field 3659A, while when the RL field 3657A contains a 0 (VSIZE 3657.A2) the rest of the beta field 3654 (EVEX byte 3, bit [6-5]—S2-1) is interpreted as the vector length field 3659B (EVEX byte 3, bit [6-5]—L1-0). When U=1 and the MOD field 3742 contains 00, 01, or 10 (signifying a memory access operation), the beta field 3654 (EVEX byte 3, bits [6:4]—SSS) is interpreted as the vector length field 3659B (EVEX byte 3, bit [6-5]—L1-0) and the broadcast field 3657B (EVEX byte 3, bit [4]—B).
In other words, the vector length field 3659B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field 3659B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format 3700 operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.
Write mask registers 3815—in the embodiment illustrated, there are 8 write mask registers (k0 through k7), each 64 bits in size. In an alternate embodiment, the write mask registers 3815 are 16 bits in size. As previously described, in one embodiment of the disclosure, the vector mask register k0 cannot be used as a write mask; when the encoding that would normally indicate k0 is used for a write mask, it selects a hardwired write mask of 0xFFFF, effectively disabling write masking for that instruction.
General-purpose registers 3825—in the embodiment illustrated, there are sixteen 64-bit general-purpose registers that are used along with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.
Scalar floating point stack register file (x87 stack) 3845, on which is aliased the MMX packed integer flat register file 3850—in the embodiment illustrated, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32/64/80-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.
Alternative embodiments of the disclosure may use wider or narrower registers. Additionally, alternative embodiments of the disclosure may use more, less, or different register files and registers.
Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.
In
The front end unit 3930 includes a branch prediction unit 3932 coupled to an instruction cache unit 3934, which is coupled to an instruction translation lookaside buffer (TLB) 3936, which is coupled to an instruction fetch unit 3938, which is coupled to a decode unit 3940. The decode unit 3940 (or decoder or decoder unit) may decode instructions (e.g., macro-instructions), and generate as an output one or more micro-operations, micro-code entry points, micro-instructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit 3940 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core 3990 includes a microcode ROM or other medium that stores microcode for certain macro-instructions (e.g., in decode unit 3940 or otherwise within the front end unit 3930). The decode unit 3940 is coupled to a rename/allocator unit 3952 in the execution engine unit 3950.
The execution engine unit 3950 includes the rename/allocator unit 3952 coupled to a retirement unit 3954 and a set of one or more scheduler unit(s) 3956. The scheduler unit(s) 3956 represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) 3956 is coupled to the physical register file(s) unit(s) 3958. Each of the physical register file(s) units 3958 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit 3958 comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) 3958 is overlapped by the retirement unit 3954 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit 3954 and the physical register file(s) unit(s) 3958 are coupled to the execution cluster(s) 3960. The execution cluster(s) 3960 includes a set of one or more execution units 3962 and a set of one or more memory access units 3964. The execution units 3962 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) 3956, physical register file(s) unit(s) 3958, and execution cluster(s) 3960 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) 3964). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.
The set of memory access units 3964 is coupled to the memory unit 3970, which includes a data TLB unit 3972 coupled to a data cache unit 3974 coupled to a level 2 (L2) cache unit 3976. In one exemplary embodiment, the memory access units 3964 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 3972 in the memory unit 3970. The instruction cache unit 3934 is further coupled to a level 2 (L2) cache unit 3976 in the memory unit 3970. The L2 cache unit 3976 is coupled to one or more other levels of cache and eventually to a main memory.
By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline 3900 as follows: 1) the instruction fetch 3938 performs the fetch and length decoding stages 3902 and 3904; 2) the decode unit 3940 performs the decode stage 3906; 3) the rename/allocator unit 3952 performs the allocation stage 3908 and renaming stage 3910; 4) the scheduler unit(s) 3956 performs the schedule stage 3912; 5) the physical register file(s) unit(s) 3958 and the memory unit 3970 perform the register read/memory read stage 3914; the execution cluster 3960 perform the execute stage 3916; 6) the memory unit 3970 and the physical register file(s) unit(s) 3958 perform the write back/memory write stage 3918; 7) various units may be involved in the exception handling stage 3922; and 8) the retirement unit 3954 and the physical register file(s) unit(s) 3958 perform the commit stage 3924.
The core 3990 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.), including the instruction(s) described herein. In one embodiment, the core 3990 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.
It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).
While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units 3934/3974 and a shared L2 cache unit 3976, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.
The local subset of the L2 cache 4004 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 4004. Data read by a processor core is stored in its L2 cache subset 4004 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 4004 and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is 1012-bits wide per direction.
Thus, different implementations of the processor 4100 may include: 1) a CPU with the special purpose logic 4108 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 4102A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores 4102A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 4102A-N being a large number of general purpose in-order cores. Thus, the processor 4100 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 4100 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.
The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units 4106, and external memory (not shown) coupled to the set of integrated memory controller units 4114. The set of shared cache units 4106 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit 4112 interconnects the integrated graphics logic 4108, the set of shared cache units 4106, and the system agent unit 4110/integrated memory controller unit(s) 4114, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units 4106 and cores 4102-A-N.
In some embodiments, one or more of the cores 4102A-N are capable of multi-threading. The system agent 4110 includes those components coordinating and operating cores 4102A-N. The system agent unit 4110 may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 4102A-N and the integrated graphics logic 4108. The display unit is for driving one or more externally connected displays.
The cores 4102A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 4102A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.
Referring now to
The optional nature of additional processors 4215 is denoted in
The memory 4240 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 4220 communicates with the processor(s) 4210, 4215 via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection 4295.
In one embodiment, the coprocessor 4245 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub 4220 may include an integrated graphics accelerator.
There can be a variety of differences between the physical resources 4210, 4215 in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.
In one embodiment, the processor 4210 executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor 4210 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 4245. Accordingly, the processor 4210 issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor 4245. Coprocessor(s) 4245 accept and execute the received coprocessor instructions.
Referring now to
Processors 4370 and 4380 are shown including integrated memory controller (IMC) units 4372 and 4382, respectively. Processor 4370 also includes as part of its bus controller units point-to-point (P-P) interfaces 4376 and 4378; similarly, second processor 4380 includes P-P interfaces 4386 and 4388. Processors 4370, 4380 may exchange information via a point-to-point (P-P) interface 4350 using P-P interface circuits 4378, 4388. As shown in
Processors 4370, 4380 may each exchange information with a chipset 4390 via individual P-P interfaces 4352, 4354 using point to point interface circuits 4376, 4394, 4386, 4398. Chipset 4390 may optionally exchange information with the coprocessor 4338 via a high-performance interface 4339. In one embodiment, the coprocessor 4338 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.
A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.
Chipset 4390 may be coupled to a first bus 4316 via an interface 4396. In one embodiment, first bus 4316 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.
As shown in
Referring now to
Referring now to
Embodiments (e.g., of the mechanisms) disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the disclosure may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
Program code, such as code 4330 illustrated in
The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.
One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.
Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
Accordingly, embodiments of the disclosure also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.
In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.
This invention was made with Government support under contract number H98230A-13-D-0124 awarded by the Department of Defense. The Government has certain rights in this invention.
