Claims
- 1. A logic cell for a programmable application specific integrated circuit, comprising:
- a first logic gate
- a second logic gate;
- a third logic gate, said third logic gate having a first input and a second input, said first input of said third logic gate being connected to a first data node;
- a fourth logic gate, said fourth logic gate having an output, said output of the fourth logic gate being connected to said second input of said third logic gate;
- a first multiplexer having one data input from an output of said first logic gate, another data input from an output of said second logic gate, and a select input from an output of said third logic gate;
- a fifth logic gate;
- a sixth logic gate;
- a second multiplexer having one data input from an output of said fifth logic gate, another data input from an output of said sixth logic gate, and a select input from an output of said third logic gate;
- a seventh logic gate, said seventh logic gate having a first input and a second input, said first input being connected to a second data node;
- an eighth logic gate, said eighth logic gate having an output, said output of said eighth logic gate being connected to said second input of said seventh logic gate;
- a third multiplexer having one data input from an output of said first multiplexer, another data input from an output of said second multiplexer, and a select input from an output of said seventh logic gate; and
- a flipflop having an input from an output of said third multiplexer,
- wherein said first, second, third, fourth, fifth, sixth, seventh and eighth logic gates, said first, second and third multiplexers, and said flipflop are all part of said logic cell.
- 2. The logic cell of claim 1, wherein said first, second, third, fifth, sixth and seventh logic gates are AND gates and wherein said first, second and third multiplexers are 2:1 multiplexers.
- 3. A logic cell for a programmable application specific integrated circuit, comprising:
- a first logic gate;
- a second logic gate;
- a third logic gate, said third logic gate having a first input and a second input, said first input of said third logic gate being connected to a first data node;
- a fourth logic gate, said fourth logic gate having an output, said output of the fourth logic gate being connected to said second input of said third logic gate;
- a first multiplexer having at least a first and a second data input, a select input, and an output, said first data input being from an output of said first logic gate, said second data input being from an output of said second logic gate, said select input being from an output of said third logic gate;
- a fifth logic gate;
- a sixth logic gate;
- a second multiplexer having at least a first and a second data input, a select input, and an output, said first data input being from an output of said fifth logic gate, said second data input being from an output of said sixth logic gate, said select input being from an output of said third logic gate;
- a seventh logic gate, said seventh logic gate having a first input and a second input, said first input being connected to a second data node;
- an eighth logic gate, said eighth logic gate having an output, said output of said eighth logic gate being connected to said second input of said seventh logic gate;
- a third multiplexer having one data input from said output of said first multiplexer, another data input from said output of said second multiplexer, and a select input from an output of said seventh logic gate; and
- a flipflop having an input from an output of said third multiplexer,
- wherein said first, second, third, fourth, fifth, sixth, seventh and eighth logic gates, said first, second and third multiplexers, and said flipflop are all part of said logic cell.
- 4. The logic cell of claim 3, wherein said first, second, third, fifth and sixth logic gates are AND gates and wherein said first, second and third multiplexers are 2:1 multiplexers.
Parent Case Info
This application is a continuation application of U.S. application Ser. No. 07/847,137, filed Mar. 6, 1992, now U.S. Pat. No. 5,220,213, which in turn is a continuation application of U.S. application Ser. No. 07/665,103, filed Mar. 6, 1991, now U.S. Pat. No. 5,122,685.
US Referenced Citations (9)
Continuations (2)
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Number |
Date |
Country |
Parent |
847137 |
Mar 1992 |
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Parent |
665103 |
Mar 1991 |
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