"Optimized Reconfigurable Cell Arry (ORCA) Series Field-Programmable Gate Arrays," AT&T Microelectronics, pp. 1-87, Advance Data Sheet, Feb. 1985. |
"The Programmable Logic Data Book," Xilinx, Inc., 1994, pp. 2-5 to 2-102. |
Masumoto, Rodney T., "Configurable On-Chip RAM Incorporated into High Speed Logic Array," IEEE Custom Integrated Circuits Conference, Jun. 1985, CH2157-6/85/0000-0240, pp. 240-243. |
Landry, Steve, "Application -Specific ICs, Relying on RAM, Implement Almost Any Logic Function," Electronic Design, Oct. 31, 1985, pp. 123-130. |
Bursky, Dave, "Shrink Systems with One-Chip Decoder, EPROM, and RAM," Electronic Design, Jul. 28, 1988, pp. 91-94. |
Kawana, Keiichi et al., "An Efficient Logic Block Interconnect Architecture for User-Reprogrammable Gate Array," IEEE 1990 Custom Integrated Circuits Conf., May 1990, CH2860-5/90/0000-0164, pp. 31.3.1 to 31.3.4. |
Shubat, Alexander et al., "A Family of User-Programmable Peripherals with a Functional Unit Architecture," IEEE Jor. of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, 0018-9200/92$03.00, pp. 515-529. |
"AT&T's Orthogonal ORCA Targets the FPGA Future," 8029 Electronic Engineering, 64, No. 786, Jun. 1992, pp. 9-10. |
Bursky, Dave, "FPGA Advances Cut Delays, Add Flexibility," 2328 Electronic Design, 40, No. 20, Oct. 1, 1992, pp. 35-43. |
Smith, Daniel, "Intel's FLEXlogic FPGA Architecture," IEEE 1063-6390/93, 1993 pp. 378-384. |
Bursky, Dave, "Denser, Faster FPGAs Vie for Gate-Array Applications," 2328 Electronic Design, 41, No. 11, May 27, 1993, pp. 55-75. |
Ngai, Kai-Kit Tony, "An SRAM-Programmable Field-Reconfigurable Memory," Presentation at University of Toronto, Canada, Jun. 1993, pp. 1-14. |
Kautz, "Cellular Logic in Memory Arrays," IEEE Trans. on Computers, vol. C-18, No. 8, Aug. 1969, pp. 719-727. |
Stone, "A Logic in Memory Computer," IEEE Trans. on Computers, Jan. 1970, pp. 73-78. |
Manning, "An Approach to Highly Integrated Computer Maintained Cellular Arrays," IEEE Trans. on Computers, vol. C-26, No. 6, Jun. 1977,pp. 536-552. |
Patil et al., "A Programmable Logic Approach for VLSI," IEEE Trans. on Computers, vol. C-28, No. 9, Sep. 1979, pp. 594-601. |
Seitz, "Concurrent VLSI Architectures," IEEE Trans. on Computers, vol. C-33, No. 12, Dec. 1984, pp. 1247-1265. |
Hseih et al., "Third Generation Architecture Boosts Speed and Density of Field Programmable Gate Arrays," Proc. of IEEE CICC Conf., May 1990, pp. 31.2.1 to 31.2.7. |
Bursky, "Combination RAM/PLD Opens New Application Options," Electronic Design, May 23, 1991, pp. 138-140. |
Ling et al., "WASMII: A Data Driven Computer on a Virtual Hardware," Proc. of IEEE Field Prog. Custom Computing Machines Conf., Napa, California, Apr. 1993, pp. 33-42. |
Casselman, "Virtual Computing and The Virtual Computer," IEEE, Jul. 1993, p. 43. |
Quenot et al., "A Reconfigurable Compute Engine for Real-Time Vision Automata Prototyping," Proc. of IEEE FCCM Conf., Napa, California, Feb. 1994, pp. 91-100. |
Plus Logic "FPSL5110 Intelligent Data Buffer" Product Brief, Plus Logic, Inc., San Jose, California, Oct. 1990, pp. 1-6. |
Larsson, T, "Programmable Logic Circuits: The Luxury Alternatives are Coming Soon," Elteknik-med-Aktuell Electronik, No. 4, Feb. 25-Mar. 9, 1988, pp. 37-38, (with English abstract). |
Intel Preliminary Datasheet, "iFX780: 10ns FLEXlogic FPGA with SRAM Option," Nov. 1993, pp. 2-24 to 2-46. |
Quinnell, Richard A., "FPGA Family Offers Speed, Density, On-Chip RAM, and Wide-Decode Logic," EDN Dec. 6, 1990, pp. 62-63. |
Satoh, Hisayasu et al., "A 209K-Transistor ECL Gate Array with RAM," IEEE Jor. of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1275-1279. |
Xilinix, The Programmable Logic Data Book, 1993. |