Claims
- 1. A programmable logic device organized in a two-dimensional array comprising:
- a first plurality of conductors, each of said first plurality of conductors provided in a first dimension of said two dimensional array;
- a second plurality of conductors, each of said second plurality of conductors provided in a second dimension of said two dimensional array;
- a plurality of logic blocks devoted substantially to logic functions, each of said logic blocks programmably coupled to at least one of said first or second plurality of conductors; and
- a plurality of memory blocks devoted substantially to user memory, each of said memory blocks programmably coupled to at least one of said first or second plurality of conductors,
- wherein a selected number of said plurality of logic blocks are configured to provide a plurality of registers and multiplexers, each of said registers configured to receive a first data input and a first clock input and each of said multiplexers configured to receive a second data input, said multiplexers coupled to at least one of said plurality of memory blocks, said at least one memory block configured to receive a second clock input.
- 2. The programmable logic device of claim 1 wherein said multiplexers are configured to provide a selected memory block input to said at least one memory block from said first data input or said second data input, said selected memory block input stored in said at least one memory block by said second clock input.
- 3. The programmable logic device of claim 1 wherein said selected number of logic blocks are configured to provide an output register coupled to an output of said at least one memory block.
- 4. The programmable logic device of claim 1 wherein each of said memory blocks further comprises:
- a plurality of memory columns; and
- a control unit coupling said first plurality of conductors to said plurality of memory columns.
- 5. The programmable logic device of claim 4 wherein each of said memory blocks further comprises:
- a data input register coupled to said memory columns; and
- an address register coupled to said control unit.
- 6. The programmable logic device of claim 5 wherein each of said memory blocks further comprises a data output register coupled to said memory columns.
- 7. The programmable logic device of claim 6 wherein said data output register is programmably coupled to said second plurality of conductors.
- 8. The programmable logic device of claim 5 wherein said control unit further comprises:
- an address encoder coupled to said address register;
- an address control circuit having inputs coupled to said address encoder and to said plurality of first plurality of conductors; and
- an address decoder having inputs coupled to said address control circuit.
- 9. The programmable logic device of claim 5 wherein said control unit further comprises a read/write control circuit having a plurality of inputs and a plurality of outputs coupled to said memory columns.
- 10. The programmable logic device of claim 9 wherein said plurality of inputs to said read/write control circuit further comprise:
- a program mode signal from said address register;
- an address clock; and
- a write enable signal.
- 11. The programmable logic device of claim 6 wherein said control unit further comprises a clock/output enable generator having a plurality of inputs coupled to said first plurality of conductors and an output coupled to said data output register.
Parent Case Info
This patent application is a continuation of Ser. No. 08/655,870 filed May 24, 1996 now U.S. Pat. No. 5,668,771 which is a continuation of Ser. No. 08/245,509, filed Aug. 16, 1995 now U.S. Pat. No. 5,550,782, which is a continuation-in-part of Ser. No. 08/111,693, filed Aug. 25, 1993 now U.S. Pat. No. 5,436,575, which is a continuation-in-part of Ser. No. 07/754,017, filed Sep. 3, 1991 now U.S. Pat. No. 5,260,610, which is a continuation in part of Ser. No. 07/880,942, filed May 8, 1992 now U.S. Pat. No. 5,260,611.
US Referenced Citations (13)
Foreign Referenced Citations (1)
Number |
Date |
Country |
WO 9516993 |
Jun 1995 |
WOX |
Non-Patent Literature Citations (2)
Entry |
"Optimized reconfigurable cell array (ORCA) series field-programmable gate arrays," AT&T Microelectronics, pp. 1-87 (Advance Data Sheet, Feb. 1985). |
"The Programmable Logic Data Book," Xilnx, Inc., 1994, pp. 2-5-2-102. |
Continuations (2)
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655870 |
May 1996 |
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Parent |
245509 |
Aug 1995 |
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Continuation in Parts (3)
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111693 |
Aug 1993 |
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Parent |
754017 |
Sep 1991 |
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880942 |
May 1992 |
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