A. Scheibe et al., "A Two-Transistor SIMOS EAROM Cell", IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3, Jun. 1980, pp. 353-357. |
"An Introduction to Array Logic," H. Fleisher, L. I. Maissel, IBM Journal of Research and Development, Mar. 1975, pp. 98 et seq. |
"Array Logic Macros," J. W. Jones, IBM Journal of Research and Development, Mar. 1975, pp. 120 et seq. |
"PLAs Replace ROMs for Logic Designs," Electronic Designs 22, Oct. 15, 1973. |
"A High Speed ESFI SOS Programmable Logic Array with an MNOS Version," IEEE Journal of Solid State Circuits, vol. SC-10, No. 5, Oct. 1975, pp. 331-336. |
IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981, pp. 570-577, New York, U.S.; R. A. Wood et al.: "An Electrically Alterable PLA for Fast Turnaround-Time VLSI Development Hardware". |
Electronics, vol. 53, No. 5, Feb. 1980, pp. 113-117, New York, U.S.; W. S. Johnson et al.: "16-K EE-PROM Relies on Tunneling for Byte-Erasable Program Storage". |
IEEE Journal of Solid-State Circuits, vol. SC-19, No. 6, Dec. 1984, pp. 1041-1043, New York, U.S.; E. Fong et al.: "An Electrically Reconfigurable Programmable Logic Array Using A CMOS/DMOS Technology". |
IEEE International Solid-State Circuits Conference, vol. 28, 32nd Conference, Feb. 1985, pp. 130-131, 322-323, Coral Gables, Florida, U.S., R. Leung et al., "A 50ns 48-Term Erasable Programmable Logic Array". |
IEEE Journal of Solid-State Circuits, vol. SD-10, No. 5, Oct. 1975, pp. 331-336, New York, U.S.; K. Horninger, "A High-Speed ESFI SOS Programmable Logic Array with an MNOS Version". |
ONDE Electrique, vol. 63, No. 4, Apr. 1983, pp. 33-41, Paris, FR; P. Roux et al.; "Les Memoires Non Volatiles Electriquement Reprogrammables, Bilan et Perspectives". |
"Programmable Logic Array Decoding Technique," F. E. Howley, J. W. Jones, IBM Technical Disclosure Bulletin, vol. 17, No. 10, Mar. 1975. |
"Field-PLAs Simplify Logic Designs," Electronic Design, Sep. 1, 1975. |
"Programmable Logic Array," MOS/LSI Design and Application, W. Carr et al., pp. 255 et seq. |
"Altera EP 300 Erasable Programmable Logic Device," by Altera Corporation, Santa Clara, CA, 95051, Copyright.COPYRGT. 1984, pp. 1-12. |
"Automatic Page Write * * * Data Poling," vol. 1, No. 2, Jul. 23, 1983, by Reggie Huff. |
Monolithic Memories Advance Information Data Sheet for "PAL64R32 HAL64R32 High Density Programmable Array Logic Devices". |
Data Sheet entitled, "Product Specification Am27256 32,768.times.8-Bit Erasable PROM Advanced Micro Devices", Jul. 1983, pp. 1-6. |
Pp. 3-4, 3-10 and 3-19-3-22 Monolithic Memories, Inc., Product Data Book "20-Pin PAL/HAL". |
Characteristics and Operation of MOS Field Effect Devices, Richman, McGraw-Hill, Inc., 1967, pp. 114-118. |