Programmable signal processing device

Abstract

The device performs the function ##EQU1## for image processing, where W.sub.i are fixed weights for any specific application. It uses a PROM and accumulator algorithm, in which the memory stores the values ##EQU2## in 2.sup.M words, with addresses formed from one bit of each data word in a given bit position. In operation the most significant bit of each data word is used first to address memory, and in successive clock cycles the other bit positions are used down to the least significant. The memory output words are supplied to the adder-accumulator, and in each clock cycle the adder-accumulator output is shifted left one bit and used as a second input thereof. Then if the data words have N bits designated j=0 to N-1, after N clock cycles the memory output words have each been effectively multiplied by 2.sup.j and accumulated in the sum.

Description

BACKGROUND OF THE INVENTION

This invention relates to a programmable signal processing device using a read only memory and an accumulator with shifting to form a sum of products.

Rapid advances have been made during the past several years in large-scale integrated circuit (LSIC) technology. These advances have had a significant impact on many signal processing functions in such applications as forward looking infrared (FLIR) radar, guidance and control, and electronic counter measures (ECM) systems. In particular, image processing system studies for video bandwidth reduction, FLIR automatic cueing, 3-D target classification, and image understanding have consistently recommended using LSIC technologies to perform critical image processing functions. A general purpose algorithm (see W. K. Pratt, Digital Image Processing, Wiley-Interscience, New York, 1978) which uses the linear operation ##EQU3## on a single video line or on a square block of picture elements is a candidate to be implemented with LSIC technologies.

While such algorithms can be executed easily at low data rates using general purpose mini-computers or even commercial microprocessors, it is usually not possible to execute them in real time in an airborne environment because of excessive size, weight, power dissipation, and cost. The key to effective system design is to apply LSIC technology to minimize the overall component count and variety of components while absorbing as much as possible of the control and timing logic onto the information processing chips themselves. The solution is optimum when the same chips can be used for a multitude of other applications to provide a high volume market. These requirements have lead to the desire for a programmable chip architecture, and in turn, to the concept of a parallel/serial input bus.

A read-only memory (ROM)--accumulate algorithm has been discovered and applied to digital filter structures. This has been discussed in various places, including H. J. DeMan et al in a paper entitled "High Speed NMOS Circuits for ROM Accumulator and Multiplier-type Digital Filters," Proceedings ISSCC (San Francisco, Feb. 17, 1978) p 200, 1; and IEEE Journal Solid-State Circuits, Vol. SC-13 (October 1978), pp 565-572. see also C. S. Burrus, "Digital Filter Structures Described by Distributed Arithmetic," IEEE Transactions on Circuits and Systems, Vol. CAS-24 (December 1977), pp 674-680. The algorithm makes use of the fact that each multiplication involves a fixed coefficient or weighting factor and a variable data factor. The multiply operations are precalculated and stored in the ROM, for individual bit positions of the data.

SUMMARY OF THE INVENTION

The object of the invention is to provide a general purpose digital device which can be programmed to perform a variety of signal processing functions such as cosine and Hadamard transforms, edge extraction, unsharp masking, pole-zero filtering, and signal smoothing on data blocks at high data rates.

Another object is to provide such a device without excessive size, weight, power dissipation, or cost.

The device according to the invention comprises data input registers including parallel to serial registers, a programmable read-out memory, and accumulator-shift circuits arranged to calculate ##EQU4## in which the sum of products ##EQU5## are stored in the memory with 2.sup.M words. The memory addresses comprise M binary digits (bits), one from each data word in position j, starting with the most (or least) significant bit. The memory output is supplied to an adder, whose output is shifted left (or right) one position and supplied as a second input of the adder. The result is that after the memory is addressed for all j bit positions of the data words, the memory outputs for position j have been multiplied by 2.sup.j, for positions (j-1) by 2.sup.j-1, down to 2.sup.0 for the least significant position, and the sum has been accumulated.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block diagram of a programmable signal processing device; and

FIG. 2 is a diagram showing nine of the devices of FIG. 1 connected to receive the same input data, for matrix calculations.

DETAILED DESCRIPTION

The programmable signal processing device can perform any mathematical operation of the form: ##EQU6## where X.sub.i are data inputs, W.sub.i are weighting coefficients, and M is the number of data inputs. In a preferred embodiment the X.sub.i have 1 to 6 bits accuracy, the W.sub.i have 1 to 8 bits accuracy, and M varies from 1 to 9.

The operations are performed entirely in the digital mode with no restrictions on the values of the weighting coefficients. The device is configured for a specific application by programming of the memory and by the clocking, control and input-output connection logic. The programming makes use of a unique algorithm approach in which no multiplies are used whatsoever, with the result that the throughput is limited primarily by the add cycle time and the number of bits accuracy utilized for the input data (i.e., not by the number of terms M in the summation expression).

A block diagram of the preferred embodiment is shown in FIG. 1. This block diagram along with a discussion of the algorithm for programming the memory and operation of the device was supplied by applicants herein to a contractor (contract No. F33615-79-C-1763) who designed a large-scale integrated circuit chip to implement the block diagram. The final contract report AFWAL-TR-80-1209 dated November 1980, government accession No. AD-A100852, is attached hereto as an appendix, and is incorporated herein by reference. It is available from National Technical Information Service (NTIS).

The input section of FIG. 1 comprises nine sets of latches 11-19 for loading up to nine data words X.sub.1 to X.sub.9, and nine parallel-to-serial registers 21-29. In order to accommodate both word-serial and word-parallel data inputs (e.g., for an 8.times.1 transform as well as a 3.times.3 window operation), an addressing scheme is used which permits loading up to three words simultaneously using three separate input ports and their associated three separate input buses S, T and P. Alternatively, up to nine words can be loaded sequentially into the same input latches by tieing together the input pins from all three inputs to form a common input bus, and then applying the proper address sequence. The input buses S, T and P, the latches 11-19, the registers 21-29, and the lines between them, all provide conductors and devices for six bits in parallel. The latch control circuit 20 receives the data addresses on five leads K.sub.0 -K.sub.4 and supplies them to selected one of the nine leads connected individually to the latches 11-19. The parallel-to-serial registers 21-29 are static or dynamic components which can be implemented using either a parallel load/serially-clocked shift register approach, a multiplexer approach, or a variable length shift register approach. All parallel-to-serial registers are clocked in common and initiated at one time.

The memory 40 is a programmable read-only memory having 512 words of twelve bits each. The address is supplied from the parallel-to-serial registers 21-29. Each address comprises one bit of each data word, starting with the most significant bit.

The output from the memory is supplied on twelve leads 42 to a parallel adder/accumulator 44 (leads for bits 12-17 at the left are connected together at this input). A second input to the adder is supplied on a set of sixteen leads 48 from a shift left circuit 50, which provides a one-bit shift after each add operation. The output of the adder is supplied on seventeen leads 46 to an output latch 52, and on sixteen of these leads 46 to the shift left circuit. Timing and control circuits 30 supplies the required timing and control signals to the various units.

Once the memory has been properly programmed, the chip operation is effected by (1) loading the input data, (2) clocking the device for a fixed number of clock periods, and (3) hitting the output enable line 54 to obtain the desired output.

As an alternative embodiment, the memory addresses may be formed starting with the least significant bits of the data words, and the shift left circuit 50 replaced by a shift right circuit.

PRINCIPLES OF OPERATION AND PROGRAMMING

It is desired to calculate ##EQU7## where the weights W.sub.i are fixed and known a priori, and where the inputs X.sub.i are variable. In binary arithmetic one can represent the X.sub.i by ##EQU8## where the B.sub.ij are the binary values in each "digit" place, i.e.,

B.sub.ij .epsilon.{0,1} Substituting equation (2) into equation (1) gives ##EQU9## Some reflection on equation (4) will show that .delta.Y.sub.j has only 2.sup.M possible values. Therefore, since the W.sub.i are known, a priori, and since the B.sub.ij are either zero or one, it is possible to precompute the .delta.Y.sub.j in equation (4) for all possible combinations of B.sub.ij, store them in the memory, and then use the particular B.sub.ij from the incoming data to address the memory and obtain the .delta.Y.sub.j values which correspond to it. Once the particular values of .delta.Y.sub.j are obtained, equation (3) is used to compute the final value of Y. Equation (3) merely involves shifting the .delta.Y.sub.j 's by one bit position before adding to the previous sum.

The size of the memory required for this techique is 2.sup.M words, where M is the maximum number of terms in equation (1), i.e., the maximum number of input words to be filtered. The number of bits per word in the memory is given by

word length of .delta.Y.sub.j =word length of W.sub.i =log.sub.2 M.

To help clarify the above discussion, it is convenient to assume small size words and the number thereof. Let us assume M=4, i.e., (i=1 to 4), N=2, i.e., (j=0 to 2), and W.sub.i length of 4 bits. The expansion of equation (2) gives

X.sub.1 =4B.sub.12 +2B.sub.11 +B.sub.10 X.sub.2 =4B.sub.22 +2B.sub.21 +B.sub.20 X.sub.3 =4B.sub.32 +2B.sub.31 +B.sub.30 X.sub.4 =4B.sub.42 +2B.sub.31 +B.sub.30 Expansion of equation (4) gives .delta.Y.sub.0 =W.sub.4 B.sub.40 +W.sub.3 B.sub.30 +W.sub.2 B.sub.20 +W.sub.1 B.sub.10 .delta.Y.sub.1 =W.sub.4 B.sub.41 +W.sub.3 B.sub.31 +W.sub.2 B.sub.21 +W.sub.1 B.sub.11 .delta.Y.sub.2 =W.sub.4 B.sub.42 +W.sub.3 B.sub.32 +W.sub.2 B.sub.22 +W.sub.1 B.sub.12 and by equation (3) Y=4.delta.Y.sub.2 +2.delta.Y,+.delta.Y.sub.0 It is clear that the possible values of .delta.Y.sub.j is independent of the particular value of j, and that for M=4 there are sixteen different values to be stored in memory. The four bits of the memory address may be used in any order as long as the use is consistent and the appropriate value of W.sub.i is used with each bit for calculating the memory contents. Let's use the order B.sub.4 B.sub.3 B.sub.2 B.sub.1. Then the memory words have the values W.sub.4 B.sub.4 +W.sub.3 B.sub.3 +W.sub.2 B.sub.2 +W.sub.1 B.sub.1.

EXAMPLE 1

As a specific example, let W.sub.4 =5, W.sub.3 =30, W.sub.2 =17, W.sub.1 =2. Then the contents of the memory are as shown in Table A.

TABLE A______________________________________ ContentsAddress Decimal Binary______________________________________0000 0 000 00000001 2 000 00100010 17 001 00010011 19 001 00110100 30 001 11100101 32 010 00000110 47 010 11110111 49 011 00011000 5 000 01011001 7 000 01111010 22 000 11101011 24 001 10001100 35 010 00111101 37 010 01011110 52 011 01001111 54 011 0110______________________________________

To show the operation with one specific set of input data, assume

______________________________________Decimal Binary MSB on right______________________________________X.sub.4 6 110 011X.sub.3 5 101 101X.sub.2 1 001 100X.sub.1 4 100 001______________________________________ The most significant bits of the data words are used first in forming the memory addresses. In this example the addresses and contents are as follows: ______________________________________Bit position Address Contents______________________________________j.sup.2 1101 010 0101j.sup.1 1000 000 0101j.sup.0 0110 010 1111______________________________________ The outputs of the memory, the adder, and the shift left circuit are then as follows: ______________________________________Address______________________________________1101 shift 0000 0000 memory 010 0101 adder 0 0010 01011000 shift 0100 1010 memory 000 0101 adder 0 0100 11110110 shift 1001 1110 memory 010 1111 adder 0 1100 1101______________________________________ The last value from the adder is the output, which has a decimal value of 205. The decimal calculation using equation (1) is as follows: ______________________________________ W.sub.4 X.sub.4 = 5 .times. 6 = 30 W.sub.3 X.sub.3 = 30 .times. 5 = 150 W.sub.2 X.sub.2 = 17 .times. 1 = 17 W.sub.1 X.sub.1 = 2 .times. 4 = 8 Sum 205______________________________________

Thus, when the summation in equation (4) is performed to full precision, there is no truncation or roundoff in the final answer. I.e., the result is exact. However, the device of FIG. 1 may be operated with some truncation or roundoff if desired, for some applications.

Specific Embodiment

As a specific embodiment, assume a memory and registers with the sizes shown in FIG. 1. Also assume that the memory is to be programmed for a Hadamard transform. The inputs are supplied in the 3.times.3 format, with the center position blank as follows:

______________________________________ a b c h d g f e______________________________________ The weighting coefficients may be calculated with a simple FORTRAN program as follows: ______________________________________ ISCALE=2**10 WRITE (7,2)2 FORMAT(1X,37HINPUT A,B,C,D,E,F,G,H FORMAT 1X,F6.3) READ (5,3) A,B,C,D,E,F,G,H,3 FORMAT (8(1X,F6,3)) DO 100 IX="O, "377 YY=A*(IX.AND."1)+B*(IX.AND. "2)/2.+ C*(IX.AND."4)/4. YY=YY+D*(IX.AND. "10)/8.+E*(IX.AND. "20)/16. YY=YY+F*(IX.AND."40)/32. Y=YY+G*(IX.AND."100)/64.+H*(IX.AND. "200)/128. IY=IFIX(Y*ISCALE) WRITE (6,1)IX,IY,Y1 FORMAT(1X,03,5X,06,5X,F6.3)100 CONTINUE END *______________________________________

The scale factor of 2.sup.10 is used because the weight coefficients have fractional values in the form of a decimal point followed by three decimal digits, which requires ten binary digits. The scale factor permits the conversion to integer form. Assume that the assigned weights are

______________________________________W.sub.1 = .245 W.sub.4 = .049 W.sub.7 = -.208W.sub.2 = .208 W.sub.5 = -.049 W.sub.8 = -.245W.sub.3 = .139 W.sub.6 = -.139______________________________________ Then the memory content for a few of the 512 addresses is as shown in Table B. TABLE B______________________________________Address Contents______________________________________0000 0000 0000 0000 00000001 1100 1111 0111 00100001 1111 1111 0100 11001110 0000 0010 0101 11101111 1111 0001 1010 1001______________________________________

EXAMPLE 2

To show a sample calculation, assume data input as follows:

______________________________________ a b c 38 38 38 h d = 48 49 g f e 48 49 49______________________________________ This is loaded as follows: ______________________________________Data Input Registers 21-14 28, MSB on right______________________________________a 100110 011001b 100110 011001c 100110 011001d 110001 100011e 110001 100011f 110001 100011g 110000 000011h 110000 000011______________________________________

The outputs of the memory, the adder, and the shift left circuit are then shown below. Note that when the MSB (the sign bit) from memory is a 1, then all bits to the left thereof become 1's at the adder input.

______________________________________Address______________________________________1111 1111 Shift 0000 0000 0000 0000 memory 0001 1010 1001 adder 0 0000 0001 1010 10010001 1111 shift 0000 0011 0101 0010 memory 1111 0100 1100 adder 0 0000 0010 1001 11100000 0000 shift 0000 0101 0011 1100 memory 0000 0000 0000 adder 0 0000 0101 0011 11001110 0000 shift 0000 1010 0111 1000 memory 0010 0101 1110 adder 0 0000 1100 1101 01101110 0000 shift 0001 1001 1010 1100 memory 0010 0101 1110 adder 0 0001 1100 0000 10100001 1100 shift 0011 1000 0001 0100 memory 1111 0111 0010 adder 0 0011 0111 1000 0110______________________________________ The output is then divided by the scale factor of 2.sup.10. This is because the weights stored in memory were multiplied by 2.sup.10 to eliminate the factoring in both the memory and the adder accumulator. The result is 000 1101.1110 0001 10 which is 13.881 base 10.

The calculation using equation (1) in decimal form is ##EQU10## which is a % error=0.2 due to truncation of the weights in memory.

Matrix Operation

The device of FIG. 1 is ideally suited for matrix operations of the form. ##EQU11## Where Y represents the product of a row vector, W, and a column vector, X. Most signal-processing applications require the product of a weighting matrix and an input vector. This can be represented by

Y=WX (6) or, for the device as ##EQU12##

A diagram of the device configured to implement Equation (6) is shown in FIG. 2. Nine chip devices of FIG. 1 are used, with each programmed with the weighting coefficients of one row of W. This eliminates reprogramming, thus increasing the speed of the calculation. All the inputs are connected and data is entered sequentially. Nine sample periods are required to load the devices. The Y vector is calculated in parallel for the particular values of X. A valid output is available every sample period if operating on sliding 9-by-1 data while nine sample periods are required to produce an answer if the operation of Equation (6) is performed on nonsliding 9-by-1 data blocks.

Thus, while preferred constructional features of the invention are embodied in the structure illustrated herein, it is to be understood that changes and variations may be made by the skilled in the art without departing from the spirit and scope of my invention.

Claims

1. A signal processing system comprising a signal processing device for calculating ##EQU13## said device comprising: a read-only memory which is programmed to store the sum of products ##EQU14## in 2.sup.M words, where B.sub.i have binary values of 0 or 1 and W.sub.i are weighting coefficients for a given application, the memory addresses being the 2.sup.M different sets of B.sub.i for words of M bits;

input means comprising M.sub.m first registers, each of which provides storage for a word of N bits, input bus means having at least one input bus with parallel conductors for N bit positions coupled via input gate means to the first registers, input address means connected to control the input gate means to enter M words of data X.sub.i from the input bus means into corresponding input registers, M for a given application having a positive integer value equal to or less than M.sub.m, M.sub.m parallel-to-serial registers coupled via transfer gate means to the first registers, control means which includes means for controlling transfer of the data words from the first register via the transfer gate means to the parallel-to-serial registers;

memory address means for said memory coupled to the parallel-to-serial registers to form addresses with one bit from each parallel-to-serial register in a given bit position;

output means including an adder-accumulator and a shift circuit, the adder-accumulator having a first input from the output of said memory and a second input from the shift circuit, and a connection from the adder-accumulator output to the shift circuit input;

said control means including timing means for providing successive clock cycles; the device being operative, after the data words are loaded into the parallel-to-serial registers and the shift circuit is cleared, during each clock cycle to use an address from the memory address means and supply the memory word at that address to the first input of the adder-accumulator and add it to the word from the shift circuit, and then in the shift circuit to shift the resulting word from the adder-accumulator one bit, so that after N clock cycles each word output from memory has been effectively multiplied by 2.sup.j and accumulated in the sum.

2. The device as set forth in claim 1, wherein said ready-only memory is erasable and programmable, and said control means has changeable parameters, so that the device may be adapted for a specific application wherein the value of M and the weighting coefficients are fixed.

3. The device as set forth in claim 2, wherein M.sub.m equals nine, and said input bus means comprises three buses of N bit conductors each, the input address means being adapted to enter data words from all three buses at the same time, with up to three words in sequence on each bus, or alternatively to enter the M data words in sequence from one bus, depending on the specific application.

4. The device as set forth in claim 3, wherein the 512 memory words have twelve bits each to accommodate weighting coefficients of eight bits, and wherein the output means includes an output latch coupled to the output of the adder-accumulator.

5. The device as set forth in claim 4, wherein N equals 6, the shift circuit provides for words of 16 bits, and the output from the adder-accumulator to the output latch provides for words of 17 bits.

6. A signal processing system comprising a plurality of the devices as set forth in claim 1, 3, or 5, with the input bus means connected in common to supply the devices with the same data words, the devices being programmed with different weighting coefficients.

7. The device as set forth in claim 1, 2, 3 or 4, wherein said shift circuit is a shift left circuit, the memory address being formed first from the most significant bits with j=(N-1) of the data words, and then in successive clock cycles from the succeeding bits j=(N-2) etc bits until the least significant bits are reached with j=0.

8. The device as set forth in claim 1, 2, 3 or 4 wherein said device is incorporated on one large scale integrated circuit chip.

9. A signal processing system comprising a plurality of the devices as set forth in claim 8, with the input bus means connected in common to supply the devices with the same data words, the devices being programmed with different weighting coefficients.