Claims
- 1. A method for erasing a memory array, the method using erase pulses, the method comprising the step of:
adapting said erase pulses to the current state of said memory array.
- 2. A method according to claim 1 wherein said step of adapting includes the steps of:
determining erase conditions of the erase pulse used to erase a representative portion of said memory array; and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said representative portion.
- 3. A method according to claim 1 and wherein said step of adapting includes the steps of:
measuring the current threshold level of a bit to within a predetermined range; and selecting an incremental voltage level of a next erase pulse for said bit in accordance with said measured current threshold level.
- 4. A method according to claim 3 and wherein said step of measuring includes the step of having multiple verify levels for said array.
- 5. A method according to claim 3 and wherein said step of measuring also includes the step of after an erase pulse, comparing a threshold level of a group of bits which have received said erase pulse to at least one of said verify levels and said step of selecting includes the step of selecting a next erase pulse level according to generally the lowest verify level achieved by said group.
- 6. A method according to claim 5 and also comprising the steps of removing any bit which has been erased from said group and repeating said steps of comparing and selecting until there are no more bits in said group.
- 7. A method according to claim 3 and wherein said step of measuring also includes the step of after an erase pulse, comparing a threshold level of a bit which received said erase pulse to at least one of said verify levels and said step of setting includes the step of selecting a next erase pulse level according to generally the lowest verify level achieved by said bit.
- 8. A method according to claim 2 and wherein said erase conditions comprises at least one of the following set: the gate voltage level, the drain voltage level, the erase duration and any combination thereof.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a divisional application of U.S. Ser. No. 09/730,586, filed Dec. 7, 2000, which application is a continuation in part application of Ser. No. 09/563,923, filed May 4, 2000, which application is incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09730586 |
Dec 2000 |
US |
Child |
10155216 |
May 2002 |
US |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09563923 |
May 2000 |
US |
Child |
09730586 |
Dec 2000 |
US |