Programming of analog memory cells using a single programming pulse per state transition

Abstract

A method for data storage in analog memory cells includes defining multiple programming states for storing data in the analog memory cells. The programming states represent respective combinations of more than one bit and correspond to respective, different levels of a physical quantity stored in the memory cells. The data is stored in the memory cells by applying to the memory cells programming pulses that cause the levels of the physical quantity stored in the memory cells to transition between the programming states, such that a given transition is caused by only a single programming pulse.

Description

FIELD OF THE INVENTION

The present invention relates generally to memory devices, and particularly to methods and systems for programming analog memory cells.

BACKGROUND OF THE INVENTION

Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell holds a certain level of a given physical quantity such as an electrical charge or voltage, which represents the data stored in the cell. The levels of this physical quantity are also referred to as storage values or analog values. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to a programming state that represents one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.

Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.

Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.

Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24^th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.

Various methods and systems for programming memory cells are known in the art. For example, PCT International Publication WO 2008/083131, whose disclosure is incorporated herein by reference, describes a method for programming non-volatile storage elements. A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a second set of non-volatile storage elements.

PCT International Publication WO 2008/124760, whose disclosure is incorporated herein by reference, describes a predictive programming mode for programming an array of non-volatile memory cells, which are individually programmable to one of a range of threshold voltage levels. A predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In an embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. The checkpoint is an actual programming voltage that programs the memory cell in question to a verified designated threshold voltage level.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a method for data storage in analog memory cells, including:

defining multiple programming states for storing data in the analog memory cells, such that the programming states represent respective combinations of more than one bit and correspond to respective, different levels of a physical quantity stored in the memory cells; and

storing the data in the memory cells by applying to the memory cells programming pulses that cause the levels of the physical quantity stored in the memory cells to transition between the programming states, such that a given transition is caused by only a single programming pulse.

In some embodiments, the method includes measuring respective values of a property of the memory cells, and setting respective amplitudes of the programming pulses applied to the memory cells responsively to the measured values of the property. In a disclosed embodiment, setting the amplitudes includes setting a first amplitude of a first programming pulse for causing a transition between a given pair of the programming states in a first memory cell, and setting a second amplitude, different from the first amplitude, of a second programming pulse for causing the transition between the given pair of the programming states in a second memory cell, different from the first memory cell.

In an embodiment, the property includes a responsiveness of the memory cells to the programming pulses. Additionally or alternatively, the property may include a number of prior Programming and Erasure (P/E) cycles applied to the memory cells. Further additionally or alternatively, the property may include a temperature of the memory cells. In another embodiment, the memory cells are divided into multiple groups, and setting the amplitudes includes setting a respective common amplitude for the memory cells in each of the groups. In some embodiments, the method includes setting one or more reading parameters responsively to the measured values of the property, and reading the data from the memory cells using the reading parameters. The reading parameters may include respective positions of one or more read thresholds that are used for reading the data from the memory cells. In some embodiments, setting the amplitudes includes applying respective calibration pulses to the memory cells, sensing the respective levels of the physical quantity that are stored in the memory cells by the calibration pulses, and calculating the amplitudes based on the sensed levels of the physical quantity.

In an embodiment, the method includes retrieving the data from the memory cells by sensing the respective levels of the physical quantity so as to determine the programming states of the memory cells, and reconstructing the data based on the determined programming states. In a disclosed embodiment, storing the data includes encoding the data with an Error Correction Code (ECC), and reconstructing the data includes decoding the ECC. In another embodiment, reconstructing the data includes canceling interference that distorts the levels of the physical quantity of the memory cells. In yet another embodiment, retrieving the data includes determining the programming states by comparing the sensed levels of the physical quantity to one or more read thresholds, and adjusting respective positions of the read thresholds so as to successfully reconstruct the data.

There is additionally provided, in accordance with an embodiment of the present invention, a method for data storage in analog memory cells, including:

defining multiple programming states for storing data in the analog memory cells, such that the programming states represent respective combinations of more than one bit and correspond to respective, different levels of a physical quantity stored in the memory cells; and

storing the data in the memory cells by applying to the memory cells programming pulses that cause the levels of the physical quantity stored in the memory cells to transition between the programming states, such that a given transition is caused by one or more programming pulses that are applied without verifying the levels of the physical quantities caused by the programming pulses.

There is also provided, in accordance with an embodiment of the present invention, a data storage apparatus, including:

a plurality of analog memory cells, for which multiple programming states are defined, such that the programming states represent respective combinations of more than one bit and correspond to respective, different levels of a physical quantity stored in the memory cells; and

circuitry, which is coupled to the memory cells and is configured to store data in the memory cells by applying to the memory cells programming pulses that cause the levels of the physical quantity stored in the memory cells to transition between the programming states, such that a given transition is caused by only a single programming pulse.

The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;

FIG. 2 is a flow chart that schematically illustrates a method for programming analog memory cells, in accordance with an embodiment of the present invention;

FIG. 3 is a flow chart that schematically illustrates a method for programming and reading analog memory cells, in accordance with an embodiment of the present invention; and

FIG. 4 is a diagram that schematically illustrates a process for programming multi-level analog memory cells, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Overview

Analog memory cells typically hold certain levels of a physical quantity (e.g., electrical charge), which represent the data stored in the cells. Multiple programming states are typically defined, such that each programming state represents a certain stored data value and corresponds to a certain level of the physical quantity.

Analog memory cells are often programmed by applying programming pulses to the cells. The programming pulses change the levels of the physical quantity stored in the cells, and thus transition the cells from one programming state to another. In some cases, a programming operation transitions a given memory cell from an erased state to a non-erased state. In other cases, e.g., in a multi-level cell, the memory cell may already be programmed to a certain non-erased state, and the programming operation transitions the cell to another programming state.

Embodiments of the present invention that are described hereinbelow provide improved methods and systems for programming analog memory cells. The methods and systems described herein are particularly suitable for MLC devices, i.e., memory cells that store more than one bit per cell, but can be used with SLC devices, as well. The methods and systems described herein program the memory cells such that a given state transition is carried out by applying only a single programming pulse. Unlike some known programming methods that apply sequences of programming pulses and/or verify the cell values after programming, the methods and systems described herein apply the single programming pulses in open loop, without verification. As a result, high programming speed can be achieved.

In many practical cases, however, the responsiveness of memory cells to programming pulses may differ considerably from one cell or cell group to another. In such cases, applying programming pulses in open loop may cause the levels of the physical quantity stored in the cells to have a wide distribution, which increases the likelihood of read errors. Several methods for narrowing and controlling the mean values of these distributions, without compromising the speed of open-loop single-pulse programming, are described herein.

In some embodiments, the amplitudes of the programming pulses are adjusted prior to data storage based on various properties of the memory cells. When using such an adjustment process, the amplitudes of the programming pulses applied to a given memory cell or group of cells are matched to the properties of that memory cell or cell group. Thus, the physical quantity levels assumed by the cells in response to the programming operation have a relatively narrow distribution having a controlled mean value, even though the responsiveness of different cells or groups of cells to programming may vary considerably. Additionally or alternatively, techniques such as read threshold tracking and Error Correction Coding (ECC) may be used to achieve good error performance in the presence of the relatively wide distributions caused by open-loop programming.

System Description

FIG. 1 is a block diagram that schematically illustrates a memory system 20, in accordance with an embodiment of the present invention. System 20 can be used in various host systems and devices, such as in computing devices, cellular phones or other communication terminals, removable memory modules (“disk-on-key” devices), Solid State Disks (SSD), digital cameras, music and other media players and/or any other system or device in which data is stored and retrieved.

System 20 comprises a memory device 24, which stores data in a memory cell array 28. The memory cell array comprises multiple analog memory cells 32. In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog level of a physical quantity, such as an electrical voltage or charge. Array 28 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and CTF Flash cells, PCM, NROM, FRAM, MRAM and DRAM cells. Memory cells 32 may comprise Single-Level Cells (SLC) or Multi-Level Cells (MLC, also referred to as multi-bit cells).

The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values or storage values. Although the embodiments described herein mainly address threshold voltages, the methods and systems described herein may be used with any other suitable kind of storage values.

System 20 stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming states are selected from a finite set of possible states, and each state corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming states by writing one of four possible nominal storage values to the cell. The number of bits stored in each cell is not necessarily integer. In other words, the number of programming states may not necessarily be a power of 2. For example, three programming states can be defined per memory cell.

Memory device 24 comprises a reading/writing (R/W) unit 36, which converts data for storage in the memory device to storage values and writes them into memory cells 32. In alternative embodiments, the R/W unit does not perform the conversion, but is provided with voltage samples, i.e., with the storage values for storage in the cells. When reading data out of array 28, R/W unit 36 converts the storage values of memory cells 32 into digital samples having a resolution of one or more bits. The R/W unit typically reads data from cells 32 by comparing the storage values of the cells to one or more read thresholds. Data is typically written to and read from the memory cells in groups that are referred to as pages. In some embodiments, the R/W unit can erase a group of cells 32 by applying one or more negative erasure pulses to the cells.

The storage and retrieval of data in and out of memory device 24 is performed by a memory controller 40. In some embodiments, controller 40 produces the storage values for storing in the memory cells and provides these values to R/W unit 36. Alternatively, controller 40 may provide the data for storage, and the conversion to storage values is carried out by the R/W unit internally to the memory device.

Memory controller 40 communicates with a host 44, for accepting data for storage in the memory device and for outputting data retrieved from the memory device. In some embodiments, some or even all of the functions of controller 40 may be implemented in hardware. Alternatively, controller 40 may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements.

The configuration of FIG. 1 is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. Elements that are not necessary for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits and debugging circuits, have been omitted from the figure for clarity.

In the exemplary system configuration shown in FIG. 1, memory device 24 and memory controller 40 are implemented as two separate Integrated Circuits (ICs). In alternative embodiments, however, the memory device and the memory controller may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or System on Chip (SoC). Further alternatively, some or all of the circuitry of the memory controller may reside on the same die on which the memory array is disposed. Further alternatively, some or all of the functionality of controller 40 can be implemented in software and carried out by a processor or other element of the host system. In some implementations, a single memory controller may be connected to multiple memory devices 24. In yet another embodiment, some or all of the memory controller functionality may be carried out by a separate unit, referred to as a memory extension, which acts as a slave of memory device 24. Typically, controller 40 comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on tangible media, such as magnetic, optical, or electronic memory.

Memory cells 32 of array 28 are typically arranged in a grid having multiple rows and columns, commonly referred to as word lines and bit lines, respectively. The array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Cells are typically erased in groups of word lines that are referred to as erasure blocks. In some embodiments, a given memory devices comprises multiple memory cell arrays, which may be fabricated on separate dies.

Cell Responsiveness to Programming, and its Effect on Storage Reliability

R/W unit 36 programs memory cells 32 by applying programming pulses (e.g., voltage pulses) to the cells. For example, when cells 32 comprise floating-gate Flash cells, the R/W unit applies programming pulses to the gates of the cells. In a typical Flash device configuration, the gates of multiple cells are connected to a common word line, and the R/W unit is able to program multiple cells in parallel by applying programming pulses to the word line.

A given programming pulse causes a given memory cell to assume a given storage value, which corresponds to a certain level of a physical quantity. For example, in a Flash memory cell, a given programming pulse causes the memory cell to accumulate a given amount of electrical charge, so as to assume a given threshold voltage. The description that follows refers mainly to Flash cells whose charge levels (or threshold voltages) represent stored data. Alternatively, however, the methods and systems described herein can be used with various other sorts of analog memory cells that hold various other kinds of physical quantities and storage values.

Memory cells 32, or groups of cells 32, may differ from one another in their responsiveness to programming pulses. The term “responsiveness to programming” is used to describe the extent to which a given memory cell reacts to a given programming pulse in assuming its intended physical quantity level or storage value. When a programming pulse having a given amplitude is applied to multiple memory cells, some cells (referred to as low-responsiveness cells) may accumulate less charge and assume a lower threshold voltage, while other cells (referred to as high-responsiveness cells) may accumulate more charge and assume a higher threshold voltage. In other words, responsiveness to programming is a relative measure, which compares the physical quantities or storage values assumed by different cells or groups of cells in response to a certain programming pulse or pulses.

The difference in responsiveness to programming pulses among different cells is one of the factors that cause the storage values of the cells to vary from their intended target levels after programming. The storage values in a group of N-level memory cells will typically be distributed around the N nominal storage values that represent the N programming states. FIG. 4 below shows an example of storage value distributions in a group of four-level memory cells.

The variance of the storage value distributions, and the separation between the distributions, have a considerable detrimental effect on the storage reliability of the memory cells, i.e., on the probability of read errors. As noted above, reading data from the memory cells is typically performed by comparing their storage values to one or more read thresholds, attempting to associate the read storage values to the programming states correctly. When the distributions are wide and/or closely-spaced, the likelihood of storage values to fall on the wrong side of a read threshold increases. This effect is particularly severe in multi-level memory cells, in which the separation between adjacent programming states is relatively small.

Programming Memory Cells Using a Single Programming Pulse Per State Transition

For a given memory cell, a given programming operation can be viewed as a transition from one programming state of the cell to another. Consider, for example, a four-level cell in which four programming states denoted L1 . . . L4 are represented by four respective nominal threshold voltages. Such a cell can store two data bits. In the present example, memory states L1 . . . L4 represent the bit combinations “11”, “10”, “00” and “01”, respectively. State L1 also represents an erased state (i.e., when a block of cells is erased, the cells in the block are set to state L1, which is often represented by a negative threshold voltage). In this example, programming an erased cell to store “01” data can be viewed as a transition from state L1 to state L4. When a cell is already at state L3 (i.e., holds the data “00”, the cell can be programmed to store “01” using a transition from state L3 to state L4.

Embodiments of the present invention provide improved methods and systems for programming analog memory cells. The methods and systems described herein carry out a given state transition by applying only a single programming pulse. As a result, programming operations applied to the memory cells are extremely fast and enable high programming speed. In some embodiments, the amplitude of the programming pulse applied to a given cell is pre-calculated based on certain properties of the cell, so as to control the mean value and reduce the variance of the resulting storage value distributions.

FIG. 2 is a flow chart that schematically illustrates a method for programming memory cells 32, in accordance with an embodiment of the present invention. The method begins with system 20 performing a calibration process that measures certain properties of cells 32, e.g., the responsiveness of the cells to programming, at a calibration step 50. The results of the calibration process are used for calculating the appropriate amplitudes of the programming pulses applied to the memory cells in subsequent programming operations.

In an example calibration process, controller 40 applies calibration pulses having known amplitudes to cells or groups of cells. The memory controller then reads the storage values assumed by the cells in response to the calibration pulses. Using the read results, the memory controller assesses the responsiveness of each cell or group of cells to programming. The calibration results may be stored in memory controller 40 or in memory device 24 for later use.

The calibration process may be performed at any desired stage during the lifetime of device 24, such as during production, during power-up or initialization of the memory device in a host system, or even during normal operation of the memory device in the host system (e.g., during idle periods in which memory access operations are not performed).

The memory controller may assess the responsiveness to programming of individual cells, or collectively for groups of cells, e.g., word lines. In an example embodiment, the memory controller may hold a nominal pulse amplitude that is to be applied to a certain word line in order to cause a certain state transition. Based on the calibration results, the memory controller may compute an offset from the nominal pulse amplitude for each word line. The offset corresponding to a given word line can be used to scale the programming pulses applied to this word line.

When intending to store data in memory cells 32, memory controller 40 calculates the appropriate amplitudes of the programming pulses to be applied to the memory cells based on the calibration results, at an amplitude calculation step 54. The memory controller programs the cells by applying the programming pulses, at a programming step 58. Each cell is programmed by applying a single programming pulse. In other words, each transition between programming states in a given cell is performed by applying a single programming pulse.

When programming the cells, the memory controller sets the amplitudes of the programming pulses to the values calculated at step 54 above. Since the amplitude of each programming pulse is matched to the properties of the cell in which the pulse is applied, the distribution of storage values assumed by the cells is relatively narrow. As a result, the likelihood of subsequent read errors is reduced.

In the description above, the amplitudes of programming pulses are adjusted based on the estimated programming responsiveness of the cells. Additionally or alternatively, system 20 may calculate the pulse amplitudes based on any other suitable property of cells 32, such as, for example, the number of Programming and Erasure (P/E) cycles the cells have gone through, or the temperature of the memory device. Since the programming responsiveness of the cells may vary with the number of P/E cycles, the calibration process described above may be repeated periodically in order to account for these changes. When the memory device employs wear leveling techniques that distribute P/E cycles evenly among different cell groups, periodic calibration may be performed for the entire memory device. When different cell groups differ from one another considerably in the number of P/E cycles, each cell group can be calibrated at suitable time intervals, as appropriate.

Further additionally or alternatively, the dependence of the calibration results (e.g., offsets to programming pulse amplitudes) on the number of P/E cycles can be studied and modeled a-priori, and then compensated for during operation without a need for periodic calibration. This a-priori modeled dependence can also be used as side information that assists or complements the periodic calibration process.

Improved Reading of Cells that were Programmed Using a Single Pulse Per State Transition

In some embodiments, system 20 employs certain techniques for enhancing the performance of reading data from memory cells 32, in conjunction with the single-pulse programming schemes described above. These reading techniques may either replace the pre-programming calibration processes described above, or complement such calibration processes. In either case, such reading techniques are able to reliably reconstruct the stored data even though the storage value distributions in cells 32 may have relatively high variances. Moreover, reading techniques are sometimes used to compensate for cross-coupling interference from neighboring cells, which may be present in the storage values of cells 32.

For example, memory controller 40 may encode the stored data using an Error Correction Code (ECC), such as a Low-Density Parity Check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code or any other suitable ECC. Additionally or alternatively, the memory controller may employ methods for canceling cross-coupling interference and other distortion in the storage values of the memory cells. Further additionally or alternatively, the memory controller may apply methods that adaptively track and adjust the values of the read thresholds used for reading the data from the memory cells.

In some embodiments, the memory controller may use a separate set of reading parameters (e.g., read thresholds) for each group of cells (e.g., for each word line, block or memory cell array). In some embodiments, the reading parameters (e.g., values of read thresholds) can be set based on the calibration results described above.

Techniques for adaptively adjusting read threshold values are described, for example, in PCT International Publications WO 2008/053472 and WO 2008/111058, whose disclosures are incorporated herein by reference. Techniques for estimating and cancelling distortion in memory cells are described, for example, in PCT International Publications WO 2007/132452, WO 2007/132453, WO 2007/132457 and WO 2008/026203, whose disclosures are incorporated herein by reference. ECC techniques for use in analog memory cells are described, for example, in PCT International Publication WO 2007/132457, cited above.

FIG. 3 is a flow chart that schematically illustrates a method for programming and reading analog memory cells 32, in accordance with an embodiment of the present invention. The method begins with memory controller 40 programming memory cells 32 using a single programming pulse per state transition, at a single-pulse programming step 60. The memory controller adjusts the reading parameters for each cell group (e.g., word line, block or array), at a reading adjustment step 64. The memory controller then reads the data from a given cell group using its respective set of reading parameters, at a reading step 68.

In the description of FIGS. 2 and 3 above, the different calibration, calculation and parameter setting operations are performed by memory controller 40. This configuration, however, is chosen purely by way of example, and the methods and systems described herein are in no way limited to this sort of configuration. In alternative embodiments, any of the functions described above can be performed by R/W unit 36. The different functions can be divided between the memory controller and the R/W unit in any suitable way. The memory controller and the R/W unit are regarded herein as processing circuitry, which is coupled to the memory cells and is configured to carry out the methods described herein.

FIG. 4 is a diagram that demonstrates a process for programming a group of four-level cells using a single pulse per state transition, in accordance with an embodiment of the present invention. In the present example, each memory cell in the group has four programming states denoted E, L1, L2 and L3. State E also functions as the erased state. When the cells are programmed using a single pulse per state transition, the storage values associated with states E, L1, L2 and L3 are distributed in accordance with distributions 80A . . . 80D, respectively. The group of cells stores two memory pages, such that the two bits of each cell belong to the two pages.

When programming is initiated, all cells are assumed to be erased, i.e., in state E. Programming of the first page is shown in the top half of the figure. The first page is programmed by applying a single pulse (denoted PULSE1 in the figure) to the cells in which the first bit is “0”. After this programming operation, the cells in which the first bit is “0” are transitioned to state L2, while the cells in which the first bit is “1” remain in state E.

The second bit is programmed as follows: For cells that are in state E and in which the second bit is “0”, a single pulse denoted PULSE2 is applied, causing these cells to transition to state L1. For cells that are in state E and in which the second bit is “1”, no pulse is applied and these cells remain in state E. For cells that are in state L2 and in which the second bit is “1”, a single pulse denoted PULSE3 is applied, causing these cells to transition to state L3. For cells that are in state L2 and in which the second bit is “0”, no pulse is applied and these cells remain in state L2. Thus, the group of four-level cells is programmed to store two memory pages by selectively applying three programming pulses, such that each state transition is carried out using only a single programming pulse.

In the present example, the nominal storage values of states L1, L2 and L3 are 1V, 2V and 3V, respectively. The amplitudes of pulses PULSE1, PULSE2 and PULSE3 are set, using the calibration methods described above, to 17V, 16V and 18V, respectively. The three pulses are assumed to have the same time duration. In alternative embodiments, any other suitable values can also be used. Note that the programming order shown in FIG. 4, i.e., the order in which the different programming pulses are applied, is chosen by way of example. Various other programming orders, which use a single pulse per state transition, can also be used.

It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

Claims

1. A method for data storage in analog memory cells, comprising: defining multiple programming states for storing data in the analog memory cells, such that the programming states represent respective combinations of more than one bit and correspond to respective, different levels of a physical quantity stored in the memory cells; andstoring the data in the memory cells by applying to the memory cells programming pulses that cause the levels of the physical quantity stored in the memory cells to transition between the programming states, such that a given transition is caused by only a single programming pulse, without verifying the levels of the physical quantities caused by the programming pulses.

2. The method according to claim 1, and comprising measuring respective values of a property of the memory cells, and setting respective amplitudes of the programming pulses applied to the memory cells responsively to the measured values of the property.

3. The method according to claim 2, wherein setting the amplitudes comprises setting a first amplitude of a first programming pulse for causing a transition between a given pair of the programming states in a first memory cell, and setting a second amplitude, different from the first amplitude, of a second programming pulse for causing the transition between the given pair of the programming states in a second memory cell, different from the first memory cell.

4. The method according to claim 2, wherein the property comprises a responsiveness of the memory cells to the programming pulses.

5. The method according to claim 2, wherein the property comprises a number of prior Programming and Erasure (P/E) cycles applied to the memory cells.

6. The method according to claim 2, wherein the property comprises a temperature of the memory cells.

7. The method according to claim 2, wherein the memory cells are divided into multiple groups, and wherein setting the amplitudes comprises setting a respective common amplitude for the memory cells in each of the groups.

8. The method according to claim 2, and comprising setting one or more reading parameters responsively to the measured values of the property, and reading the data from the memory cells using the reading parameters.

9. The method according to claim 8, wherein the reading parameters comprise respective positions of one or more read thresholds that are used for reading the data from the memory cells.

10. The method according to claim 2, wherein setting the amplitudes comprises applying respective calibration pulses to the memory cells, sensing the respective levels of the physical quantity that are stored in the memory cells by the calibration pulses, and calculating the amplitudes based on the sensed levels of the physical quantity.

11. The method according to claim 1, and comprising retrieving the data from the memory cells by sensing the respective levels of the physical quantity so as to determine the programming states of the memory cells, and reconstructing the data based on the determined programming states.

12. The method according to claim 11, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), and wherein reconstructing the data comprises decoding the ECC.

13. The method according to claim 11, wherein reconstructing the data comprises canceling interference that distorts the levels of the physical quantity of the memory cells.

14. The method according to claim 11, wherein retrieving the data comprises determining the programming states by comparing the sensed levels of the physical quantity to one or more read thresholds, and adjusting respective positions of the read thresholds so as to successfully reconstruct the data.

15. A data storage apparatus, comprising: a plurality of analog memory cells, for which multiple programming states are defined, such that the programming states represent respective combinations of more than one bit and correspond to respective, different levels of a physical quantity stored in the memory cells; andcircuitry, which is coupled to the memory cells and is configured to store data in the memory cells by applying to the memory cells programming pulses that cause the levels of the physical quantity stored in the memory cells to transition between the programming states, such that a given transition is caused by only a single programming pulse, without verifying the levels of the physical quantities caused by the programming pulses.

16. The apparatus according to claim 15, wherein the circuitry is configured to measure respective values of a property of the memory cells, and to set respective amplitudes of the programming pulses applied to the memory cells responsively to the measured values of the property.

17. The apparatus according to claim 16, wherein the circuitry is configured to set a first amplitude of a first programming pulse for causing a transition between a given pair of the programming states in a first memory cell, and to set a second amplitude, different from the first amplitude, of a second programming pulse for causing the transition between the given pair of the programming states in a second memory cell, different from the first memory cell.

18. The apparatus according to claim 16, wherein the property comprises a responsiveness of the memory cells to the programming pulses.

19. The apparatus according to claim 16, wherein the property comprises a number of prior Programming and Erasure (P/E) cycles applied to the memory cells.

20. The apparatus according to claim 16, wherein the property comprises a temperature of the memory cells.

21. The apparatus according to claim 16, wherein the memory cells are divided into multiple groups, and wherein the circuitry is configured to set a respective common amplitude for the memory cells in each of the groups.

22. The apparatus according to claim 16, wherein the circuitry is configured to set one or more reading parameters responsively to the measured values of the property, and to read the data from the memory cells using the reading parameters.

23. The apparatus according to claim 21, wherein the reading parameters comprise respective positions of one or more read thresholds that are used for reading the data from the memory cells.

24. The apparatus according to claim 16, wherein the circuitry is configured to apply respective calibration pulses to the memory cells, to sense the respective levels of the physical quantity that are stored in the memory cells by the calibration pulses, and to calculate the amplitudes based on the sensed levels of the physical quantity.

25. The apparatus according to claim 15, wherein the circuitry is configured to retrieve the data from the memory cells by sensing the respective levels of the physical quantity so as to determine the programming states of the memory cells, and reconstructing the data based on the determined programming states.

26. The apparatus according to claim 25, wherein the circuitry is configured to encode the data with an Error Correction Code (ECC), and to reconstruct the data by decoding the ECC.

27. The apparatus according to claim 25, wherein the circuitry is configured to reconstruct the data by canceling interference that distorts the levels of the physical quantity of the memory cells.

28. The apparatus according to claim 25, wherein the circuitry is configured to determine the programming states by comparing the sensed levels of the physical quantity to one or more read thresholds, and to adjust respective positions of the read thresholds so as to successfully reconstruct the data.