All of the material in this patent application is subject to copyright protection under the copyright laws of the United States and of other countries. As of the first effective filing date of the present application, this material is protected as unpublished material.
However, permission to copy this material is hereby granted to the extent that the copyright owner has no objection to the facsimile reproduction by anyone of the patent documentation or patent disclosure, as it appears in the United States Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
Not Applicable
Not Applicable
The present invention relates generally to providing a transient voltage surge suppressor protection mechanism for RUN and/or START capacitors that are used with AC motors in order to improve the overall performance and reliability of these capacitors and prevent AC motor damage caused by failure of these capacitors in the field.
As generally depicted in
As generally depicted. in
The RUN capacitor used as described in
An extension of the configurations depicted
RUN capacitors may take a variety of physical forms, but are generally have a cylindrical diameter of from 1.5-3.0 inches and a cylinder length of from 2.0-6.0 inches for cylindrically formed enclosures and stadium-formed capacitors typically have a thickness from 1.0-3.0 inches, a width of 1.5-4.0 inches, and a length of 2.0-6.0 inches. Typical RUN capacitors have a capacitance in the range of 1 microfarad to 100 microfarads and a working voltage of 270 VAC or 440 VAC. In all of these configurations, the conventional connection mechanism for these capacitors takes the form of a 0.25-inch wide male spade lug, although in some circumstances direct wiring to the capacitor is available.
The electrical connections to these capacitors are insulated from the capacitor enclosure which is normally constructed of 0.062-inch or thinner metal (typically aluminum or steel). Electrical insulators in this common configuration are sealed to the top cap of the metal enclosure as the enclosure itself is filled with dielectric oil that insulates the internal capacitor plates, isolates these conductors from the metal capacitor enclosure, and provides for heat transfer from the internal capacitor components to the metal capacitor enclosure as an aid in dissipating internal capacitor losses that are manifested as heat within the internal capacitor structure.
The focus of be present invention is protection of the RUN capacitor (0119, 0219). This capacitor sources current continuously to the START/AUX winding (0113, 0213) and as such is subject to a variety of transient voltage spikes caused by the quality of the AC power input (0101, 0201) and/or make/break electrical connections caused by mechanical operation of the power switch/contactor (0102, 0202). While the RUN capacitor (0119, 0219) typically has a working voltage of 370-440 VAC in operating environments where the AC power input (0101, 0201) is 240-330 VAC, this overvoltage margin has proven to be insufficient to prevent transient overvoltaaes from occurring across the RUN capacitor (0119, 0219) which generate partial discharges within the capacitor dielectric and eventually cause the capacitor to lose effective capacitance, incur excessive internal series resistance, and/or fail due to a puncture shorting of the capacitor plates through the insulating dielectric of the capacitor.
Field reliability studies have shown that the RUN capacitor (0119, 0219) has a high probability of failure in any electric motor (0110, 0210) system, and this failure probability is especially high in harsh environment applications that are normally associated with HVAC air conditioner/heat pump compressor motors and the like. The additional parasitic lead inductance (0117, 0118, 0217, 0218) caused by wiring that connects the RUN capacitor (0119, 0219) to the electric motor (0110, 0210) can also cause voltage ringing in the RUN capacitor (0119, 0219) (in conjunction with the parasitic inductors (0117, 0217) and (0118, 0218) associated with wiring of the RUN capacitor (0119, 0219) to the remaining components in the electric motor system) that can induce overvoltages in the RUN capacitor (0119, 0219) leading to device failure. The environmental temperature extremes in which the RUN capacitor (0119) operates and external system mechanical vibration can cause internal mechanical movement in the capacitor also causing overvoltage transients to degrade the capacitor operation. Internal series resistance losses in the RUN capacitor (0119, 0219) can also cause similar temperature-related overvoltage failure mechanisms to occur.
In a typical application context the RUN capacitor is purchased from a number of manufacturers and it is difficult to predict the mean time between failure (MTBF) for a given capacitor purchased and installed on an electric motor system. However, field studies have indicated that in general the quality of RUN capacitors has deteriorated in recent years due in part to quality control issues with foreign manufacturing plants. As a result the incidents of RUN capacitor replacement have increased over time as domestic manufacturers have become a smaller part of the capacitor supplier market. For this reason the overall maintenance cost of many electric motor systems has increased over time due to the increased number of service calls due to capacitor failure. This increased capacitor failure rate has also resulted in increased electric motor damage and a resulting higher overall maintenance cost for electric motor systems employing RUN and/or START capacitors.
Since the sources for RUN capacitors are limited, any solution to overcoming the MTBF problem with current RUN capacitors must address scenarios in which existing RUN capacitors with poor reliability/manufacturing processes can be protected from premature failure in the field.
Accordingly, the objectives of the present invention are (among others) to circumvent the deficiencies in the prior art and affect the following objectives:
(1) Provide for protected capacitor system and method that reduces voltage transients across RUN and/or START capacitors used in conjunction with an AC motor.
(2) Provide for a protected capacitor system and method that can be retrofit to existing RUN and/or START capacitors used in conjunction with an AC motor.
(3) Provide for a protected capacitor system and method that can be integrated within RUN and/or START capacitors used in conjunction with an AC motor.
(4) Provide for a protected capacitor system and method that provides for improved reliability over existing RUN and/or START capacitors used in conjunction with an AC motor.
While these objectives should not be understood to limit the teachings of the present invention, in general these objectives are achieved in part or in whole by the disclosed invention that is discussed in the following sections. One skilled in the art will, no doubt be able to select aspects of the present invention as disclosed to affect any combination of the objectives described above.
The present invention overcomes the disadvantages of currently available RUN/START capacitor systems by shunting the capacitor with a series combination of one or more surge suppression devices (SSDs) proximally located and in parallel with the capacitor structure to produce an overall protected capacitor structure having enhanced reliability and simultaneous ability to resist transient overvoltage conditions.
The SSDs are formed from series combinations of transient voltage surge suppressors (TVSs) (metal oxide varistor (MOV), diode for alternating current (DIAC), and/or silicon diode for alternating current (SIDAC)) and corresponding shunt diode rectifiers (SDRs) and placed in parallel across the capacitor structure to locally suppress voltage transients across the capacitor structure in excess the voltage rating of the capacitor structure.
The parallel shunting TVS/SDR pairs may be integrated into a printed circuit board (PCB) assembly that is externally attached to the capacitor structure or encapsulated in an enclosure incorporating the capacitor structure. The parallel shunting TVS/SDR pairs may be integrated into unified structures in some situations to improve space efficiency and economic performance of the overall transient protection system.
The present invention system may be utilized in the context of an overall protected capacitor method, wherein the TVS/SDR pair is incorporated within the context of a printed circuit board (PCB) that mechanically connects to the electrical contacts of an existing capacitor structure to provide proximal transient voltage protection for the capacitor. In these situations an existing capacitor may be retrofit to incorporate improved transient protection is the use of a piggy-back. PCB that provides for mating to electrical contacts of an existing capacitor structure on one side of the PCB and provides replacement contacts mimicking the original capacitor on the other side of the PCB. In these circumstances wiring from the original capacitor can be removed, the piggy-beck PCB in on the capacitor, and the original wiring connected to the piggy-back PCB to complete the performance reliability upgrade to the existing capacitor.
For a fuller understanding of the advantages provided by the invention, reference should be made to the following detailed description together with the accompanying drawings wherein:
While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detailed preferred embodiment of the invention with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the broad aspect of the invention to the embodiment illustrated.
The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment, wherein these innovative teachings are advantageously applied to the particular problems of a PROTECTED CAPACITOR SYSTEM AND METHOD. However, it should be understood that this embodiment is only one example of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
The present invention a wide variety of exterior surface profiles that may be used with the capacitor structures described herein. Specifically, and without limitation, the present invention anticipates that the exterior surface profiles of the capacitor enclosures described herein may be of cylindrical-form (in which the capacitor enclosure forms a cylindrical tube with one closed end and is used to contain an internal capacitor structure having solid cylindrical form) or of stadium-form (in which the capacitor enclosure forms a geometric shape constructed of a rectangle with semicircles at a pair of opposite sides and is used to contain an internal capacitor structure having either a solid cylindrical form or a solid stadium form). The geometric stadium form is also alternatively referred to as a discorectangle form and obround form in the literature.
The present invention anticipates a wide variety of shunt diode rectifiers (SDRs) may be used to implement the present invention. In many preferred embodiments, this SDR structure comprises a semiconductor P-N junction diode and/or a Schottky diode rectifier.
The present invention anticipates that a wide variety of Transient Voltage Surge Suppressor (TVS) technologies may be used to implement various embodiments of the present invention and makes no limitation on the particular type of TVSS that may be used to construct various invention embodiments.
In many preferred invention embodiments the TVS structure may comprise a metal oxide varistor (MOV), a diode for alternating current (DIAC), a silicon diode for alternating current (SIDAC), and/or combinations of these devices.
The present invention may be best understood by inspection of the system overview depicted in
Details of typical implementations of the diode-MOV (DMV) (1320) structure are generally depicted in
The present invention may in some preferred contexts be implemented as a retrofit design in which an existing non-polarized capacitor is augmented with a DMV protective structure as generally depicted in
The present invention may in some preferred contexts be implemented as an integrated protected capacitor design in which non-polarized capacitor structure is augmented internally with a DMV protective structure as generally depicted in
Any of the DMV structures detailed herein may be in some preferred invention embodiments be implemented using integrated two-terminal and/or three-terminal diode+MOV structures as detailed in U.S. Pat. Nos. 9,634,474; 9,093,832; and 9,093,831 which are herein incorporated by reference.
As generally depicted in
It should be noted that in this and other retrofit applications the PCB (1710) may be directly mated to the capacitor (1720) such that first and second PCB male input terminals (1715, 1716) are electrically connected to first and second PCB female output terminals (2025, 2026) that mate directly to corresponding spade lug terminals (2135, 2136) on the capacitor (1720). This allows field-retrofit operations in which an existing stadium-form capacitor (1720) may be retrofit with the PCB (1710) to form protected capacitor system.
As generally depicted in
It should be noted that in this and other retrofit applications the PCB (2510) may be directly mated to the capacitor (2520) such that first, second, and third PCB male input terminals (2517, 2518, 2519) (corresponding to the COMMON (COM), FAN MOTOR (FAN), and HERMETICALLY SEALED COMPRESSOR (HERM) capacitor connections) are electrically connected to first and second PCB female output terminals (2827, 2828, 2829) that mate directly to corresponding spade lug terminals (2937, 2938, 2939) on the capacitor (2520). This allows field-retrofit operations in which an existing cylindrical-form capacitor (2520) may be retrofit with the PCB (2510) to form a protected capacitor system.
The teachings of the present invention may be applied to an integrated capacitor structure as well as retrofit applications. As generally depicted in
Assembly detail for this preferred exemplary embodiment is generally depicted in
While the integrated protective PCB assembly (4024) depicted in
While the integrated protective PCB assembly (4024) depicted in
While the integrated protective PCB assembly (4024) depicted in
While the integrated protective PCB assembly (4024) depicted in
Additional detail of an exemplary capacitor cover structure including insulators and terminal connectors is provided in
Additional detail of exemplary capacitor top and bottom cup insulators used within the integrated protected capacitor system are provided in
The present invention retrofit application method may be seen in an overview context as generally illustrated in the flowchart of
(1) configuring a printed circuit board (PCB) to contain a transient voltage surge suppressor (TVS) and semiconductor P-N diode (PND) electrically series coupled between a first input connector (FIC)/first output connector (FOC) and a second input connector (SIC)/second output connector (SOC) on the PCB (6301);
(2) electrically and mechanically coupling a first capacitor connection (FTC) of a non-polarized capacitor (NPC) to a first output connector (FOC) of the PCB (6302);
(3) electrically and mechanically coupling a second capacitor connection (STC) of the non-polarized capacitor (NPC) to a second output connector (SOC) of the PCB (6303);
(4) electrically coupling the first input connector (SIC) of the printed circuit board (PCB) to a source of electrical power (6304); and
(5) electrically coupling the second input connector (SIC) of the printed circuit board (PCB) to an electrical load device (6305).
One skilled in the art will recognize that these method steps may be augmented or rearranged without limiting the teachings of the present invention.
The present invention integrated capacitor application method may be seen in an overview context as generally illustrated in the flowchart of
(1) placing a non-polarized capacitor (NPC) and printed circuit board (PCB) comprising a transient voltage surge suppressor (TVS) and semiconductor P-N diode (PND) within a capacitor enclosure (CPE) shell comprising an open cavity end (OCE) and an open cavity void (OCV) (6401);
(2) electrically coupling a first terminal connection (FTC) of the capacitor cover (CPC) to a first input connector (FIC) of the PCB (6402);
(3) electrically coupling a second terminal connection (STC) of the capacitor cover (CPC) to a second input connector (SIC) of the PCB (6403);
(4) covering the open cavity end (OCE) of the capacitor enclosure (CPE) with a capacitor cover (CPC) and sealing the capacitor cover (CPC) to the capacitor enclosure (CPE) (6404);
(5) configuring the capacitor cover (CPC) to electrically couple a first terminal connection (FTC) of the capacitor cover (CPC) to a source of electrical power (6405); and
(6) configuring the capacitor cover (CPC) to electrically couple a second terminal connection (STC) of the capacitor cover (CPC) to an electrical load device (6406).
One skilled in the art will recognize that these method steps may be augmented or rearranged without limiting the teachings of the present invention.
The present invention preferred exemplary system embodiment, can be generalized as protected capacitor retrofit system comprising:
(a) non-polarized capacitor (NPC);
(b) printed circuit board (PCB);
(c) transient voltage surge suppressor (TVS); and
(d) semiconductor P-N diode (PND);
wherein:
the NPC comprises a capacitor enclosure (CPE) and a capacitor cover (CPC);
the NPC comprises a first capacitor connection (FTC) and a second capacitor connection (STC);
the TVS comprises a first TVS connection (FVC) and a second TVS connection (SVC);
the PND comprises a first PND connection (FPC) and a second PND connection (SPC);
the SVC is electrically coupled to the FPC via metal traces on the PCB;
the TVS and the PND form a surge suppression device (SSD) having a first SSD terminal (FDC) electrically coupled to the FVC and a second SSD terminal (SDC) electrically coupled to the SPC;
the PCB comprises a first input connector (FIC), a second input connector (SIC), a first output connector (FOC), and a second output connector (SOC);
the PCB comprises metal traces configured to electrically couple the FIC, the FOC, and the FDC;
the PCB comprises metal traces configured to electrically couple the SIC, the SOC, and the SDC;
the FTC is electrically coupled to the FOC; and
the STC is electrically coupled to the SOC.
This general system summary may be augmented by the various elements described herein to produce a wide variety of invention embodiments consistent with this overall design description.
The present invention preferred exemplary method embodiment can be generalized as protected capacitor retrofit method wherein the method utilizes a protected capacitor system comprising:
(a) non-polarized capacitor (NPC);
(b) printed circuit board (PCB);
(c) transient voltage surge suppressor (TVS); and
(d) semiconductor PN diode (PND);
wherein:
the NPC comprises a capacitor enclosure (CPE) and a capacitor cover (CPC);
the NPC comprises a first capacitor connection (FTC) and a second capacitor connection (STC);
the TVS compress a first TVS connection (FVC) and a second TVS connection (SVC);
the PND comprises a first PND connection (FPC) and a second PND connection (SPC);
the SVC is electrically coupled to the FPC via metal traces on the PCB;
the TVS and the PND form a surge suppression device (SSD) having a first SSD terminal (FDC) electrically coupled to the FVC and a second SSD terminal (SDC) electrically coupled to the SPC;
the PCB comprises a first input connector (FIC), a second input connector (SIC), a first output connector (FOC), and a second output connector (SOC);
the PCB comprises metal traces configured to electrically couple the FIC, the FOC, and the FDC;
the PCB comprises metal races configured to electrically couple the SIC, the SOC, and the SDC;
the FTC is electrically coupled to the FOC; and
the STC is electrically coupled to the SOC;
with the method comprising the steps of:
(1) configuring the PCB to mechanically couple the FOC to the FTC;
(2) configuring the PCB to mechanically couple the SOC to the STC;
(3) configuring the PCB to electrically couple the FIC to a source of electrical power; and
(4) configuring the PCB to electrically couple the SIC to an electrical load device.
One skilled in the art will recognize that these method steps may be augmented or rearranged without limiting the teachings of the present invention.
An alternate present invention preferred exemplary system embodiment can be generalized as an integrated protected capacitor system comprising:
(a) capacitor enclosure (CPE);
(b) capacitor cover (CPC);
(c) non-polarized capacitor (NPC);
(d) printed circuit board (PCB);
(e) transient voltage surge suppressor (TVS); and
(f) semiconductor P-N diode (PND);
wherein:
the CPE is configured as a shell having an open cavity end (OCE) and an open cavity void (OCV) configured to contain the NPC and the PCB;
the CPC is configured to cover and seal the OCE;
the NPC and the PCB are contained within the OCV;
the CPC comprises a first terminal connection (FTC) and a second terminal connection (STC);
the FTC and the STC are insulated from the CPC and extend through an outer surface of the CPC;
the NPC comprises a first capacitor connection (FCC) and a second capacitor connection (SCC);
the TVS comprises a first TVS connection (FVC) and a second TVS connection (SVC);
the PND comprises a first PND connection (FPC) and a second PND connection (SPC);
the SVC is electrical coupled to the FPC via metal traces on the PCB;
the TVS and the PND form a surge suppression device (SSD) having a first SSD terminal (FDC) electrically coupled to the FVC and a second SSD terminal (SDC) electrically coupled to the SPC;
the PCB comprises a first input connection (FIC), second input connection (SIC), a first output connection (FOC), and a second output connection (SOC);
the PCB comprises metal traces configured to electrically couple the FTC, the FIC, the FOC, and the FDC;
the PCB comprises metal traces configured to electrically couple the STC, the SIC, the SOC, and the SDC;
the FCC is electrically coupled to the FOC; and
the SCC is electrically coupled to the SOC.
This general system summary may be augmented by the various elements described herein to produce a wide variety of invention embodiments consistent with this overall design description.
An alternate present invention preferred exemplary method embodiment can be generalized as an integrated protected capacitor method wherein the method utilizes a protected capacitor system comprising:
(a) capacitor enclosure (CPE);
(b) capacitor cover (CPC);
(c) non-polarized capacitor (NPC);
(d) printed circuit board (PCB);
(e) transient voltage surge suppressor (TVS); and
(f) semiconductor P-N diode (PND);
wherein:
the CPE is configured as a shell having an open cavity end (OCE) and an open cavity void (OCV) configured to contain the NPC and the PCB;
the CPC is configured to cover and seal the OCE;
the NPC and the PCB are contained within the OCV;
the CPC comprises a first terminal connection (FTC) and a second terminal connection (STC);
the FTC and the STC are insulated from the CPC and extend through an outer surface of the CPC;
the NFC comprises a first capacitor connection (FCC) and a second capacitor connection (SCC);
the TVS comprises a first TVS connection (FVC) and a second TVS connection (SVC);
the PND comprises a first PND connection (FPC) and a second PND connection (SPC);
the SVC is electrically coupled to the FPC via metal traces on the PCB;
the TVS and the PND form a surge suppression device (SSD) having first SSD terminal (FDC) electrically coupled to the FVC and a second SSD terminal (SDC) electrically coupled to the SPC;
the PCB comprises a first input connection (FIC), a second input connection (SIC), a first output connection (FOC), and a second output connection (SOC);
the PCB comprises metal traces configured to electrically couple the FTC, the FIC, the FOC, and the FDC;
the PCB comprises metal traces configured to electrically couple the STC, the SIC, the SOC, and the SDC;
the FCC is electrically coupled to the FOC; and
the SCC is electrically coupled to the SOC;
with the method comprising the steps of:
(1) placing the NPC, the PCB, and the SSD within the CPE;
(2) covering the OCE of the CPE with the CPC and sealing the CPC to the CPE;
(3) configuring the CPC to electrically couple the FTC to a source of electrical power; and
(4) configuring the CPC to electrically couple the STC to an electrical load device.
One skilled in the art will recognize that these method steps may be augmented or rearranged without limiting the teachings of the present invention.
It will be evident to those skilled in the art that there has been described herein an improved method and apparatus for connecting to, and supplying power for, a device or appliance that is protected by certain surge suppression circuits. Although the invention hereof has been described by way of preferred embodiments, it is evident that other adaptations and modifications can be employed without departing from the spirit and scope thereof.
The present invention anticipates a wide variety of variations in the basic theme of construction. The examples presented previously do not represent the entire scope of possible usages. They are meant to cite a few of the almost limitless possibilities. The basic system and method described above may be augmented with a variety of ancillary embodiments, including but not limited to:
An embodiment wherein where NPC has a capacitance in the range of 1 microfarad to 100 microfarads.
An embodiment wherein the TVS is selected from a group consisting of: metal oxide varistor (MOV); diode for alternating current (DIAC); and silicon diode for alternating current (SIDAC).
One skilled in the art will recognize that other embodiments are possible based on combinations of elements taught within the above invention description.
A protected capacitor system/method implementing enhanced transient over-voltage suppression has been disclosed. The system/method incorporates one or more surge suppression devices (SSDs) proximally located and in parallel with a capacitor structure to produce an overall protected capacitor structure having enhanced reliability and simultaneous ability to resist transient overvoltage conditions. The SSDs are formed from series combinations or transient voltage surge suppressors (TVSs) (metal oxide varistor (MOV), diode for alternating current (DIAC), and/or silicon diode for alternating current (SIDAC)) and corresponding shunt diode rectifiers (SDRs) and placed in parallel across a capacitor structure to locally suppress voltage transients across the capacitor structure in excess of the voltage rating of the capacitor structure. The parallel shunting TVS/SDR pairs may be integrated into a printed circuit board (PCB) assembly that is externally attached to the capacitor structure or encapsulated an enclosure incorporating the capacitor structure.
The following rules apply when interpreting the CLAIMS of the present invention:
“ADAPTED FOR” clauses should be considered as limiting the scope of the claimed invention.
Although a preferred embodiment of the present invention has been illustrated in the accompanying drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications, and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.
This is a Continuation-In-Part patent application (CIP) of U.S. Utility patent application for ELECTRICAL WIRING SYSTEM AND METHOD by inventor Mark E. Goodson, filed electronically with the USPTO on Jul. 1, 2015, with Ser. No. 14/789,270, EFS ID 22802725, confirmation number 7696, docket AXITH.0101CIP1-C, issued as U.S. Pat. No. 9,634,474 on Apr. 25, 2016. This application claims benefit under 35 U.S.C. §120 and incorporates by reference U.S. Utility patent application for ELECTRICAL WIRING SYSTEM AND METHOD by inventor Mark E. Goodson, filed electronically with the USPTO on Jul. 1, 2015, with Ser. No. 14/789,270, EFS ID 22802725, confirmation number 7696, docket AXITH.0101CIP1-C, issued as U.S. Pat. No. 9,634,474 on Apr. 25, 2016. U.S. Utility patent application for ELECTRICAL WIRING SYSTEM AND METHOD by inventor Mark E. Goodson, filed electronically with the USPTO on Jul. 1, 2015, with Ser. No. 14/789,270, EFS ID 22802725, confirmation number 7696, docket AXITH.0101CIP1-C, issued as U.S. Pat. No. 9,634,474 on Apr. 25, 2016 claims benefit under 35 U.S.C. §120 and incorporates by reference U.S. Utility patent application for ELECTRICAL WIRING SYSTEM AND METHOD by inventor Mark E. Goodson, filed electronically with the USPTO on Feb. 11, 2015, with Ser. No. 14/619,619, EFS ID 21468808, confirmation number 6788, docket AXITH.0101CIP1, issued as U.S. Pat. No. 9,093,831 on Jul. 28, 2015. U.S. Utility patent application for ELECTRICAL WIRING SYSTEM AND METHOD by inventor Mark E. Goodson, filed electronically with the USPTO on Feb. 11, 2015, with Ser. No. 14/619,619, EFS ID 21468808, confirmation number 5788, docket AXITH.0101CIP1, issued as U.S. Pat. No. 9,093,831 on Jul. 28, 2015 claims benefit under 35 U.S.C. §120 and incorporates by reference U.S. Utility patent application for ELECTRICAL WIRING SYSTEM AND METHOD by inventor Mark S. Goodson, filed electronically with the USPTO on Feb. 11, 2015, with Ser. No. 14/619,755, EFS ID 21470782, confirmation number 1057, docket AXITH.0101CIP2, issued as U.S. Pat. No. 9,093,832 on Jul. 28, 2015. U.S. Utility patent application for ELECTRICAL WIRING SYSTEM AND METHOD by inventor Mark E. Goodson, filed electronically with the USPTO on Feb. 11, 2015, with Ser. No. 14/619,755, EFS ID 21470782, confirmation number 1057, docket AXITH.0101CIP2, issued as U.S. Pat. No. 9,093,832 on Jul. 28, 2015 claims benefit under 35 U.S.C. §120 and incorporates by reference U.S. Utility patent application for ELECTRICAL WIRING SYSTEM by inventor Mark E. Goodson, filed electronically with the USPTO on Apr. 25, 2012, with Ser. No. 13/455,686, EFS ID 12628238, confirmation number 5731, docket AXITH.0101, now abandoned.
Number | Date | Country | |
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Parent | 14619619 | Feb 2015 | US |
Child | 14789270 | US |
Number | Date | Country | |
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Parent | 14789270 | Jul 2015 | US |
Child | 15495763 | US | |
Parent | 14619755 | Feb 2015 | US |
Child | 14619619 | US | |
Parent | 13455686 | Apr 2012 | US |
Child | 14619755 | US |