Patent Application
20070091524
The present application relates to semiconductor chips and protection circuitry built into the chips. More particularly, the present application relates to circuits and methods for protecting semiconductor chips from electrostatic discharge (ESD).
It is well known that static electricity can be produced in every day situations. Static electricity is created when electrons are transferred from one object to another, thereby negatively charging one object while positively charging the other. An electrostatic potential, either positive or negative, can be carried on the skin of a person, for example, and discharged to an object having a different electrostatic potential. When an electric field between oppositely charged objects breaks down, an electrostatic discharge (ESD), or “shock”, can occur. An ESD event is characterized by a high voltage, but the current and charge are relatively low.
As an example, when a person walks across a carpet, a voltage on the order of about 10 kilovolts (kV) can be produced. Although a discharge of such a voltage may cause only mild discomfort for the person, such a discharge can destroy semiconductor chips and other computer components, which are extremely sensitive to ESD. In fact, a discharge of a voltage as low as 10 volts, far too small to even be felt by a person, can damage semiconductor chips. For this reason, circuitry for protecting chips from destructive ESD pulses is typically designed into chips. This built-in ESD protection circuitry is intended to provide protection during the physical handling of the chip before it is actually installed on a circuit board or integrated into a larger electronic system.
If the chip 10 were to experience an ESD pulse, the voltage discharge will usually occur at the pads 14, including the power terminal pad(s) and ground terminal pad(s) of the chip 10. For this reason, the I/O circuits 16 will experience the ESD pulse first and will typically be the weakest link in the ESD equation.
Therefore, the I/O circuits 16 may also be designed with ESD protection circuitry, in addition to the output drivers, for protecting the chip 10 and especially the output drivers. Furthermore, an output driver and ESD protection circuit can be combined in the I/O circuit 16 in such a way as to save area on the chip, which can be beneficial for reducing the chip size.
The output driver 18 includes a PMOS transistor 22 and an NMOS transistor 24. The PMOS transistor 22 receives at its gate a gate control signal PG from the functional circuitry 12, and the NMOS transistor 24 receives a gate control signal NG at its gate. Typically, the PG and NG signals are the same. During normal operation of the output driver 18, a low input at PG and NG turns on the PMOS transistor 22 to connect the respective pad 14 to VDD and turns off the NMOS transistor 24. A high input at PG and NG turns off the PMOS transistor 22 and turns on the NMOS transistor 24 to connect the pad 14 to VSS, or ground. Therefore, this output driver 18 acts as a CMOS inverter in that a high input to PG and NG produces a low output at the pad 14 and a low input to PG and NG produces a high output at the pad 14.
ESD protection circuits may be configured using any number of conventional ESD protection schemes. The ESD protection circuit 20 shown in
As is known in the art, each CMOS transistor inherently contains a small parasitic diode. The combination of the plurality of PMOS transistors 26 of the ESD protection circuit 20 possesses a large PMOS parasitic diode 30 that shunts current in a forward-bias direction from the pad 14 to VDD. Also, the combination of the plurality of NMOS transistors 28 possesses a large NMOS parasitic diode 32 that shunts current in a forward-bias direction from VSS to the pad 14. The parasitic diodes 30 and 32 can also shunt the current in a reverse-bias direction when a breakdown voltage is reached. The PMOS parasitic diode 30 and the NMOS parasitic diode 32 are capable of dissipating the charge to protect the chip from damage caused by the ESD event. The ESD protection circuit 20 and output driver 18 may include PMOS and NMOS transistors and drain diodes that are doped such that the effective breakdown voltage is adjusted to be lower than that of the transistors and diodes residing in functional circuitry 12. When a chip is manufactured with ESD protection circuitry, the chip can be tested using methods that attempt to model real-world ESD events. For example, one test includes applying a 2 kV pulse to different terminals of the chip to check whether or not the ESD protection circuit is able to dissipate the charge. The 2 kV pulse may be applied in at least four ways: from a pad to VDD, from VDD to a pad, from a pad to VSS, and from VSS to a pad. If the chip is able to manage these four pulses, then it is considered to have acceptable ESD protection.
However, even though prior art ESD protection circuits may pass these tests and operate well in most situations, it is possible that such ESD protection circuits may still fail under certain conditions that cannot be easily repeatable. It has been proposed that one possible reason for failure may be that an ESD event may actually cause a chip to be “powered up” by the discharge. This can be caused, for example, when an ESD pulse from the pad 14 to VSS is applied causing a current to be supplied through the PMOS parasitic diode 30 to VDD, powering up the chip. If by happenstance the NG signal at the gate of the NMOS transistor 24 of the output driver 18 is high and drives transistor 24 to a conductive state when the chip is powered up, a large current may be delivered to the relatively small area of the transistor 24, causing the output driver 18 to be destroyed. This occurs because the conducting transistor 24 has a lower impedance than the other parallel devices residing in the ESD protection circuit 20. There is therefore a need in the art to provide a circuit that can provide improved ESD protection, even when an ESD event powers up the chip.
The present application describes circuits and methods for protecting semiconductor chips from damage caused by electrostatic discharge. In general, one method for protecting a circuit from an ESD event comprises sensing when a chip is powering up, such as by the presence of an ESD event, and disabling an output driver of a circuit to be protected in response to the chip powering up.
One embodiment, for example, of a circuit for protecting a semiconductor chip from an electrostatic discharge (ESD) event comprises an ESD sensing circuit and a disabling circuit. The sensing circuit, for instance, includes an RC circuit, a first inverter and a second inverter. The RC circuit includes a resistor and a capacitor connected in series between VDD and VSS. The first inverter is connected between the second inverter and a node that connects the resistor with the capacitor. The output of the second inverter provides an enable signal EN and the output of the first inverter provides a signal
The disable circuit, for instance, is configured to receive the EN and
The first PMOS transistor is further configured to connect a second PMOS transistor to VDD when EN is low, and the first NMOS transistor is further configured to connect a second NMOS transistor to VSS when
Many aspects of the embodiments of the present disclosure can be better understood with reference to the following drawings. Like reference numerals designate corresponding parts throughout the several views.
The present application describes circuits and methods for protecting a semiconductor chip, or other computer components, from the damage caused by transients and electrostatic discharge (ESD) events. Since the prior art ESD protection circuits are able to function properly in most cases, the conventional circuitry of the prior art can be used without requiring a complete redesign.
However, since the prior art does not protect a chip in all possible situations, an additional protection circuit is added to overcome the deficiencies of the conventional circuits. The present application describes an ESD protection circuit that senses an ESD event and disables the transistors of an output driver when the ESD event is sensed. With the transistors of the output driver turned off, destructive currents will be blocked from flowing through them. The ESD currents can safely be channeled through the diodes 30 and 32 operating in either a forward-biased or reverse-breakdown mode. Therefore, even if an ESD event powers up the semiconductor chip and a random signal state attempts to turn on the transistors of the output driver, the embodiments described in the present application are capable of protecting the chip from the ESD event.
The values of the resistor 38 and capacitor 40 of the RC circuit 36 are selected to provide a timing characteristic such that, during the duration of the ESD pulse, the output of the RC circuit 36 at node 42 will not be able to rise to a destructive voltage and also does not rise high enough to switch the inverter 44. For example, the resistor 38 and capacitor 40 may be selected to provide a time constant of about 1 μsec or more, which can sufficiently accommodate an ESD pulse, which typically has a duration on the order of about ten nanoseconds. In this regard, the resistor 38 may have a value of 1 Mohm and the capacitor 40 may have a value of 1 pF.
The operation of the RC circuit 34 will now be described, given the initial condition, for instance, that the chip is not installed and all nodes and terminals are substantially neutral. Immediately before the chip experiences an ESD event, the terminals of the chip will be floating at substantially a ground potential. If an ESD pulse or other transient powers up the VDD terminal, the RC circuit 36 provides a voltage at the output node 42 that builds up gradually based on the time constant of the RC circuit 36. Since the voltage across the capacitor 40 can not be changed instantaneously, the initial voltage across the capacitor 40 will remain at about zero volts, or VSS. The large voltage difference across the resistor 38 causes a current to flow from VDD to the node 42. This gradually charges up one of the plates of the capacitor 40 to create an increasing voltage at node 42 until it eventually approaches VDD and the voltage across the resistor 38 becomes zero. The duration of a typical ESD pulse is typically much smaller, e.g. about ten nanoseconds, than the charging time of the capacitor 40. When the device is powering up, the RC circuit 36 has a time constant that sets the time it takes the chip to power up. For 1 μsec, for example, the output will be turned off. Since an ESD event has a much shorter duration than that, the outputs will be off during an ESD pulse and the current will flow through the breakdown mechanism as designed.
Before the ESD pulse is imposed upon the chip and the terminals of the chip are neutral, the output of the RC circuit 36 will be low. When an ESD pulse powers up the chip, the inverters will also be powered up. With the initial low output at node 42, the output of the first inverter 44 will provide a high
Immediately after the chip experiences an ESD pulse, the EN signal will be low and the
During normal operation, when the chip is first powered up by a normal power source, the output driver 18 will initially be disabled. As the RC circuit 36 approaches a steady state after a short power up sequence, e.g. about 1 μsec, a voltage at node 42 reaches the threshold voltage causing the inversion of the EN and
It should be recognized that the disable circuit 48 may be considered to be a three-state device. In a first state, while the device is powering up from an ESD pulse or a normal power source, both the PMOS transistor 22 and NMOS transistor 24 will be turned off, allowing the pad to float. During normal operation, the functional circuitry of the chip can provide a second state by turning the PMOS transistor 22 on and turning the NMOS transistor 24 off. The pad is switched high at this time. The third state occurs when the functional circuitry turns the PMOS transistor 22 off and turns the NMOS transistor 24 on.
The pad is switched low at this time.
In the embodiment shown in
Alternatively, the disabling circuit 48 may be configured with both the NMOS 52 and the PMOS 54 omitted. In this configuration, the PG and NG inputs are separated from each other during normal operation. Thus, the PG and NG will be isolated from each other during the power up phase when VDD is applied to the PMOS transistor 22 and VSS is applied to the NMOS transistor 24. Functional circuitry of the chip can be designed with this alternative embodiment to switch the PG and NG inputs individually. Before inverting the PG and NG inputs, the functional circuitry may momentarily turn both transistors off before switching one on. In this respect, a low impedance path from VDD to VSS will not be created, which would waste energy.
It should be emphasized that the above-described embodiments are merely examples of possible implementations. Many variations and modifications may be made to the above-described embodiments without departing from the principles of the present disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.
