Patent Application
20240347529
The present disclosure relates to a protection circuit and a semiconductor device.
Patent Literature 1 discloses a radio frequency integrated circuit with an electrostatic protection element. The electrostatic protection element electrically couples a depletion-type field-effect transistor and an enhancement-type field-effect transistor in series to each other, and further electrically couples a capacitor to the enhancement-type field-effect transistor in parallel. The field-effect transistors each include a MESFET, a gate junction type FET, a HEMT, or the like.
In the electrostatic protection element, when a noise or a high-voltage pulse is inputted from outside, the enhancement-type field-effect transistor performs a breakdown operation and an impedance thereof is lowered to allow for discharging of the noise or the high-voltage pulse.
Further, Patent Literature 2 discloses a surge protection element and a semiconductor device. The surge protection element includes a pnp bipolar transistor. The bipolar transistor is configured with a p-type GaN layer as a collector region, an AlGaN layer and a Gan layer as a base region, and a p-type Gan layer as an emitter region. In the surge protection element, a surge is absorbed as a puchthrough current.
Furthermore, Patent Literature 3 discloses a semiconductor integrated circuit including an electrostatic breakdown protection circuit. The electrostatic breakdown protection circuit includes a diode-coupled transistor. A bipolar transistor or a MOSFET is used as the transistor.
Patent Literature 1: Japanese Patent No. 4843927
Patent Literature 2: International Publication No. WO2014/103126A1
Patent Literature 3: Japanese Patent No. 4803747
A radio frequency power amplifier operating in a millimeter wave band has been developed for next-generation mobile terminals. An insulated gate field-effect transistor including a GAN-based wide band gap material is used to construct the radio frequency power amplifier. Specifically, a metal-insulator-semiconductor field-effect transistor (Metal Insulator Semiconductor Field Effect Transistor; hereinafter simply referred to as a “MISFET”) is used.
The electrostatic protection element disclosed in Patent Literature 1 described above, the surge protection element disclosed in Patent Literature 2, and the electrostatic breakdown protection circuit disclosed in Patent Literature 3 each use a p-type layer. In a GaN-based process, p-type impurities are very low in activation rate, which makes it difficult to produce p-type GaN and makes its process affinity (mass productivity) in a manufacturing process poor. In other words, it is difficult to implement a protection element using p-type GaN. Accordingly, a protection circuit and a semiconductor device that are superior in electrostatic discharge (Electro Static Discharge: hereinafter simply referred to as “ESD”) robustness or avalanche (Avalanche) robustness are desired.
The present technology provides a protection circuit and a semiconductor device that are superior in ESD robustness or avalanche robustness.
A protection circuit according to a first embodiment of the present disclosure includes a first insulated gate field-effect transistor in which: a first main electrode is coupled between an external terminal and an internal circuit; a second main electrode and a gate electrode are coupled to a reference power supply: and an electric charge accumulation section configured to accumulate hot carriers is provided in a gate insulating film.
A semiconductor device according to a second embodiment of the present disclosure includes an external terminal provided on a substrate, an internal circuit provided on the substrate and coupled to the external terminal, and a protection circuit provided on the substrate and including a fist insulated gate field-effect transistor in which: a first main electrode is coupled between the external terminal and the internal circuit; a second main electrode and a gate electrode are coupled to a reference power supply: and an electric charge accumulation section configured to accumulate hot carriers is provided in a gate insulating film.
Some embodiments of the present disclosure are described in detail below with reference to the drawings. It is to be noted that description is given in the following order.
A first embodiment describes a first example in which the present technology is applied to a radio frequency (Radio Frequency: hereinafter simply referred to as “RF”) power amplifier module equipped with a semiconductor device incorporating a protection circuit and an internal circuit. Here, a description is given of a configuration of the RF power amplifier module, a layout of the semiconductor device, a circuit block configuration, a vertical cross-sectional structure, a plan structure, and a manufacturing method of the protection circuit and the internal circuit, and a method of adjusting a threshold voltage of the protection circuit.
A second embodiment describes a second example in which the configuration of the protection circuit is changed in the semiconductor device according to the first embodiment.
A third embodiment describes a third example in which the configuration of the protection circuit is changed in the semiconductor device according to the first embodiment.
A fourth embodiment describes a fourth example in which the configuration of the protection circuit is changed in the semiconductor device according to the first embodiment.
A fifth embodiment describes a fifth example in which the semiconductor device according to the third embodiment and the semiconductor device according to the fourth embodiment are combined.
A sixth embodiment describes a sixth example in which the configuration of the protection circuit is changed in the semiconductor device according to the fourth embodiment.
A seventh embodiment describes a seventh example in which the semiconductor device according to the fifth embodiment and the semiconductor device according to the sixth embodiment are combined.
An eighth embodiment describes an eighth example in which the configuration of the protection circuit is changed in the semiconductor device according to the sixth embodiment.
A ninth embodiment describes a ninth example in which the semiconductor device according to the seventh embodiment and the semiconductor device according to the eighth embodiment are combined.
A tenth embodiment describes a tenth example in which the configuration of the protection circuit is changed in the semiconductor device according to the eighth embodiment.
An eleventh embodiment describes an eleventh example in which the semiconductor device according to the ninth embodiment and the semiconductor device according to the tenth embodiment are combined.
A twelfth embodiment describes a twelfth example in which the configuration of the protection circuit is changed in the semiconductor device according to the first embodiment.
A description will be given of a protection circuit 22, a protection circuit 23, and a semiconductor device 2 according to the first embodiment of the present disclosure with reference to
Here, an arrow-X direction illustrated as appropriate in the drawings indicates one planar direction of the semiconductor device 2 placed on a plane for convenience An arrow-Y direction indicates another planar direction orthogonal to the arrow-X direction. Further, an arrow-Z direction indicates an upward direction orthogonal to the arrow-X direction and the arrow-Y direction. That is, the arrow-X direction, the arrow-Y direction, and the arrow-Z direction exactly coincide with an X-axis direction, a Y-axis direction, and a Z-axis direction, respectively, of a three-dimensional coordinate system.
It is to be noted that these directions are each illustrated to aid understanding of descriptions, and are not intended to limit directions used in the present technology.
The substrate 10 is formed as a module substrate. The substrate 10 is formed in a rectangular shape, for example, as viewed in the arrow-Z direction (hereinafter simply referred to as “in a plan view”).
Here, the input section matching circuit 3 is mounted on a left side on top of the substrate 10. The input section matching circuit 3 is to receive an RF signal from outside the RF power amplifier module 1.
The semiconductor device 2 is mounted on a middle of the substrate 10. The semiconductor device 2 includes the protection circuit 22, an internal circuit 24, and the protection circuit 23.
The protection circuit 22 is configured as an input-side protection circuit. The protection circuit 22 is coupled to each of the input section matching circuit 3 and the internal circuit 24.
In the first embodiment, the internal circuit 24 includes an RF power amplifier. For example, the internal circuit 24 includes an RF power amplifier that operates in a millimeter wave band for a fifth or subsequent generation mobile terminal.
The protection circuit 23 is configured as an output-side protection circuit. The protection circuit 23 is coupled to each of the internal circuit 24 and the output section matching circuit 4. It is to be noted that the protection circuit 23 has a configuration similar to the configuration of the protection circuit 22, and the description thereof will thus be omitted hereinafter.
The output section matching circuit 4 is mounted on a right side below the substrate 10. The output section matching circuit 4 outputs an RF signal to outside the RF power amplifier module 1.
The DC bias circuit 5 is mounted below the substrate 10. The DC bias circuit 5 is coupled to the semiconductor device 2. The DC bias circuit 5 is supplied with DC power from outside the RF power amplifier module 1.
Further, reference power GND is supplied to an unillustrated power supply wiring line provided in the substrate 10. The reference power GND is 0 V, for example.
The semiconductor device 2 includes an external terminal 201 as an input-side external terminal, and the internal circuit 24 coupled to the external terminal 201. The external terminal 201 and the internal circuit 24 are formed on a semiconductor substrate 21. The external terminal 201 is coupled to the input section matching circuit 3. Here, the internal circuit 24 is an RF power amplifier.
A coupling capacitor 202 is electrically coupled in series between the external terminal 201 and the internal circuit 24. Further, one end of a DC bias resistance 203 is coupled between the coupling capacitor 202 and the internal circuit 24, and another end of the DC bias resistance 203 is coupled to an external power supply terminal 208. The DC bias circuit 5 is coupled to the external power supply terminal 208 and, for example, negative DC bias power is supplied from the DC bias circuit 5. Moreover, one of electrodes of a decoupling capacitor 207 is coupled between the other end of the DC bias resistance 203 and the external power supply terminal 208. Another of the electrodes of the decoupling capacitor 207 is coupled to a reference power supply GND.
The semiconductor device 2 further includes the protection circuit 22 as the input-side protection circuit. In the first embodiment, the protection circuit 22 includes one MISFET 221. The MISFET 221 corresponds to a “first insulated gate field-effect transistor” according to the present technology.
In the MISFET 221, an electric charge accumulation section (see a reference numeral 219 in
A first main electrode (for example, a drain electrode) as one of main electrodes of the MISFET 221 is coupled between the external terminal 201 and the internal circuit 24 with the DC bias resistance 203 interposed therebetween. To be more specific, the first main electrode is coupled between the coupling capacitor 202 and the internal circuit 24. A second main electrode (for example, a source electrode) as another of the main electrodes and a gate electrode of the MISFET 221 are coupled to the reference power supply GND.
The protection circuit 22 further includes a resistance 222. The resistance 222 is electrically coupled in series between the second main electrode and the gate electrode of the MISFET 221. The resistance 222 corresponds to a “resistance” according to the present technology. The resistance 222 is set to a resistance value of, for example, 100 Ω or more and 10 MΩ or less. It is to be noted that as with the resistance 222, the DC bias resistance 203 is set to a resistance value of, for example, 10 Ω or more and 10 MΩ or less.
The protection circuit 22 is provided with a first external terminal 204, a second external terminal 205, and a third external terminal 206 for injecting hot carriers into the electric charge accumulation section of the MISFET 221. Here, the hot carriers are hot electrons. The first external terminal 204, the second external terminal 205, and the third external terminal 206 are provided on the semiconductor substrate 21.
The first external terminal 204 is coupled to the first main electrode of the MISFET 221. The first external terminal 204 corresponds to a “first external terminal” according to the present technology. The second external terminal 205 is coupled to the second main electrode. The second external terminal 205 corresponds to a “second external terminal” according to the present technology. The third external terminal 206 is coupled to the gate electrode. The third external terminal 206 corresponds to a “third external terminal” according to the present technology.
The MISFET 221 constructing the protection circuit 22 and the MISFET 241 constructing the internal circuit 24 are formed on the semiconductor substrate 21 with a buffer layer 211 interposed therebetween. For example, a Si substrate is used as the semiconductor substrate 21. In a case of a 6-inch Si wafer, the Si substrate is formed in a thickness of 600 μm or more and 700 μm or less. For example, the buffer layer 211 includes AlGaN. AlGaN is formed into a thickness of 0.3 μm or more and 1.0 μm or less by an epitaxial growth method, for example.
It is to be noted that a ceramic substrate such as a sapphire substrate may be used instead of the semiconductor substrate 21.
First, the MISFET 241 constructing the internal circuit 24 is provided on the buffer layer 211 in a region surrounded by an element separation section 212. The MISFET 241 includes a semiconductor layer 213, a two-dimensional electron gas (Two Dimensional Electron gas: hereinafter simply referred to as “2DEG”) 214, a gate insulating film 215, a gate electrode 216, and a pair of main electrodes 217. The MISFET 241 corresponds to a “second insulated gate field-effect transistor” according to the present technology.
At a location between the MISFETs 241 adjacent to each other, the element separation section 212 makes the semiconductor layer 213 amorphous and eliminates electrical conductivity of the 2DEG 214. The element separation section 212 is formed by an ion implantation method, for example. In the ion implantation method, for example, B ions are used as ions to be implanted. To be more specific, for example, B ions are implanted under a condition in which acceleration energy is 50 keV and an amount of dose is about 1×1015 ions/cm2.
Here, the semiconductor layer 213 includes a GaN layer 213A, a GaN channel layer 213B, an AlN layer 213C, and an InAlN layer 213D.
The GaN layer 213A is stacked on the buffer layer 211. The GaN layer 213A is formed in a thickness of, for example, 0.8 μm or more and 1.5 μm or less.
The GaN channel layer 213B is stacked on the GaN layer 213A. The GaN channel layer 213B is formed in a thickness of, for example, 100 nm or more and 500 nm or less.
The AlN layer 213C is stacked on the GaN channel layer 213B. The AlN layer 213C is formed in a thickness of, for example, 0.5 nm or more and 1.5 nm or less.
The InAlN layer 213D is stacked on the AlN layer 213C. The InAlN layer 213D is formed in a thickness of, for example, 5 nm or more and 15 nm or less.
The 2DEG 214 is generated at the GaN channel layer 213B in the vicinity of an interface between the GaN channel layer 213B and the InAlN layer 213D to extend from one of the main electrodes 217 to another of the main electrodes 217. When no gate voltage is supplied to the gate electrode 216, the 2DEG 214 is formed at all times and therefore the MISFET 214 is in a conducting state. That is, the MISFET 214 is of the depletion type.
The MISFET 241 is configured with a high electron mobility transistor (High Electron Mobility Transistor; hereinafter simply referred to as “HEMT”) structure using a compound semiconductor material. In particular, the InAlN layer 213D is stacked and spontaneous polarization of the InAlN layer 213D is utilized for generation of the 2DEG 214, and this makes it possible to increase a carrier concentration of the 2DEG 214. Accordingly, employing the HEMT structure for the MISFET 241 makes it possible to enhance RF output power of the internal circuit 24, that is, the RF power amplifier.
The gate insulating film 215 is formed on the semiconductor layer 213. Here, the gate insulating film 215 includes a first oxide film 215A, and a second oxide film 215B stacked on the first oxide film 215A. The oxide films each include at least one or more selected from Al2O3, HfO2, Ta2O5, ZrO2, Y2O3, and SiO2.
In the first embodiment, the first oxide film 215A includes Al2O3. The first oxide film 215A is formed in a thickness of, for example, 1 nm or more and 10 nm or less. Further, the second oxide film 215B includes HfO2. The second oxide film 215B is formed in a thickness of, for example, 1 nm or more and 10 nm or less.
The gate electrode 216 is stacked on the gate insulating film 215. Here, the gate electrode 216 incudes a stacked film of, for example, Ni, and Au stacked on Ni. Ni is formed in a thickness of, for example, 30 nm or more and 50 nm or less. Au is formed in a thickness of, for example, 400 nm or more and 500 nm or less.
Further, a gate length dimension of the MISFET 241 is set to, for example, 0.1 μm or more and 0.3 μm or less. Here, the gate length dimension refers to a length of the gate electrode 216 in a direction (the arrow-X direction) coinciding with a direction in which the pair of main electrodes 217 are arranged.
The pair of main electrodes 217 are in contact with or on the 2DEG 214 and stacked on the GaN channel layer 213B. On of the pair of main electrodes 217 is used as a first main electrode, e.g., a drain electrode. The other of the main electrodes 217 is used as a second main electrode, e.g., a source electrode.
The main electrodes 217 are each formed by a thermal diffusion method with a stacked film including, for example, Ti, Al stacked on Ti, Ni stacked on Al, and Au stacked on Ni. The main electrodes 217 are ohmic (Ohmic) electrodes. Ti is formed in a thickness of, for example, 5 nm or more and 15 nm or less. Al is formed in a thickness of, for example, 50 nm or more and 150 nm or less. Ni is formed in a thickness of, for example, 15 nm or more and 25 nm or less. Au is formed in a thickness of, for example, 5 nm or more and 15 nm or less.
It is to be noted that an insulator 218 is provided between each of the gate insulating film 215 and the gate electrode 216 and the main electrode 217. The insulator 218 is provided also on the element separation section 212. The insulator 218 includes, for example, Al2O3.
In contrast, the MISFET 221 constructing the protection circuit 22 is provided on the buffer layer 211 in a region surrounded by the element separation section 212, as with the MISFET 241. The MISFET 221 includes the semiconductor layer 213, the 2DEG 214, the gate insulating film 215, the electric charge accumulation section 219, the gate electrode 216, and the pair of main electrodes 217. In the semiconductor layer 213, an InAlN layer 213E is provided instead of the InAlN layer 213D.
The electric charge accumulation section 219 is configured to accumulate hot carriers. In the MISFET 221, hot carriers are injected from the 2DEG 214 to the electric charge accumulation section 219 in the vicinity of the main electrode 217 serving as the drain electrode, and the injected hot carriers are accumulated in the electric charge accumulation section 219.
When no hot carriers are accumulated in the electric charge accumulation section 219, the 2DEG 214 is generated at the GaN channel layer 213B in the vicinity of an interface between the GaN channel layer 213B and the InAlN layer 213E to extend from one of the main electrodes 217 to the other of the main electrodes 217. That is, the MISFET 221 is produced as the depletion type.
In contrast, when the hot carriers are accumulated in the electric charge accumulation section 219, the 2DEG 214 below the electric charge accumulation section 219 disappears, and the threshold voltage shifts to a positive direction. That is, the MISFET 221 is adjusted to the threshold voltage of the enhancement type.
The InAlN layer 213E of the MISFET 221 is formed in a thickness smaller than the thickness of the InAlN layer 213D of the MISFET 241. For example, the thickness of the InAlN layer 213E of the MISFET 221 is formed to be 1 nm or more and 9 nm or less, thus being formed to be ⅕ times or more and ⅗ times or less the thickness of the InAlN layer 213D of the MISFET 241.
Forming the InAlN layer 213E to be small in thickness makes it possible to improve efficiency of injection of hot carriers into the electric charge accumulation section 219.
The gate insulating film 215 of the MISFET 221 includes the first oxide film 215A, the second oxide film 215B stacked on the first oxide film 215A, a nitride film 215C stacked on the second oxide film 215B, and a third oxide film 215D stacked on the nitride film 215C. The nitride film 215C includes SiN, for example. The nitride film 215C is formed in a thickness of, for example, 1 nm or more and 10 nm or less. The third oxide film 215D includes SiO2, for example. The third oxide film 215D is formed in a thickness of, for example, 1 nm or more and 10 nm or less.
That is, for the gate insulating film 215, an ONO (Oxide-Nitride-Oxide) structure is employed in which an oxide film, a nitride film, and an oxide film are stacked one by one. Further, for the MISFET 221 including the semiconductor layer 213 and the gate electrode 216, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure is employed.
The electric charge accumulation section 219 includes the nitride film 215C having a hot carrier trap level. The electric charge accumulation section 219 may further include an interface between the nitride film 215C and the second oxide film 215B.
The gate length dimension of the MISFET 221 is set to, for example, 0.05 μm or more and 0.3 μm or less. Further, a gate width dimension of the MISFET 221 is set to, for example, 10 μm or more and 10000 μm or less. Here, the gate width dimension refers to a length of the gate electrode 216 in a gate width direction (the arrow-Y direction) orthogonal to a gate length direction.
As illustrated in
The first external terminal 204 and the like are formed in the same layer as that of the external terminal 201 that is illustrated in
The first external terminal 204 is formed integrally with respective wiring lines, whose reference signs are omitted, that are coupled to the main electrode (the first main electrode) 217 of the MISFET 221 of the protection circuit 22, the DC bias resistance 203, and the external power supply terminal 208 (see
The second external terminal 205 is formed integrally with respective wiring lines, whose reference signs are omitted, that are coupled to the resistance 222 and the main electrode (the second main electrode) 217 of the MISFET 221.
The third external terminal 206 is formed integrally with respective wiring lines, whose reference signs are omitted, that are coupled to the resistance 222 and the gate electrode 216 of the MISFET 221.
It is to be noted that as illustrated in
As illustrated in
Next, a method of manufacturing the protection circuit 22 and the semiconductor device 2 will be described briefly.
First, the semiconductor substrate 21 is prepared (see
As illustrated in
The insulator 218 is formed over an entire surface of the semiconductor layer 213 (see
Next, as illustrated in
As illustrated in
In a formation region of the gate insulating film 215 of the MISFET 221, an opening 218A is formed in the insulator 218 (see
As illustrated in
As illustrated in
In each of the formation region of the gate insulating film 215 of the MISFET 221 and the formation region of the gate insulating film 215 of the MISFET 241, an opening 218B is formed in the insulator 218 (see
As illustrated in
The gate insulating film 215 is formed by stacking the first oxide film 215A, the second oxide film 215B, the nitride film 215C, and the third oxide film 215D one by one. The gate insulating film 215 is formed by an atomic layer deposition (Atomic Layer Deposition) method or the like, for example.
Here, in the MISFET 221, the gate insulating film 215 has the ONO structure, and accordingly, the electric charge accumulation section 219 is formed. Further, at this point in time, no hot carriers have been accumulated in the electric charge accumulation section 219, and the MISFET 221 is thus formed to have the threshold voltage of the depletion type.
As illustrated in
As illustrated in
The resistance 222 and the DC bias resistance 203 are formed on the MISFET 221 and the MISFET 241, and the external terminal 201, the first external terminal 204 to the third external terminal 206, and the wiring lines are each formed in a further upper layer (see
[Method of Electric Charge Accumulation into Electric Charge Accumulation Section 219]
In the protection circuit 22 illustrated in
When the method of manufacturing the semiconductor device 2 illustrated in
It is to be noted that the injection of hot carriers may be performed after mounting of the semiconductor device 2 onto the RF power amplifier module 1.
When the injection of hot carriers is started, the hot carriers start being injected into the electric charge accumulation section 219 of the MISFET 221 of the protection circuit 22 (step S1 in
Here, assume that Vdsw represents a voltage between the drain electrode and the source electrode, BVpth represents a punchthrough voltage, Vt represents a threshold voltage, Vgsw represents a voltage between the gate electrode and the source electrode, BVg represents a gate breakdown voltage, and BVj represents a junction breakdown voltage. In this case, hot carriers are injected with conditions represented by Expressions <1> to <3> below satisfied.
Specifically, for example, Expression <1> above is calculated in accordance with Expression <4> below.
In step S1, on the basis of Expression <4> above, for example, 3.25 [V] is supplied to the first external terminal 204, 0 [V] is supplied to the second external terminal 205, and 6.5 [V] is supplied to the third external terminal 206 (see
Further, voltage conditions including the voltage Vdsw between the drain electrode and the source electrode are as follows, for example.
After step S1 ends, the threshold voltage Vt of the MISFET 221 is measured (step S2). On the basis of a measurement result, whether or not the threshold voltage Vt is greater than or equal to a predetermined value (here, 6.0 [V]) set in Expression <1> above is determined (step S3). When the threshold voltage Vt is greater than or equal to the predetermined value, the injection of hot carriers ends.
In contrast, when the threshold voltage Vt is less than the predetermined value in step S3, an additional number of times of supply of power is set (step S4). The additional number of times of supply of power is denoted as n, and n is set to 10 times, for example. In accordance with the additional number of times of supply of power, the flow returns to step S1 to continue the injection of hot carriers.
Thereafter, the injection of hot carriers ends when the threshold voltage Vt becomes greater than or equal to the predetermined value after going through step S2 and step S3. When the injection of hot carriers ends, the threshold voltage Vth of the MISTET 221 is formed into the enhancement type from the depletion type.
In the MISFET 221 of the protection circuit 22, electric charge is accumulated in the electric charge accumulation section 219, and the threshold voltage Vt is set to be higher than a protection voltage Vesd (the punchthrough voltage VBpth). Accordingly, when at a voltage less than the protection voltage Vesd, a region between the pair of main electrodes 217 of the MISFET 221 exhibits a high resistance. That is, the protection circuit 22 exerts no influence on the operation of the internal circuit 24 at a signal voltage inputted to the external terminal 201.
As illustrated in
The region between the pair of main electrodes 217 of the MISFET 221 is adjusted to be at a constant punchthrough voltage BVpth by adjustment of the gate length dimension. Accordingly, the surge voltage is reduced to the protection voltage Vesd, and an ESD protection function is thus obtained.
In contrast, if the DC bias circuit 5 is “negatively” charged, conversely to a case where it is “positively” charged, the surge current lesd flows from the reference power supply GND through the MISFET 221 and the external power supply terminal 208.
The resistance 222 is provided between the gate electrode 216 of the MISFET 221 and the main electrode 217 used as the source electrode. Accordingly, a gate potential of the gate electrode 216 rises while a gate capacitance of the gate electrode 216 is charged through the resistance 222. At this time, because the region between the pair of electrodes 217 of the MISFET 221 is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension, the surge voltage is reduced to the protection voltage Vesd. That is, the gate potential does not rise to be greater than or equal to the protection voltage Vesd, and it is thus possible to effectively suppress or prevent breakdown of the gate insulating film 215. Accordingly, it is possible to obtain the ESD protection function.
The protection circuit 22 according to the first embodiment includes the MISFET 221, as illustrated in
The MISFET 221 is formed as the depletion type and is able to be formed into the threshold voltage of the enhancement type by accumulation of hot carriers in the electric charge accumulation section 219. Accordingly, it is possible to construct the protection circuit 22 having superior ESD robustness or avalanche robustness, with use of the MISFET 221 that uses no pn junction and has a high process affinity.
In addition, the MISFET 211 uses no pn junction or no Schottky junction. Accordingly, it is possible to implement the protection circuit 22 that is free from a surge breakdown at a junction.
Further, as illustrated in
In addition, it is possible to cause the electric charge accumulation section 219 to operate as the protection circuit 22 immediately after the injection of hot carriers thereinto.
Further in addition, even if a negative surge is inputted to the external power supply terminal 208, for example, the gate potential of the MISFET 221 does not immediately rise due to a CR delay operation, and in the meantime, a punchthrough occurs between the pair of main electrodes 217. Accordingly, it is possible to achieve protection against positive and negative surges with use of the MISFET 221 alone, without causing breakdown of the gate insulating film 215.
Further, as illustrated in
Accordingly, it is possible to inject hot carriers into the electric charge accumulation section 219 on an as-needed basis immediately after production of the protection circuit 22 or thereafter to thereby start the protection function of the protection circuit 22.
Further, as illustrated in
This makes it possible to obtain workings and effects similar to the workings and effects obtainable with the protection circuit 22 described above.
In addition, it is possible to construct the MISFET 221 of the protection circuit 22 easily with use of substantially the same structure or substantially the same manufacturing process as that used for the MISFET 241 constructing the internal circuit 24.
In addition, in the semiconductor device 2, the MISFET 221 of the protection circuit 22 further includes the resistance 222 that is electrically coupled in series between the gate electrode 216 and the main electrode (the second main electrode) 217.
Accordingly, the semiconductor device 2 makes it possible to obtain workings and effects similar to the workings and effects obtainable with the protection circuit 22 described above.
Further, as illustrated in
Furthermore, in the semiconductor device 2, as illustrated in
Accordingly, it is possible to construct the electric charge accumulation section 219 easily by employing the ONO structure for the gate insulating film 215.
Further, in the semiconductor device 2, as illustrated in
Accordingly, it is possible to construct the protection circuit 22 with use of the MISFET 221 having the HEMT structure. In particular, it is possible to construct the protection circuit 22 easily with use of a structure substantially the same as the structure of the MISFET 241 constructing the internal circuit 24.
Further, in the semiconductor device 2, the MISFET 221 of the protection circuit 22 causes hot carriers to be accumulated in the electric charge accumulation section 219 and causes the threshold voltage to shift to the positive direction from the depletion type into the enhancement type.
Accordingly, the MISFET 221 of the protection circuit 22 is formed with use of substantially the same structure or substantially the same manufacturing process as that used for the MISFET 241 of the internal circuit 24. It is thus possible to construct the protection circuit 22 easily.
Further, in the semiconductor device 2, the gate length of the MISFET 221 of the protection circuit 22 illustrated in
Accordingly, in the MISFET 221, it is possible to generate a punchthrough appropriately when a surge is inputted.
Further, in the semiconductor device 2, as illustrated in
Moreover, in the semiconductor device 2, as illustrated in
Accordingly, it is possible to improve efficiency of injection of hot carriers into the electric charge accumulation section 219 of the MISFET 221.
A description will be given of the protection circuit 22 and the semiconductor device 2 according to a second embodiment of the present disclosure. It is to be noted that in the second and subsequent embodiments, the same components or substantially the same components as those of the protection circuit 22 and the semiconductor device 2 according to the first embodiment are assigned the same reference numerals, and redundant descriptions will thus be omitted.
In the protection circuit 22 and the semiconductor device 2 according to the second embodiment, the MISFET 221 of the protection circuit 22 is provided with the InAlN layer 213E in a portion of the InAlN layer 213D of the semiconductor layer 213, the InAlN layer 213E being smaller in thickness than the InAlN layer 213D. To be more specific, the InAlN layer 213E is provided in the vicinity of the main electrode (the first main electrode) 217 used as the drain electrode in the gate length direction.
Hot carriers to be injected into the electric charge accumulation section 219 are generated in the vicinity of the drain electrode where electric field intensity becomes high.
Configurations except for the above are similar to the configurations of the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
The protection circuit 22 and the semiconductor device 2 according to the second embodiment make it possible to obtain workings and effects similar to the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
Moreover, as illustrated in
A description will be given of the protection circuit 22 and the semiconductor device 2 according to a third embodiment of the present disclosure. The third embodiment is a modification example of the protection circuit 22 and the internal circuit 24 according to the first embodiment.
In the protection circuit 22 and the semiconductor device 2 according to the third embodiment, the main electrode (the first main electrode) of the MISFET 221 is coupled between the external terminal 201 and the coupling capacitor 202 with a surge inductive resistance 223 interposed therebetween.
Further, the one end of the DC bias resistance 203 is coupled between the coupling capacitor 202 and the internal circuit 24, and the other end of the DC bias resistance 203 is coupled to the decoupling capacitor 207 and a DC bias circuit 25. The DC bias circuit 25 replaces the externally attachable DC bias circuit 5 and is contained in the semiconductor device 2.
Configurations except for the above are similar to the configurations of the protection circuit 22 and the semiconductor device 2 according to the first embodiment. [Circuit Operation of Protection Circuit 22]
In the MISFET 221 of the protection circuit 22, electric charge is accumulated in the electric charge accumulation section 219, and the threshold voltage Vt is set to be higher than the protection voltage Vesd (the punchthrough voltage VBpth). Accordingly, when at a voltage less than the protection voltage Vesd, the region between the pair of main electrodes of the MISFET 221 exhibits a high resistance. That is, the protection circuit 22 exerts no influence on the operation of the internal circuit 24 at the signal voltage inputted to the external terminal 201.
As illustrated in
The region between the pair of main electrodes of the MISFET 221 is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension. Accordingly, the surge voltage is reduced to the protection voltage Vesd, and the ESD protection function is thus obtained.
Conversely, if a “negative” surge voltage is applied to the external terminal 201, the surge current Iesd flows from the reference power supply GND side to the external terminal 201 through the pair of main electrodes of the MISFET 221 and the surge inductive resistance 223.
The resistance 222 is provided between the gate electrode of the MISFET 221 and the main electrode used as the source electrode. Accordingly, the gate potential of the gate electrode rises while the gate capacitance of the gate electrode is charged through the resistance 222. At this time, because the region between the pair of electrodes of the MISFET 221 is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension, the surge voltage is reduced to the protection voltage Vesd. That is, the gate potential does not rise to be greater than or equal to the protection voltage Vesd, and it is thus possible to effectively suppress or prevent the breakdown of the gate insulating film. Accordingly, it is possible to obtain the ESD protection function.
The protection circuit 22 and the semiconductor device 2 according to the third embodiment make it possible to obtain workings and effects similar to the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
Moreover, in the protection circuit 22 and the semiconductor device 2, protection against positive and negative surges is achievable with use of the MISFET 221 alone.
A description will be given of the protection circuit 22 and the semiconductor device 2 according to a fourth embodiment of the present disclosure. The fourth embodiment is a modification example of the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
In the protection circuit 22 and the semiconductor device 2 according to the fourth embodiment, the protection circuit 22 is coupled between the coupling capacitor 202 and the internal circuit 24 with the DC bias resistance 203 interposed therebetween.
The protection circuit 22 includes two MISFETs 221A and 221B that share the main electrode (here, the second main electrode) used as the drain electrode and are electrically coupled in series to each other. The second main electrode of the MISFET 221A and the MISFET 221B is coupled to the first external terminal 204.
The main electrode (here, the first main electrode) used as the source electrode of the MISFET 221B is coupled to the DC bias resistance 203.
A resistance 222A is electrically coupled in series between the first main electrode of the MISFET 221A and the gate electrode. The first main electrode of the MISFET 221A is coupled to a second external terminal 205A and the reference power supply GND. The gate electrode is coupled to a third external terminal 206A.
In contrast, a resistance 222B is electrically coupled in series between the first main electrode of the MISFET 221B and the gate electrode. The first main electrode of the MISFET 221B is coupled to a second external terminal 205B. The gate electrode is coupled to a third external terminal 206B. That is, the MISFET 221A and the MISFET 221B are disposed symmetrically with respect to the second main electrode.
The externally attachable DC bias circuit 5 is coupled to the external power supply terminal 208.
In the protection circuit 22, the injection of hot carriers into the electric charge accumulation section 219 is performed in the order of the MISFET 221A and the MISFET 221B or in the reverse order, or is performed on both of them simultaneously.
In each of the MISFET 221A and the MISFET 221B of the protection circuit 22, electric charge is accumulated in the electric charge accumulation section 219, and the threshold voltage Vt is set to be higher than the protection voltage Vesd (the punchthrough voltage VBpth). Accordingly, when at a voltage less than the protection voltage Vesd, a region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B exhibits a high resistance. That is, the protection circuit 22 exerts no influence on the operation of the internal circuit 24 at the signal voltage inputted to the external terminal 201.
In the protection circuit 22, the MISFET 221A and the MISFET 221B are stacked in two layers. The MISFET 221A and the MISFET 221B share the second main electrode. The first main electrode of the MISFET 221B is coupled to the external power supply terminal 208. The first main electrode of the MISFET 221A is coupled to the reference power supply GND. Thus, the protection voltage Vesd of the protection circuit 22 according to the fourth embodiment is approximately twice that of the protection circuit 22 according to the first embodiment.
Further, in the protection circuit 22 according to the first embodiment, a slight difference is observed between respective response characteristics to protection against the “positive” surge and the “negative” surge. In contrast, the protection circuit 22 according to the fourth embodiment exhibits substantially the same response characteristics to the protection because the MISFET 221A and the MISFET 221B are disposed symmetrically.
As illustrated in
In contrast, if the DC bias circuit 5 is “negatively” charged, conversely to the case where it is “positively” charged, the surge current lesd flows from the reference power supply GND to the DC bias circuit 5 through the MISFET 221A, the MISFET 221B, and the external power supply terminal 208.
The resistance 222A is provided between the gate electrode of the MISFET 221A and the first main electrode used as the source electrode. The resistance 222B is provided between the gate electrode of the MISFET 221B and the main electrode used as the source electrode.
Accordingly, the surge current flowing from the source electrode side raises the gate potential of the gate electrode while allowing the gate capacitance of the gate electrode to be charged through the resistance 222A or the resistance 222B. At this time, because the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension, the surge voltage is reduced to the protection voltage Vesd. That is, the gate potential does not rise to be greater than or equal to the protection voltage Vesd, and it is thus possible to effectively suppress or prevent the breakdown of the gate insulating film. Accordingly, it is possible to obtain the ESD protection function.
The protection circuit 22 and the semiconductor device 2 according to the fourth embodiment make it possible to obtain workings and effects similar to the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
Further, in the protection circuit 22, the MISFET 221A and the MISFET 221B are disposed symmetrically, which makes it possible to address positive and negative surge voltages. The protection voltage Vesd is approximately twice that of the protection circuit 22 according to the first embodiment: however, polarity variations of the punchthrough voltage BVpth are suppressed and transient response characteristics to the positive and negative surge voltages become the same.
Moreover, according to the protection circuit 22, because the protection voltage Vesd is approximately twice that in the case of a single device, a withstand voltage of an RF signal doubles, which makes it possible to achieve higher RF output power.
A description will be given of the protection circuit 22 and the semiconductor device 2 according to a fifth embodiment of the present disclosure. The fifth embodiment is a modification example in which the third embodiment and the fourth embodiment are combined.
Further, the one end of the DC bias resistance 203 is coupled between the coupling capacitor 202 and the internal circuit 24, and the other end of the DC bias resistance 203 is coupled to the decoupling capacitor 207 and the DC bias circuit 25. The DC bias circuit 25 replaces the externally attachable DC bias circuit 5 and is contained in the semiconductor device 2.
Configurations except for the above are similar to the configurations of the protection circuit 22 and the semiconductor device 2 according to each of the third embodiment and the fourth embodiment.
In the MISFET 221A and the MISFET 221B of the protection circuit 22, electric charge is accumulated in the electric charge accumulation section 219, and the threshold voltage Vt is set to be higher than the protection voltage Vesd (the punchthrough voltage VBpth). Accordingly, when at a voltage less than the protection voltage Vesd, the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B exhibits a high resistance. That is, the protection circuit 22 exerts no influence on the operation of the internal circuit 24 at the signal voltage inputted to the external terminal 201.
In the protection circuit 22, the MISFET 221A and the MISFET 221B are stacked in two layers. The MISFET 221A and the MISFET 221B share the second main electrode. The first main electrode of the MISFET 221B is coupled to the external terminal 201 through the surge inductive resistance 223. The first main electrode of the MISFET 221A is coupled to the reference power supply GND. Thus, the protection voltage Vesd of the protection circuit 22 according to the fifth embodiment is approximately twice that of the protection circuit 22 according to the first embodiment.
Further, in the protection circuit 22 according to the first embodiment, a slight difference is observed between the respective response characteristics to protection against the “positive” surge and the “negative” surge. In contrast, the protection circuit 22 according to the fifth embodiment exhibits substantially the same response characteristics to the protection because the MISFET 221A and the MISFET 221B are disposed symmetrically.
As illustrated in
The region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension. Accordingly, the surge voltage is reduced to the protection voltage Vesd, and the ESD protection function is thus obtained.
Conversely, if the “negative” surge voltage is applied to the external terminal 201, the surge current lesd flows from the reference power supply GND side to the external terminal 201 through the MISFET 221A, the MISFET 221B, and the surge inductive resistance 223.
The resistance 222A is provided between the gate electrode of the MISFET 221A and the main electrode used as the source electrode. The resistance 222B is provided between the gate electrode of the MISFET 221B and the main electrode used as the source electrode.
Accordingly, the surge current flowing from the source electrode side raises the gate potential of the gate electrode while allowing the gate capacitance of the gate electrode to be charged through the resistance 222A or the resistance 222B. At this time, because the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension, the surge voltage is reduced to the protection voltage Vesd. That is, the gate potential does not rise to be greater than or equal to the protection voltage Vesd, and it is thus possible to effectively suppress or prevent the breakdown of the gate insulating film. Accordingly, it is possible to obtain the ESD protection function.
The protection circuit 22 and the semiconductor device 2 according to the fifth embodiment make it possible to obtain workings and effects as a resultant of combination of the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the third embodiment and the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the fourth embodiment.
A description will be given of the protection circuit 22 and the semiconductor device 2 according to a sixth embodiment of the present disclosure. The sixth embodiment is a modification example of the protection circuit 22 and the semiconductor device 2 according to the fourth embodiment.
In the protection circuit 22 and the semiconductor device 2 according to the sixth embodiment, the protection circuit 22 includes the two MISFETs 221A and 221B that share the main electrode (here, the second main electrode) used as the source electrode and are electrically coupled in series to each other. The second main electrode of the MISFET 221A and the MISFET 221B is coupled to the second external terminal 205.
The main electrode (here, the first main electrode) used as the drain electrode of the MISFET 221B is coupled to the DC bias resistance 203.
The resistance 222 for common use is electrically coupled in series between the second main electrode of the MISFET 221A and the gate electrode, and between the MISFET 221B and the second main electrode. The first main electrode of the MISFET 221A is coupled to a first external terminal 204A and the reference power supply GND. The gate electrode is coupled to the third external terminal 206 that is common to the gate electrode of the MISFET 221B.
In contrast, the first main electrode of the MISFET 221B is coupled to a first external terminal 204B.
The MISFET 221A and the MISFET 221B are disposed symmetrically with respect to the second main electrode.
The externally attachable DC bias circuit 5 is coupled to the external power supply terminal 208.
In each of the MISFET 221A and the MISFET 221B of the protection circuit 22, electric charge is accumulated in the electric charge accumulation section 219, and the threshold voltage Vt is set to be higher than the protection voltage Vesd (the punchthrough voltage VBpth). Accordingly, when at a voltage less than the protection voltage Vesd, the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B exhibits a high resistance. That is, the protection circuit 22 exerts no influence on the operation of the internal circuit 24 at the signal voltage inputted to the external terminal 201.
In the protection circuit 22, the MISFET 221A and the MISFET 221B are stacked in two layers. The MISFET 221A and the MISFET 221B share the second main electrode. The first main electrode of the MISFET 221B is coupled to the external power supply terminal 208. The first main electrode of the MISFET 221A is coupled to the reference power supply GND. Thus, the protection voltage Vesd of the protection circuit 22 according to the sixth embodiment is approximately twice that of the protection circuit 22 according to the first embodiment.
Further, in the protection circuit 22 according to the first embodiment, a slight difference is observed between the respective response characteristics to protection against the “positive” surge and the “negative” surge. In contrast, the protection circuit 22 according to the sixth embodiment exhibits substantially the same response characteristics to the protection because the MISFET 221A and the MISFET 221B are disposed symmetrically.
As illustrated in
In contrast, if the DC bias circuit 5 is “negatively” charged, conversely to the case where it is “positively” charged, the surge current Iesd flows from the reference power supply GND to the DC bias circuit 5 through the MISFET 221A, the MISFET 221B, and the external power supply terminal 208.
The resistance 222 is provided between the gate electrode of each of the MISFET 221A and the MISFET 221B and the second main electrode used as the source electrode.
Accordingly, the surge current flowing from the source electrode side raises the gate potential of the gate electrode while allowing the gate capacitance of the gate electrode to be charged through the resistance 222. At this time, because the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension, the surge voltage is reduced to the protection voltage Vesd. That is, the gate potential does not rise to be greater than or equal to the protection voltage Vesd, and it is thus possible to effectively suppress or prevent the breakdown of the gate insulating film. Accordingly, it is possible to obtain the ESD protection function.
The protection circuit 22 and the semiconductor device 2 according to the sixth embodiment make it possible to obtain workings and effects similar to the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the fourth embodiment.
A description will be given of the protection circuit 22 and the semiconductor device 2 according to a seventh embodiment of the present disclosure. The seventh embodiment is an example in which the protection circuit 22 and the semiconductor device 2 according to the fifth embodiment and the protection circuit 22 and the semiconductor device 2 according to the sixth embodiment are combined. [Configuration of Protection Circuit 22 and Semiconductor Device 2]
In the protection circuit 22 and the semiconductor device 2 according to the seventh embodiment, the protection circuit 22 is coupled between the external terminal 201 and the coupling capacitor 202 with the surge inductive resistance 223 interposed therebetween. The protection circuit 22 includes the two MISFETs 221A and 221B that are arranged symmetrically, as with the protection circuit 22 according to the sixth embodiment.
Further, the one end of the DC bias resistance 203 is coupled between the coupling capacitor 202 and the internal circuit 24, and the other end of the DC bias resistance 203 is coupled to the decoupling capacitor 207 and the DC bias circuit 25. The DC bias circuit 25 replaces the externally attachable DC bias circuit 5 and is contained in the semiconductor device 2.
Configurations except for the above are similar to the configurations of the protection circuit 22 and the semiconductor device 2 according to each of the fifth embodiment and the sixth embodiment.
In the MISFET 221A and the MISFET 221B of the protection circuit 22, electric charge is accumulated in the electric charge accumulation section 219, and the threshold voltage Vt is set to be higher than the protection voltage Vesd (the punchthrough voltage VBpth). Accordingly, when at a voltage less than the protection voltage Vesd, the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B exhibits a high resistance. That is, the protection circuit 22 exerts no influence on the operation of the internal circuit 24 at the signal voltage inputted to the external terminal 201.
In the protection circuit 22, the MISFET 221A and the MISFET 221B are stacked in two layers. The MISFET 221A and the MISFET 221B share the second main electrode. The first main electrode of the MISFET 221B is coupled to the external terminal 201 through the surge inductive resistance 223. The first main electrode of the MISFET 221A is coupled to the reference power supply GND. Thus, the protection voltage Vesd of the protection circuit 22 according to the seventh embodiment is approximately twice that of the protection circuit 22 according to the first embodiment.
Further, in the protection circuit 22 according to the first embodiment, a slight difference is observed between the respective response characteristics to protection against the “positive” surge and the “negative” surge. In contrast, the protection circuit 22 according to the seventh embodiment exhibits substantially the same response characteristics to the protection because the MISFET 221A and the MISFET 221B are disposed symmetrically.
As illustrated in
The region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension. Accordingly, the surge voltage is reduced to the protection voltage Vesd, and the ESD protection function is thus obtained.
Conversely, if the “negative” surge voltage is applied to the external terminal 201, the surge current lesd flows from the reference power supply GND side to the external terminal 201 through the MISFET 221A, the MISFET 221B, and the surge inductive resistance 223.
The resistance 222 is provided between the gate electrode of each of the MISFET 221A and the MISFET 221B and the main electrode used as the source electrode.
Accordingly, the surge current flowing from the source electrode side raises the gate potential of the gate electrode while allowing the gate capacitance of the gate electrode to be charged through the resistance 222. At this time, because the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension, the surge voltage is reduced to the protection voltage Vesd. That is, the gate potential does not rise to be greater than or equal to the protection voltage Vesd, and it is thus possible to effectively suppress or prevent the breakdown of the gate insulating film. Accordingly, it is possible to obtain the ESD protection function.
The protection circuit 22 and the semiconductor device 2 according to the seventh embodiment make it possible to obtain workings and effects as a resultant of combination of the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the fifth embodiment and the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the sixth embodiment.
A description will be given of the protection circuit 22 and the semiconductor device 2 according to an eighth embodiment of the present disclosure. The eighth embodiment is a modification example of the protection circuit 22 and the semiconductor device 2 according to the sixth embodiment.
In the protection circuit 22 and the semiconductor device 2 according to the eighth embodiment, the protection circuit 22 is coupled between the coupling capacitor 202 and the internal circuit 24 with the DC bias resistance 203 interposed therebetween.
The protection circuit 22 includes the two MISFETs 221A and 221B that are electrically coupled in parallel to each other.
The first main electrode used as a drain region of the MISFET 221A is coupled to the first external terminal 204A, and is coupled to the DC bias resistance 203 with a current mitigation resistance 224A interposed therebetween. The second main electrode used as the source electrode is coupled to the second external terminal 205A, and is coupled to the reference power supply GND with a current mitigation resistance 224B interposed therebetween. The gate electrode is coupled to the third external terminal 206A. The resistance 222A is electrically coupled in series between the second main electrode and the gate electrode.
The current mitigation resistance 224A and the current mitigation resistance 224B each mitigate the flow of current at the time of injection of hot carriers.
The first main electrode used as the drain region of the MISFET 221B is coupled to the first external terminal 204B, and is coupled to the reference power supply GND with a current mitigation resistance 224C interposed therebetween. The second main electrode used as the source electrode is coupled to the second external terminal 205B, and is coupled to the DC bias resistance 203 with a current mitigation resistance 224D interposed therebetween. The gate electrode is coupled to the third external terminal 206B. The resistance 222B is electrically coupled in series between the second main electrode and the gate electrode.
The current mitigation resistance 224C and the current mitigation resistance 224D each mitigate the flow of current at the time of injection of hot carriers.
The MISFET 221A and the MISFET 221B have a configuration in which the first main electrode and the second main electrode are opposite to each other in polarity.
The externally attachable DC bias circuit 5 is coupled to the external power supply terminal 208.
In the MISFET 221A and the MISFET 221B of the protection circuit 22, electric charge is accumulated in the electric charge accumulation section 219, and the threshold voltage Vt is set to be higher than the protection voltage Vesd (the punchthrough voltage VBpth). Accordingly, when at a voltage less than the protection voltage Vesd, the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B exhibits a high resistance. That is, the protection circuit 22 exerts no influence on the operation of the internal circuit 24 at the signal voltage inputted to the external terminal 201.
Because the MISFET 221A and the MISFET 221B are disposed with their polarities being in opposite directions to each other, the protection voltage Vesd of the protection circuit 22 is equal to the protection voltage Vesd of the protection circuit 22 according to the first embodiment.
In the protection circuit 22 according to the first embodiment, a slight difference is observed between the respective response characteristics to protection against the “positive” surge and the “negative” surge. In contrast, the protection circuit 22 according to the eighth embodiment exhibits substantially the same response characteristics to the protection because the polarities of the MISFET 221A and the MISFET 221B are made to be in opposite left and right directions.
As illustrated in
In contrast, if the DC bias circuit 5 is “negatively” charged, conversely to the case where it is “positively” charged, the surge current lesd flows from the reference power supply GND to the DC bias circuit 5 through the MISFET 221B and the external power supply terminal 208.
The resistance 222A is provided between the gate electrode of the MISFET 221A and the second main electrode. The resistance 222B is provided between the gate electrode of the MISFET 221B and the second main electrode.
Accordingly, the surge current flowing from the source electrode side raises the gate potential of the gate electrode while allowing the gate capacitance of the gate electrode to be charged through the resistance 222A or the resistance 222B. At this time, because the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension, the surge voltage is reduced to the protection voltage Vesd. That is, the gate potential does not rise to be greater than or equal to the protection voltage Vesd, and it is thus possible to effectively suppress or prevent the breakdown of the gate insulating film. Accordingly, it is possible to obtain the ESD protection function.
The protection circuit 22 and the semiconductor device 2 according to the eighth embodiment make it possible to obtain workings and effects similar to the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
Moreover, because the protection circuit 22 includes the MISFET 221A and the MISFET 221B whose polarities are set to opposite directions to each other, it is possible to effectively suppress polarity variations of the surge. Further, it is possible to make the transient response characteristics to the positive and negative surges equal.
A description will be given of the protection circuit 22 and the semiconductor device 2 according to a ninth embodiment of the present disclosure. The ninth embodiment is an example in which the protection circuit 22 and the semiconductor device 2 according to the seventh embodiment and the protection circuit 22 and the semiconductor device 2 according to the eighth embodiment are combined.
The protection circuit 22 includes the two MISFETs 221A and 221B that are electrically coupled in parallel to each other, as with the protection circuit 22 according to the eighth embodiment.
A configuration and a circuit operation except for the above are substantially the same as the configuration and the circuit operation of the protection circuit 22 according to the seventh embodiment and those of the protection circuit 22 according to the eighth embodiment, and descriptions thereof will thus be omitted here.
The protection circuit 22 and the semiconductor device 2 according to the ninth embodiment make it possible to obtain workings and effects as a resultant of combination of the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the seventh embodiment and the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the eighth embodiment.
A description will be given of the protection circuit 22 and the semiconductor device 2 according to a tenth embodiment of the present disclosure. The tenth embodiment is a modification example of the protection circuit 22 and the semiconductor device 2 according to the eighth embodiment.
In the protection circuit 22 and the semiconductor device 2 according to the tenth embodiment, the protection circuit 22 is coupled between the coupling capacitor 202 and the internal circuit 24 with the DC bias resistance 203 interposed therebetween.
The protection circuit 22 includes the two MISFETs 221A and 221B that are electrically coupled in parallel to each other.
The first main electrode used as the drain region of the MISFET 221A is coupled to the first external terminal 204A, and is coupled to the DC bias resistance 203. The second main electrode used as the source electrode is coupled to the first external terminal 204B, and is coupled to the reference power supply GND. The gate electrode is coupled to the third external terminal 206A. The resistance 222A is electrically coupled in series between the second main electrode and the gate electrode.
The first main electrode used as the drain region of the MISFET 221B is coupled to the first external terminal 204B, and is coupled to the reference power supply GND. The first external terminal 204B is also coupled to the second main electrode of the MISFET 221A. The second main electrode used as the source electrode is coupled to the first external terminal 204A, and is coupled to the DC bias resistance 203. The first external terminal 204A is also coupled to the first main electrode of the MISFET 221A. The gate electrode is coupled to the third external terminal 206B. The resistance 222B is electrically coupled in series between the second main electrode and the gate electrode.
The MISFET 221A and the MISFET 221B have a configuration in which the first main electrode and the second main electrode are opposite to each other in polarity.
The externally attachable DC bias circuit 5 is coupled to the external power supply terminal 208.
In the MISFET 221A and the MISFET 221B of the protection circuit 22, electric charge is accumulated in the electric charge accumulation section 219, and the threshold voltage Vt is set to be higher than the protection voltage Vesd (the punchthrough voltage VBpth). Accordingly, when at a voltage less than the protection voltage Vesd, the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B exhibits a high resistance. That is, the protection circuit 22 exerts no influence on the operation of the internal circuit 24 at the signal voltage inputted to the external terminal 201.
Because the MISFET 221A and the MISFET 221B are disposed with their polarities being in opposite directions to each other, the protection voltage Vesd of the protection circuit 22 is equal to the protection voltage Vesd of the protection circuit 22 according to the first embodiment.
In the protection circuit 22 according to the first embodiment, a slight difference is observed between the respective response characteristics to protection against the “positive” surge and the “negative” surge. In contrast, the protection circuit 22 according to the tenth embodiment exhibits substantially the same response characteristics to the protection because the polarities of the MISFET 221A and the MISFET 221B are made to be in opposite left and right directions.
As illustrated in
In contrast, if the DC bias circuit 5 is “negatively” charged, conversely to the case where it is “positively” charged, the surge current lesd flows from the reference power supply GND to the DC bias circuit 5 through the MISFET 221B and the external power supply terminal 208.
The resistance 222A is provided between the gate electrode of the MISFET 221A and the second main electrode. The resistance 222B is provided between the gate electrode of the MISFET 221B and the second main electrode.
Accordingly, the surge current flowing from the source electrode side raises the gate potential of the gate electrode while allowing the gate capacitance of the gate electrode to be charged through the resistance 222A or the resistance 222B. At this time, because the region between the pair of main electrodes of each of the MISFET 221A and the MISFET 221B is at the constant punchthrough voltage BVpth by adjustment of the gate length dimension, the surge voltage is reduced to the protection voltage Vesd. That is, the gate potential does not rise to be greater than or equal to the protection voltage Vesd, and it is thus possible to effectively suppress or prevent the breakdown of the gate insulating film. Accordingly, it is possible to obtain the ESD protection function.
The protection circuit 22 and the semiconductor device 2 according to the tenth embodiment make it possible to obtain workings and effects similar to the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the eighth embodiment.
Moreover, in the protection circuit 22, the first external terminal 204A also serves as an external terminal that couples the first main electrode of the MISFET 221A and the second main electrode of the MISFET 221B to each other. Similarly, the second external terminal 204B also serves as an external terminal that couples the second main electrode of the MISFET 221A and the first main electrode of the MISFET 221B to each other. Accordingly, it is possible to reduce the number of external terminals for injecting hot carriers.
A description will be given of the protection circuit 22 and the semiconductor device 2 according to an eleventh embodiment of the present disclosure. The eleventh embodiment is an example in which the protection circuit 22 and the semiconductor device 2 according to the ninth embodiment and the protection circuit 22 and the semiconductor device 2 according to the tenth embodiment are combined.
[Configuration of Protection Circuit 22 and Semiconductor Device 2]
In the protection circuit 22 and the semiconductor device 2 according to the eleventh embodiment, the protection circuit 22 is coupled between the external terminal 201 and the coupling capacitor 202 with the surge inductive resistance 223 interposed therebetween.
The protection circuit 22 includes the two MISFETs 221A and 221B that are electrically coupled in parallel to each other, as with the protection circuit 22 according to the tenth embodiment.
A configuration and a circuit operation except for the above are substantially the same as the configuration and the circuit operation of the protection circuit 22 according to the ninth embodiment and those of the protection circuit 22 according to the tenth embodiment, and descriptions thereof will thus be omitted here.
The protection circuit 22 and the semiconductor device 2 according to the eleventh embodiment make it possible to obtain workings and effects as a resultant of combination of the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the ninth embodiment and the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the tenth embodiment.
A description will be given of the protection circuit 22 and the semiconductor device 2 according to a twelfth embodiment of the present disclosure. The twelfth embodiment is a modification example of the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
In the protection circuit 22 and the semiconductor device 2 according to the twelfth embodiment, an externally attachable protection element 6 is coupled to the external power supply terminal 208, being electrically in parallel to the DC bias circuit 5. The externally attachable protection element 6 has further higher ESD protection robustness relative to the ESD protection robustness of the protection circuit 22. For example, a GGnMOS-Tr (Gate Grounded n-type MOSFET), pn diode, or the like is practically usable as the externally attachable protection element 6.
A configuration and a circuit operation except for the above are substantially the same as the configuration and the circuit operation of the protection circuit 22 according to the first embodiment, and descriptions thereof will thus be omitted here.
The protection circuit 22 and the semiconductor device 2 according to the twelfth embodiment make it possible to obtain workings and effects similar to the workings and effects obtainable with the protection circuit 22 and the semiconductor device 2 according to the first embodiment.
Moreover, owing to the provision of the externally attachable protection element 6, it is possible to further improve the ESD robustness of the semiconductor device 2.
The present technology is not limited to the embodiments described above, and various modifications may be made without departing from the gist of the present technology.
For example, the protection circuits and the semiconductor devices according to any two or more of the first to twelfth embodiments described above may be combined.
Further, although the description has been given of the input-side protection circuit by way of example, the present technology may be applied to the output-side protection circuit.
Further, the present technology may be applied not only to the insulated gate field-effect transistor that includes the compound semiconductor material but also to a protection circuit and a semiconductor device each including an insulated gate field-effect transistor that includes a Si semiconductor material.
The protection circuit according to the first embodiment of the present disclosure includes the MISFET. The MISFET couples the first main electrode between the external terminal and the internal circuit, and couples the second main electrode to the reference power supply. In addition, the electric charge accumulation section configured to accumulate hot carriers is provided in the gate insulating film.
The MISFET is formed as the depletion type and is able to be formed into the threshold voltage of the enhancement type by accumulating hot carriers in the electric charge accumulation section. Accordingly, it is possible to construct the protection circuit having superior ESD robustness or avalanche robustness, with use of the MISFET that uses no pn junction and has a high process affinity.
Further, the semiconductor device according to the second embodiment of the present disclosure includes the external terminal, the internal circuit, and the protection circuit. The protection circuit is provided on the semiconductor substrate and includes the MISFET. The MISFET couples the first main electrode between the external terminal and the internal circuit, couples the second main electrode and the gate electrode to the reference power supply, and provides the electric charge accumulation section configured to accumulate hot carriers. Accordingly, it is possible to obtain workings and effects similar to the workings and effects obtainable with the protection circuit described above.
The present technology includes the following configurations. The present technology having the following configurations makes it possible to construct the protection circuit and the semiconductor device that are superior in ESD robustness or avalanche robustness, with use of the MISFET having a high process affinity.
The present application claims the benefit of Japanese Priority Patent Application JP2021-114604 filed with the Japan Patent Office on Jul. 9, 2021, the entire contents of which are incorporated herein by reference.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-114604 | Jul 2021 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/005953 | 2/15/2022 | WO |
