Protection of NROM devices from charge damage

Information

  • Patent Grant
  • 7317633
  • Patent Number
    7,317,633
  • Date Filed
    Tuesday, July 5, 2005
    19 years ago
  • Date Issued
    Tuesday, January 8, 2008
    16 years ago
Abstract
A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMOS transistors sharing a common deep N well and the NMOS transistors connected to a P well, wherein during negative charging, the NMOS transistors shunt leakage current to ground, and during positive charging, the PMOS transistors shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.
Description
FIELD OF THE INVENTION

The present invention relates to NROM devices, and more particularly to protecting such devices against induced charge damage during fabrication.


BACKGROUND OF THE INVENTION

Non-volatile memory (NVM) cells generally comprise transistors with programmable threshold voltages. For example, a floating gate transistor or a split gate transistor has a threshold voltage (Vt) that is programmed or erased by charging or discharging a floating gate located between a control gate and a channel in the transistor. Data is written in such memory cells by charging or discharging the floating gates of the memory cells to achieve threshold voltages corresponding to the data.


The act of programming the cell involves charging the floating gate with electrons, which increases the threshold voltage Vt. The act of erasing the cell involves removing electrons from the floating gate, which decreases the threshold voltage Vt.


One type of non-volatile cell is a nitride, read only memory (NROM) cell. Unlike a floating gate cell, the NROM cell has two separated and separately chargeable areas. Each chargeable area may define one bit or more. The separately chargeable areas are found within a nitride layer formed in an oxide-nitride-oxide (ONO) stack underneath the gate. When programming a bit, channel hot electrons are injected into the nitride layer. This is generally accomplished by the application of a positive gate voltage and positive drain voltage, the magnitude and duration of which are determined by different factors related to the amount of programming required.


However, during device fabrication, unintentional tunneling currents may be induced, resulting with cells charging, higher Vt and larger Vt variations between cells across the wafer. Such conditions may adversely impact device production.


After a stacked gate is formed, additional processing steps are performed to finish fabrication. For example, additional masking and etching may be required to form additional semiconductor structures or to deposit metal or polysilicon interconnections on a semiconductor device. When a device is exposed to plasma processing, e.g., plasma etching, electrical charges may accumulate on the interconnections due to a phenomenon referred to as the “antenna effect”. The accumulated charge on the interconnections creates a voltage difference across the ONO layer of a NROM memory cell. A sufficiently large voltage difference may cause tunneling current to flow through the ONO layer introducing a programming effect and altering the threshold voltage of the memory cell.


Methods have been described in the prior art for protecting memory cells from charging induced during device fabrication by limiting the accumulation of charge on device interconnections during fabrication and by dissipating any accumulated charge in a safe manner. For example, U.S. Pat. No. 6,869,844 to Liu, et al., assigned to Advanced Micro Device, Inc., describes a protective semiconductor structure for limiting and dissipating accumulated charge from the conductive interconnections in an NROM memory array. Protective structures are connected to the device interconnections to provide a discharge path for the accumulated charge without adversely affecting the normal operation of the semiconductor device. The discharge path is provided by a thin insulating layer between a conductive interconnection and the device substrate. The thin insulating layer is formed over a p-well formed in an n-well in the semiconductor substrate. The interconnection to be protected is formed so that a portion of the interconnection overlies the thin insulating layer. The structure forms a capacitor and back-to-back diodes connected in series between the protected interconnection and the substrate, providing a discharge path for built up charge on the interconnection.


Another example is U.S. patent application Ser. No. 20040007730 to Chou et al., assigned to Macronix of Taiwan, which describes a protection device for protecting against plasma and other related charge damages. The protection device basically includes back-to-back diodes and protection circuitry per word line. The protection device may be understood by referring to FIGS. 1 and 2. (FIG. 1 corresponds to FIG. 5 of U.S. patent application Ser. No. 20040007730.)


Reference is first made to FIG. 1. The structure of the protection device includes a semiconductor substrate 20 (PW) having an intrinsic p-type doping. A first deep n-type well 21 (NWD) and a second deep n-type well 22 (NWD) are formed by diffusion of n-type dopants into the substrate 20. A PMOS transistor 12 has a p-type source 23 and a p-type drain 24 formed within the first deep n-type well 21. An. n-type contact 25 is formed on the surface of the first deep n-type well 21. The p-type contact region 26 is formed in the surface of the substrate 20 (PW), preferably adjacent to the first deep n-type well 21. A gate 27 is formed over an insulator (not shown) between the source 23 and the drain 24 over the channel region. The first deep n-type well 21 acts as the semiconductor bulk within which the channel region is formed. The gate 27 is coupled to the first deep n-type well 21 via the contact 25. The source 23 is coupled to the substrate 20 via the contact 26, and to a ground reference. The drain 24 is coupled via a conductive line to a node 30 to be protected in integrated circuitry on the device. The gate 27 is also coupled to a circuit on the device which supplies the highest voltage VPCP11 available during operation. The voltage on the gate 27 is at least as high as the highest operating voltage applied to the node 30 during operation, and is high enough to bias the PMOS transistor 12 in a normally off position during operation of the device. During manufacture, node 30 is left floating.


Within the second deep n-type well 22, a deep p-type well 31 (PAW) is formed. An NMOS transistor 14 (also seen in FIG. 1) has a source 32 and a drain 33 formed within the p-type well 31 (PWI). A p-type contact 34 is formed by diffusion in the surface of the p-type well 31. Also, a p-type contact 35 is formed in the surface of the substrate 20, preferably adjacent to the second deep n-type well 22. A gate 36 is formed over an insulator (not shown) over the channel region between the source 32 and a drain 33 of the NMOS transistor 14. The gate 36 is coupled to the contact 34, so that the gate of the NMOS transistor 14 is coupled to the semiconductor bulk in which the channel of the NMOS transistor 14 is formed. The source 32 of the NMOS transistor 14 is coupled to the terminal 35 and to a ground reference. The drain 33 of the NMOS transistor 14 is coupled to the node 30. A contact 37 is formed in the surface of the second deep n-type well 22. The contact 37 is coupled to the highest voltage VPCP11 generated on that chip during operation, or to another voltage level sufficient to maintain isolation of the p-type well 31. The gate 36 of the NMOS transistor 14 is coupled to a circuit which supplies the lowest voltage NVPP provided on the chip, at least as low as the lowest voltage applied at the node 30 during operation, or to a circuit which provides a voltage low enough to turn off the NMOS transistor 14 during operation of the circuitry. During manufacturing, the gate 36 is left floating.


The gate insulator between the gate and channel of the NMOS transistor 14 and of the PMOS transistor 12 should be strong enough to withstand the high or low voltages applied during operation of the device. For example, the gate insulator comprises a relatively thick oxide, compared to gate oxide thicknesses for logic transistors, in one embodiment of the device.


As mentioned before, the protection device of U.S. patent application Ser. No. 20040007730 provides protection per word line. During positive charging, the PMOS transistor 12 turns on and clamps the high voltage. During negative charging, the NMOS transistor 14 turns on and clamps the high voltage. During product operation, the bipolar transistors PMOS and NMOS transistors 12 and 14 are turned off, due to voltages applied to the terminals VPCP11 and NVPP. For correct operation as a fuse one needs short channel devices (high β of the bipolar transistors). Careful optimization should be done on the Ld parameter, to provide the best tradeoff between efficient clamping and leakage at the off state.


Reference is now made to FIG. 2. In order to implement the above prior art structure per word line, a dedicated connectivity for each word line to each dedicated transistor is required. The area penalty is substantial, and may range between 2-20%, pending on various factors, e.g., the physical sector size (number and length of word lines) and design rules.


SUMMARY OF THE INVENTION

There is provided, in accordance with an embodiment of the present invention a method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor T1 and an NMOS transistor T4, the PMOS transistors T1 sharing a common deep N well and the NMOS transistors T4 associated with a P well, wherein during positive charging, the PMOS transistors T1 shunt leakage current to ground, and during negative charging, the NMOS transistors T4 shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the positive and negative voltage clamping devices direct leakage current (for example, from the PMOS and NMOS transistors T1 and T4, respectively) to ground.


In accordance with an embodiment of the present invention, the positive voltage clamping device includes a PMOS transistor T2, and the negative voltage clamping device includes a NMOS transistor T5.


Further in accordance with an embodiment of the present invention, the voltage clamping devices and method include providing antenna structure and at least one access transistor for protection during top-level metal formation. The antenna structure may include a dummy word line connected to a word line driver. The at least one access transistor may be a PMOS transistor T3 for positive charging clamping structure wherein, the at least one access transistor may be an NMOS transistor T6 for negative charging clamping device. All the P wells may be connected together with a first metal layer or a poly layer or be a common P well.





BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which:



FIG. 1 is a simplified diagram of prior art transistor circuitry for protecting memory cells from damage induced during device fabrication protection;



FIG. 2 is a simplified diagram of a physical sector of the prior art showing the relatively large area needed to implement the prior art solution of two bipolar transistors for each word line;



FIG. 3 is a simplified diagram of circuitry for protecting memory cells from damage induced during device fabrication protection, constructed and operative in accordance with an embodiment of the present invention, the circuitry providing global protection for all word lines;



FIG. 4 is a simplified circuit schematic of the protection circuitry of FIG. 3, showing the negative charging protection circuitry; and



FIG. 5 is a simplified circuit schematic of the protection circuitry of FIG. 3, showing the positive charging protection circuitry.





DETAILED DESCRIPTION OF EMBODIMENTS

Reference is now made to FIG. 3, which illustrates circuitry for protecting memory cells from damage induced during device fabrication protection, constructed and operative in accordance with an embodiment of the present invention. Unlike the prior art, this circuitry provides global protection for all word lines and saves significant die area.


The circuitry shown includes word lines connected to an X-decoder, which serves as the word line driver. Part of the X-decoder region (word line driver) is shown in FIG. 3 comprising pairs of transistors—PMOS transistors T1 (which serve as back-to-back diodes when combined with additional N+ region overlapping the NWELL region) and NMOS transistors T4. The PMOS transistors T1 are fabricated on a common deep N well 40. The NMOS transistors T42 are fabricated on P well tabs 38. The word lines are connected to the drains (active regions) of T1 and T4. A plurality of word line drivers share the deep N well 40 which has an addition of an n+ active region 42. The circuitry described so far is back-to-back diode protection circuitry that exists in the art.


The present invention utilizes the above-mentioned X-decoder circuitry and adds global protection circuitry for all word lines. In accordance with an embodiment of the present invention, this may be accomplished by providing an N+ tap for the common N well of the PMOS transistors T1 and connecting the N+ tap to a positive voltage clamping device, (for example PMOS transistors T2 and T3 shown in FIG. 5) external to the X-decoder structure. Connections may be done using poly interconnect or first metal only. The P well tabs 38 of all the NMOS T4 transistors may be connected together with either P well connections 44 or with a first metal layer or poly, and a P+ tap common to the P wells may be connected to a negative voltage clamping device, (for example, a NMOS transistors T5 and T6 shown in FIG. 4) external to the X-decoder protection structure.


Thus, the word lines to the N+/P+ active regions contact in the X-decoder region are globally connected to negative and positive voltage clamping devices) to provide negative and positive protection, respectively. During the process steps, the negative and positive voltage clamping devices may be used as fuses that direct the leakage from the NMOS and PMOS transistors T4 and T1, respectively, to the substrate. During normal operation of the product, applied voltages block this leakage path. Preferably, although not mandatory, connectivity should be realized using low level metal in order to provide protection for the process steps that follow.


Reference is now made to FIG. 4, which is a simplified circuit schematic of the NMOS protection circuitry of FIG. 3, showing the negative charging protection circuitry. At the left of the circuit diagram can be seen NMOS transistor T5 with its source connected to ground, its gate connected to its bulk, and its drain connected to the X-decoder P well. At the right of the circuit diagram can be seen an NMOS transistor T6 with its source connected to an input Vneg, its gate connected to a dummy word line 49 associated with word line driver 47, and its drain connected via a jumper M3 (highest metal level available) to the bulks and gate of NMOS transistor T5. There is a purposely disconnected line between T5 and T6, so that during fabrication transistor T6 does not come into play and the discharge path via T5 is not blocked. The highest metal level is used to connect this purposely disconnected line between T5 and T6 in order to allow access of voltage bias during operation mode to block the discharging path via T5. The word line driver associated with the dummy word line may be used to input a positive bias voltage in operation mode. If negative charging occurs during the manufacturing process, NMOS transistor T6 is off as the dummy WL is as well negatively charged, which means that the discharging path via NMOS transistors T5 is not blocked. Conversely, NMOS transistor T6 is on during operation, which means that the discharging path to ground via NMOS transistors T5 is blocked.


The connectivity to the core protection structure should preferably be formed in the highest metal layer since the discharging transistor T5 should be isolated from any other structures during the manufacturing process to assure that during negative charging the discharging path is open. However, during operation mode, negative voltages may be applied to the word lines, thus an access to T5 should be formed to allow blocking the discharging path via T5. To allow this, as mentioned before, the highest metal jumper is formed. However, forming this jumper may result in unintentional charging via transistor T6 that may block transistor T5 during the manufacturing steps that follow. To overcome this concern, the dummy word line is connected to the word line driver and serves as antenna structure for protection from charging via transistor T6 and the highest metal level jumper. Reference is now made to FIG. 5, which is a simplified circuit schematic of the protection circuitry of FIG. 3, showing the positive charging protection circuitry. At the left of the circuit diagram can be seen PMOS transistor T2 with its source connected to ground, its gate connected to its bulk, and its drain connected to the X-decoder N well. At the right of the circuit diagram can be seen a PMOS transistor T3 with its drain connected to an input Vpos, its gate connected to a word line driver 51 on a dummy word line 53, and its source connected via a jumper M3 to the bulks and gates of PMOS transistor T2. The word line driver associated with the dummy word line may be used to input a negative bias voltage to allow blocking the discharge path via T2 during operation mode. If positive charging occurs during the manufacturing process, PMOS transistor T3 is off as the dummy WL is as well positively charged, which means that any leakage is shunted to ground via PMOS transistors T2. Conversely, PMOS transistor T3 is on during operation, which means that the discharge path via PMOS transistors T2 is blocked.


Here also, the dummy word line connected to the word line driver serves as antenna structure for charging protection for the access path used in the highest metal level. The connectivity to the core protection structure should preferably be formed in the highest metal layer.


It is also appreciated that various features of the invention which are, for clarity, described in the contexts of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination.

Claims
  • 1. A method for protecting NROM devices from charge damage during process steps, the method comprising: providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor (T1) and an NMOS transistor (T4), the PMOS transistors (T1) sharing a common deep N well and the NMOS transistors (T4) connected to a P well, providing an N+ tap connected to said N well and connecting the N+ tap to a positive voltage clamping device; and connecting all the P wells together to a common P+ taps, connecting the P+ tap to a negative voltage clamping device; wherein during process steps, the negative and positive voltage clamping devices direct leakage current to a ground potential: providing antenna structure and at least one access transistor for protection during top-level metal formation, and wherein said antenna structure comprises a dummy word line connected to a word line driver.
  • 2. The method according to claim 1, wherein said negative voltage clamping device comprises a NMOS transistor (T5).
  • 3. The method according to claim 1, wherein said positive voltage clamping device comprises a PMOS transistor (T2).
  • 4. The method according to claim 1, further comprising providing at least one access transistor for access of voltage bias to the clamping devices during operation mode.
  • 5. The method according to claim 1, wherein for negative charging protection structure comprising NMOS transistors (T4) and (T5), the at least one access transistor is an NMOS transistor (T6).
  • 6. The method according to claim 1, wherein for positive charging protection structure comprising PMOS transistors (T1) and (T2), the at least one access transistor is a PMOS transistor (T3).
  • 7. The method according to claim 1, wherein all the P wells are connected together with a first metal layer.
  • 8. The method according to claim 1, wherein all the P wells are connected together with a poly layer.
  • 9. The method according to claim 1, wherein the P well is a common P well.
  • 10. Circuitry for protecting NROM devices from charge damage during process steps, the circuitry being used with existing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, an PMOS transistor (T1) and a NMOS transistor (T4), the PMOS transistors (T1) sharing a common deep N well and the NMOS transistors (T4) each connected to a P well, the circuitry comprising: an N+ tap connected to said N well and to a positive voltage clamping device, a common P+ tap that connects all the P wells together, the common P+ tap being connected to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground potential; providing antenna structure and at least one access transistor for protection during top-level metal formation, and wherein said antenna structure comprises a dummy word line connected to a word line driver.
  • 11. The circuitry according to claim 10, wherein said negative voltage clamping device comprises an NMOS transistor (T5).
  • 12. The method circuitry according to claim 10, wherein said positive voltage clamping device comprises a PMOS transistor (T2).
  • 13. The method circuitry according to claim 10, further comprising providing at least one access transistor for access of voltage bias to the clamping devices during operation mode.
RELATED APPLICATIONS

This application asserts priority of provisional application Ser. No. 60/585,088 filed Jul. 6, 2004.

US Referenced Citations (568)
Number Name Date Kind
3881180 Gosney, Jr. Apr 1975 A
3895360 Cricchi et al. Jul 1975 A
3952325 Beale et al. Apr 1976 A
4016588 Ohya et al. Apr 1977 A
4017888 Christie et al. Apr 1977 A
4145703 Blanchard et al. Mar 1979 A
4151021 McElroy Apr 1979 A
4173766 Hayes Nov 1979 A
4173791 Bell Nov 1979 A
4247861 Hsu et al. Jan 1981 A
4257832 Schwabe et al. Mar 1981 A
4281397 Neal et al. Jul 1981 A
4306353 Jacobs et al. Dec 1981 A
4342102 Puar Jul 1982 A
4342149 Jacobs et al. Aug 1982 A
4360900 Bate Nov 1982 A
4373248 McElroy Feb 1983 A
4380057 Kotecha et al. Apr 1983 A
4388705 Sheppard Jun 1983 A
4389705 Sheppard Jun 1983 A
4404747 Collins Sep 1983 A
4435786 Tickle Mar 1984 A
4448400 Harari May 1984 A
4471373 Shimizu et al. Sep 1984 A
4494016 Ransom et al. Jan 1985 A
4507673 Aoyama Mar 1985 A
4521796 Rajkanan et al. Jun 1985 A
4527257 Cricchi Jul 1985 A
4586163 Koike Apr 1986 A
4613956 Paterson et al. Sep 1986 A
4630085 Koyama Dec 1986 A
4663645 Komori et al. May 1987 A
4665426 Allen et al. May 1987 A
4667217 Janning May 1987 A
4672409 Takei et al. Jun 1987 A
4725984 Ip et al. Feb 1988 A
4733105 Shin et al. Mar 1988 A
4742491 Liang et al. May 1988 A
4758869 Eitan et al. Jul 1988 A
4760555 Gelsomini et al. Jul 1988 A
4761764 Watanabe Aug 1988 A
4769340 Chang et al. Sep 1988 A
4780424 Holler et al. Oct 1988 A
4839705 Tigelaar et al. Jun 1989 A
4847808 Kobatake Jul 1989 A
4857770 Partovi et al. Aug 1989 A
4870470 Bass, Jr. et al. Sep 1989 A
4888735 Lee et al. Dec 1989 A
4916671 Ichiguchi Apr 1990 A
4941028 Chen et al. Jul 1990 A
4961010 Davis Oct 1990 A
4992391 Wang Feb 1991 A
5021999 Kohda et al. Jun 1991 A
5027321 Park Jun 1991 A
5029063 Lingstaedt et al. Jul 1991 A
5042009 Kazerounian et al. Aug 1991 A
5075245 Woo et al. Dec 1991 A
5081371 Wong Jan 1992 A
5086325 Schumann et al. Feb 1992 A
5094968 Schumann et al. Mar 1992 A
5104819 Freiberger et al. Apr 1992 A
5117389 Yiu May 1992 A
5120672 Mitchell et al. Jun 1992 A
5142495 Canepa Aug 1992 A
5142496 Van Buskirk Aug 1992 A
5159570 Mitchell et al. Oct 1992 A
5168334 Mitchell et al. Dec 1992 A
5172338 Mehrotra et al. Dec 1992 A
5175120 Lee Dec 1992 A
5204835 Eitan Apr 1993 A
5214303 Aoki May 1993 A
5237213 Tanoi Aug 1993 A
5241497 Komarek Aug 1993 A
5260593 Lee Nov 1993 A
5268861 Hotta Dec 1993 A
5276646 Kim et al. Jan 1994 A
5280420 Rapp Jan 1994 A
5289412 Frary et al. Feb 1994 A
5293563 Ohta Mar 1994 A
5295092 Hotta et al. Mar 1994 A
5295108 Higa Mar 1994 A
5305262 Yoneda Apr 1994 A
5311049 Tsuruta May 1994 A
5315541 Harari et al. May 1994 A
5324675 Hayabuchi Jun 1994 A
5334555 Sugiyama et al. Aug 1994 A
5335198 Van Buskirk et al. Aug 1994 A
5338954 Shimoji Aug 1994 A
5345425 Shikatani Sep 1994 A
5349221 Shimoji Sep 1994 A
5350710 Hong et al. Sep 1994 A
5352620 Komori et al. Oct 1994 A
5357134 Shimoji Oct 1994 A
5359554 Odake et al. Oct 1994 A
5361343 Kosonocky et al. Nov 1994 A
5366915 Kodama Nov 1994 A
5375094 Naruke Dec 1994 A
5381374 Shiraishi et al. Jan 1995 A
5393701 Ko et al. Feb 1995 A
5394355 Uramoto et al. Feb 1995 A
5399891 Yiu et al. Mar 1995 A
5400286 Chu et al. Mar 1995 A
5402374 Tsuruta et al. Mar 1995 A
5412601 Sawada et al. May 1995 A
5414693 Ma et al. May 1995 A
5418176 Yang et al. May 1995 A
5418743 Tomioka et al. May 1995 A
5422844 Wolstenholme et al. Jun 1995 A
5424567 Chen Jun 1995 A
5424978 Wada et al. Jun 1995 A
5426605 Van Berkel et al. Jun 1995 A
5434825 Harari et al. Jul 1995 A
5436478 Bergemont et al. Jul 1995 A
5436481 Egawa et al. Jul 1995 A
5440505 Fazio et al. Aug 1995 A
5450341 Sawada et al. Sep 1995 A
5450354 Sawada et al. Sep 1995 A
5455793 Amin et al. Oct 1995 A
5467308 Chang et al. Nov 1995 A
5477499 Van Buskirk et al. Dec 1995 A
5495440 Asakura Feb 1996 A
5496753 Sakurai et al. Mar 1996 A
5508968 Collins et al. Apr 1996 A
5518942 Shrivastava May 1996 A
5521870 Ishikawa May 1996 A
5523251 Hong Jun 1996 A
5523972 Rashid et al. Jun 1996 A
5530803 Chang et al. Jun 1996 A
5534804 Woo Jul 1996 A
5537358 Fong Jul 1996 A
5544116 Chao et al. Aug 1996 A
5553018 Wang et al. Sep 1996 A
5553030 Tedrow et al. Sep 1996 A
5557221 Taguchi et al. Sep 1996 A
5557570 Iwahashi Sep 1996 A
5559687 Nicollini et al. Sep 1996 A
5563823 Yiu et al. Oct 1996 A
5566125 Fazio et al. Oct 1996 A
5568085 Eitan et al. Oct 1996 A
5579199 Kawamura et al. Nov 1996 A
5581252 Thomas Dec 1996 A
5583808 Brahmbhatt Dec 1996 A
5590068 Bergemont Dec 1996 A
5590074 Akaogi et al. Dec 1996 A
5592417 Mirabel Jan 1997 A
5596527 Tomioka et al. Jan 1997 A
5599727 Hakozaki et al. Feb 1997 A
5600586 Lee et al. Feb 1997 A
5604804 Micali Feb 1997 A
5606523 Mirabel Feb 1997 A
5608679 Mi et al. Mar 1997 A
5612642 McClinyock Mar 1997 A
5617357 Haddad et al. Apr 1997 A
5623438 Guritz et al. Apr 1997 A
5627790 Golla et al. May 1997 A
5633603 Lee May 1997 A
5636288 Bonneville et al. Jun 1997 A
5644531 Kuo et al. Jul 1997 A
5654568 Nakao Aug 1997 A
5656513 Wang et al. Aug 1997 A
5657332 Auclair et al. Aug 1997 A
5661060 Gill et al. Aug 1997 A
5663907 Frayer et al. Sep 1997 A
5666365 Kostreski Sep 1997 A
5672959 Der Sep 1997 A
5675280 Nomura Oct 1997 A
5677867 Hazani Oct 1997 A
5677869 Fazio et al. Oct 1997 A
5683925 Irani et al. Nov 1997 A
5689459 Chang et al. Nov 1997 A
5694356 Wong et al. Dec 1997 A
5696929 Hasbun et al. Dec 1997 A
5708608 Park et al. Jan 1998 A
5712814 Fratin et al. Jan 1998 A
5712815 Bill et al. Jan 1998 A
5715193 Norman Feb 1998 A
5717581 Canclini Feb 1998 A
5717632 Richart et al. Feb 1998 A
5717635 Akatsu Feb 1998 A
5721781 Deo et al. Feb 1998 A
5726946 Yamagata et al. Mar 1998 A
5748534 Dunlap et al. May 1998 A
5751037 Aozasa et al. May 1998 A
5751637 Chen et al. May 1998 A
5754475 Bill et al. May 1998 A
5760445 Diaz Jun 1998 A
5760634 Fu Jun 1998 A
5768192 Eitan Jun 1998 A
5768193 Lee et al. Jun 1998 A
5771197 Kim Jun 1998 A
5774395 Richart et al. Jun 1998 A
5777919 Chi-Yung et al. Jul 1998 A
5781476 Seki et al. Jul 1998 A
5781478 Takeuchi et al. Jul 1998 A
5783934 Tran Jul 1998 A
5784314 Sali et al. Jul 1998 A
5787036 Okazawa Jul 1998 A
5793079 Georgescu et al. Aug 1998 A
5801076 Ghneim et al. Sep 1998 A
5805500 Campardo et al. Sep 1998 A
5808506 Tran Sep 1998 A
5812449 Song Sep 1998 A
5812456 Hull et al. Sep 1998 A
5812457 Arase Sep 1998 A
5815435 Van Tran Sep 1998 A
5822256 Bauer et al. Oct 1998 A
5825683 Chang et al. Oct 1998 A
5825686 Schmitt-Landsiedel et al. Oct 1998 A
5828601 Hollmer et al. Oct 1998 A
5834851 Ikeda et al. Nov 1998 A
5835935 Estakhri et al. Nov 1998 A
5836772 Chang et al. Nov 1998 A
5841700 Chang Nov 1998 A
5847441 Cutter et al. Dec 1998 A
5861771 Matsuda et al. Jan 1999 A
5862076 Eitan Jan 1999 A
5864164 Wen Jan 1999 A
5867429 Chen et al. Feb 1999 A
5870334 Hemink et al. Feb 1999 A
5870335 Khan et al. Feb 1999 A
5872848 Romney et al. Feb 1999 A
5875128 Ishizuka et al. Feb 1999 A
5877537 Aoki Mar 1999 A
5880620 Gitlin et al. Mar 1999 A
5886927 Takeuchi Mar 1999 A
RE36179 Shimoda Apr 1999 E
5892710 Fazio et al. Apr 1999 A
5903031 Yamada et al. May 1999 A
5910924 Tanaka et al. Jun 1999 A
5920503 Lee et al. Jul 1999 A
5920507 Takeuchi et al. Jul 1999 A
5926409 Engh et al. Jul 1999 A
5930195 Komatsu et al. Jul 1999 A
5933366 Yoshikawa Aug 1999 A
5933367 Matsuo et al. Aug 1999 A
5936888 Sugawara Aug 1999 A
5940332 Artieri Aug 1999 A
5946258 Evertt et al. Aug 1999 A
5946558 Hsu Aug 1999 A
5949714 Hemink et al. Sep 1999 A
5949728 Liu et al. Sep 1999 A
5959311 Shih et al. Sep 1999 A
5963412 En Oct 1999 A
5963465 Eitan Oct 1999 A
5966603 Eitan Oct 1999 A
5969989 Iwahashi Oct 1999 A
5969993 Takeshima Oct 1999 A
5973373 Krautschneider et al. Oct 1999 A
5982666 Campardo Nov 1999 A
5986940 Atsumi et al. Nov 1999 A
5990526 Bez et al. Nov 1999 A
5991202 Derhacobian et al. Nov 1999 A
5999444 Fujiwara et al. Dec 1999 A
5999494 Holzrichter Dec 1999 A
6000006 Bruce et al. Dec 1999 A
6005423 Schultz Dec 1999 A
6011725 Eitan Jan 2000 A
6018186 Hsu Jan 2000 A
6020241 You et al. Feb 2000 A
6028324 Su et al. Feb 2000 A
6030871 Eitan Feb 2000 A
6034403 Wu Mar 2000 A
6034896 Ranaweera et al. Mar 2000 A
6037627 Kitamura et al. Mar 2000 A
6040610 Noguchi et al. Mar 2000 A
6044019 Cernea et al. Mar 2000 A
6044022 Nachumovsky Mar 2000 A
6063666 Chang et al. May 2000 A
6064226 Earl May 2000 A
6064251 Park May 2000 A
6064591 Takeuchi et al. May 2000 A
6074916 Cappelletti Jun 2000 A
6075402 Ghilardelli Jun 2000 A
6075724 Li et al. Jun 2000 A
6078518 Chevallier Jun 2000 A
6081456 Dadashev Jun 2000 A
6084794 Lu et al. Jul 2000 A
6091640 Kawahara et al. Jul 2000 A
6094095 Murray et al. Jul 2000 A
6097639 Choi et al. Aug 2000 A
6107862 Mukainakano et al. Aug 2000 A
6108240 Lavi et al. Aug 2000 A
6108241 Chevallier Aug 2000 A
6117714 Beatty Sep 2000 A
6118207 Ormerod et al. Sep 2000 A
6118692 Banks Sep 2000 A
6122198 Haddad et al. Sep 2000 A
6128226 Eitan et al. Oct 2000 A
6128227 Kim Oct 2000 A
6130572 Ghilardelli et al. Oct 2000 A
6130574 Bloch et al. Oct 2000 A
6133095 Eitan et al. Oct 2000 A
6134156 Eitan Oct 2000 A
6137718 Reisinger Oct 2000 A
6147904 Liron Nov 2000 A
6147906 Bill et al. Nov 2000 A
6150800 Kinoshita et al. Nov 2000 A
6154081 Pakkala et al. Nov 2000 A
6156149 Cheung et al. Dec 2000 A
6157242 Fukui Dec 2000 A
6157570 Nachumovsky Dec 2000 A
6163048 Hirose et al. Dec 2000 A
6163484 Uekubo Dec 2000 A
6169691 Pasotti et al. Jan 2001 B1
6175523 Yang et al. Jan 2001 B1
6181597 Nachumovsky Jan 2001 B1
6181605 Hollmer et al. Jan 2001 B1
6185143 Perner et al. Feb 2001 B1
6188211 Rincon-Mora et al. Feb 2001 B1
6190966 Ngo et al. Feb 2001 B1
6192445 Rezvani Feb 2001 B1
6195196 Kimura et al. Feb 2001 B1
6198342 Kawai Mar 2001 B1
6201282 Eitan Mar 2001 B1
6201737 Hollmer et al. Mar 2001 B1
6205055 Parker Mar 2001 B1
6205056 Pan et al. Mar 2001 B1
6205059 Gutala et al. Mar 2001 B1
6208200 Arakawa Mar 2001 B1
6208557 Bergemont et al. Mar 2001 B1
6214666 Mehta Apr 2001 B1
6215148 Eitan Apr 2001 B1
6215697 Lu et al. Apr 2001 B1
6215702 Derhacobian et al. Apr 2001 B1
6218695 Nachumovsky Apr 2001 B1
6219277 Devin et al. Apr 2001 B1
6219290 Chang et al. Apr 2001 B1
6222762 Guterman et al. Apr 2001 B1
6222768 Hollmer et al. Apr 2001 B1
6233180 Eitan et al. May 2001 B1
6240032 Fukumoto May 2001 B1
6240040 Akaogi et al. May 2001 B1
6246555 Tham Jun 2001 B1
6252442 Malherbe Jun 2001 B1
6252799 Liu et al. Jun 2001 B1
6256231 Lavi et al. Jul 2001 B1
6261904 Pham et al. Jul 2001 B1
6265268 Halliyal et al. Jul 2001 B1
6266281 Derhacobian et al. Jul 2001 B1
6272047 Mihnea et al. Aug 2001 B1
6275414 Randolph et al. Aug 2001 B1
6281545 Liang et al. Aug 2001 B1
6282133 Nakagawa et al. Aug 2001 B1
6282145 Tran et al. Aug 2001 B1
6285246 Basu Sep 2001 B1
6285574 Eitan Sep 2001 B1
6285589 Kajitani Sep 2001 B1
6285614 Mulatti et al. Sep 2001 B1
6292394 Cohen et al. Sep 2001 B1
6297096 Boaz Oct 2001 B1
6297143 Foote et al. Oct 2001 B1
6297974 Ganesan et al. Oct 2001 B1
6304485 Harari et al. Oct 2001 B1
6307784 Hamilton et al. Oct 2001 B1
6307807 Sakui et al. Oct 2001 B1
6308485 Blumenthal Oct 2001 B1
6320786 Chang et al. Nov 2001 B1
6324094 Chevallier Nov 2001 B1
6326265 Liu et al. Dec 2001 B1
6330192 Ohba et al. Dec 2001 B1
6331950 Kuo et al. Dec 2001 B1
6335874 Eitan Jan 2002 B1
6335990 Chen et al. Jan 2002 B1
6337502 Eitan et al. Jan 2002 B1
6339556 Watanabe Jan 2002 B1
6343033 Parker Jan 2002 B1
6344959 Milazzo Feb 2002 B1
6346442 Aloni et al. Feb 2002 B1
6348381 Jong Feb 2002 B1
6348711 Eitan Feb 2002 B1
6351415 Kushnarenko Feb 2002 B1
6353356 Liu Mar 2002 B1
6353554 Banks Mar 2002 B1
6353555 Jeong Mar 2002 B1
6356062 Elmhurst et al. Mar 2002 B1
6356469 Roohparvar et al. Mar 2002 B1
6359501 Lin et al. Mar 2002 B2
6374337 Estakhri Apr 2002 B1
6385086 Mihara et al. May 2002 B1
6396741 Bloom et al. May 2002 B1
6400209 Matsuyama et al. Jun 2002 B1
6400607 Pasotti et al. Jun 2002 B1
6407537 Antheunis Jun 2002 B2
6410388 Kluth et al. Jun 2002 B1
6417081 Thurgate Jul 2002 B1
6418506 Pashley et al. Jul 2002 B1
6426898 Mihnea et al. Jul 2002 B1
6429063 Eitan Aug 2002 B1
6433624 Grossnikle et al. Aug 2002 B1
6436766 Rangarajan et al. Aug 2002 B1
6436768 Yang et al. Aug 2002 B1
6438031 Fastow Aug 2002 B1
6438035 Yamamoto et al. Aug 2002 B2
6440797 Wu et al. Aug 2002 B1
6442074 Hamilton et al. Aug 2002 B1
6445030 Wu et al. Sep 2002 B1
6449188 Fastow Sep 2002 B1
6449190 Bill Sep 2002 B1
6452438 Li Sep 2002 B1
6455896 Chou et al. Sep 2002 B1
6456528 Chen Sep 2002 B1
6456533 Hamilton et al. Sep 2002 B1
6458656 Park et al. Oct 2002 B1
6458677 Hopper et al. Oct 2002 B1
6469929 Kushnarenko et al. Oct 2002 B1
6469935 Hayashi Oct 2002 B2
6472706 Widdershoven et al. Oct 2002 B2
6477085 Kuo Nov 2002 B1
6490204 Bloom et al. Dec 2002 B2
6496414 Kasa et al. Dec 2002 B2
6504756 Gonzalez et al. Jan 2003 B2
6510082 Le et al. Jan 2003 B1
6512701 Hamilton et al. Jan 2003 B1
6519180 Tran et al. Feb 2003 B2
6519182 Derhacobian et al. Feb 2003 B1
6522585 Pasternak Feb 2003 B2
6525969 Kurihara et al. Feb 2003 B1
6528390 Komori et al. Mar 2003 B2
6529412 Chen et al. Mar 2003 B1
6532173 Lioka et al. Mar 2003 B2
6535020 Yin Mar 2003 B1
6535434 Maayan et al. Mar 2003 B2
6537881 Rangarjan et al. Mar 2003 B1
6538270 Randolph et al. Mar 2003 B1
6541816 Ramsbey et al. Apr 2003 B2
6552387 Eitan Apr 2003 B1
6555436 Ramsbey et al. Apr 2003 B2
6559500 Torii May 2003 B2
6562683 Wang et al. May 2003 B1
6566194 Ramsbey et al. May 2003 B1
6566699 Eitan May 2003 B2
6567303 Hamilton et al. May 2003 B1
6567312 Torii et al. May 2003 B1
6570211 He et al. May 2003 B1
6574139 Kurihara Jun 2003 B2
6577514 Shor et al. Jun 2003 B2
6577532 Chevallier Jun 2003 B1
6577547 Ukon Jun 2003 B2
6583005 Hashimoto et al. Jun 2003 B2
6583479 Fastow et al. Jun 2003 B1
6584017 Maayan et al. Jun 2003 B2
6590811 Hamilton et al. Jul 2003 B1
6593606 Randolph et al. Jul 2003 B1
6594181 Yamada Jul 2003 B1
6608526 Sauer Aug 2003 B1
6608905 Muza et al. Aug 2003 B1
6614052 Zhang Sep 2003 B1
6614295 Tsuchi Sep 2003 B2
6614686 Kawamura Sep 2003 B1
6614692 Maayan et al. Sep 2003 B2
6617179 Kim Sep 2003 B1
6617215 Halliyal et al. Sep 2003 B1
6618290 Wang et al. Sep 2003 B1
6624672 Confaloneri et al. Sep 2003 B2
6627555 Eitan et al. Sep 2003 B2
6630384 Sun et al. Oct 2003 B1
6633496 Maayan et al. Oct 2003 B2
6633499 Eitan et al. Oct 2003 B1
6633956 Mitani Oct 2003 B1
6636440 Maayan et al. Oct 2003 B2
6639271 Zheng et al. Oct 2003 B1
6639837 Takano et al. Oct 2003 B2
6639844 Liu et al. Oct 2003 B1
6639849 Takahashi et al. Oct 2003 B2
6642148 Ghandehari et al. Nov 2003 B1
6642573 Halliyal et al. Nov 2003 B1
6642586 Takahashi Nov 2003 B2
6643170 Huang et al. Nov 2003 B2
6643177 Le et al. Nov 2003 B1
6643178 Kurihara Nov 2003 B2
6643181 Sofer et al. Nov 2003 B2
6645801 Ramsbey et al. Nov 2003 B1
6649972 Eitan Nov 2003 B2
6650568 Iijima Nov 2003 B2
6653190 Yang et al. Nov 2003 B1
6653191 Yang et al. Nov 2003 B1
6654296 Jang et al. Nov 2003 B2
6664588 Eitan Dec 2003 B2
6665769 Cohen et al. Dec 2003 B2
6670241 Kamal et al. Dec 2003 B1
6670669 Kawamura Dec 2003 B1
6674138 Halliyal et al. Jan 2004 B1
6677805 Shor et al. Jan 2004 B2
6680509 Wu et al. Jan 2004 B1
6686242 Willer et al. Feb 2004 B2
6690602 Le et al. Feb 2004 B1
6693483 Deml et al. Feb 2004 B2
6700818 Shappir et al. Mar 2004 B2
6717207 Kato Apr 2004 B2
6723518 Papsidero et al. Apr 2004 B2
6731542 Le et al. May 2004 B1
6738289 Gongwer et al. May 2004 B2
6744692 Shiota et al. Jun 2004 B2
6765259 Kim Jul 2004 B2
6768165 Eitan Jul 2004 B1
6781876 Forbes et al. Aug 2004 B2
6788579 Gregori et al. Sep 2004 B2
6791396 Shor et al. Sep 2004 B2
6794249 Palm et al. Sep 2004 B2
6794280 Chang Sep 2004 B2
6818956 Kuo et al. Nov 2004 B2
6829172 Bloom et al. Dec 2004 B2
6831872 Matsuoka Dec 2004 B2
6836431 Chang Dec 2004 B2
6859028 Toner Feb 2005 B2
6869844 Liu et al. Mar 2005 B1
6870772 Nitta et al. Mar 2005 B1
6871258 Micheloni et al. Mar 2005 B2
6885585 Maayan et al. Apr 2005 B2
6885590 Zheng et al. Apr 2005 B1
6906357 Vashchenko et al. Jun 2005 B1
6912160 Yamada Jun 2005 B2
6917544 Maayan et al. Jul 2005 B2
6928001 Avni et al. Aug 2005 B2
6937523 Eshel Aug 2005 B2
6967872 Quader et al. Nov 2005 B2
6996692 Kuono Feb 2006 B2
7079420 Shappir et al. Jul 2006 B2
20010006477 Banks Jul 2001 A1
20020004878 Norman Jan 2002 A1
20020004921 Muranaka et al. Jan 2002 A1
20020064911 Eitan May 2002 A1
20020132436 Eliyahu et al. Sep 2002 A1
20020140109 Keshavarzi et al. Oct 2002 A1
20020145465 Shor et al. Oct 2002 A1
20020191465 Maayan et al. Dec 2002 A1
20020199065 Subramoney et al. Dec 2002 A1
20030001213 Lai Jan 2003 A1
20030021155 Yachareni et al. Jan 2003 A1
20030072192 Bloom et al. Apr 2003 A1
20030076710 Sofer et al. Apr 2003 A1
20030117841 Yamashita Jun 2003 A1
20030131186 Buhr Jul 2003 A1
20030134476 Roizin et al. Jul 2003 A1
20030142544 Maayan et al. Jul 2003 A1
20030145176 Dvir et al. Jul 2003 A1
20030145188 Cohen et al. Jul 2003 A1
20030155659 Verma et al. Aug 2003 A1
20030190786 Ramsbey et al. Oct 2003 A1
20030197221 Shinozaki et al. Oct 2003 A1
20030202411 Yamada Oct 2003 A1
20030206435 Takahashi Nov 2003 A1
20030208663 Van Buskirk et al. Nov 2003 A1
20030209767 Takahashi et al. Nov 2003 A1
20030214844 Iijima Nov 2003 A1
20030218207 Hashimoto et al. Nov 2003 A1
20030218913 Le et al. Nov 2003 A1
20030222303 Fukuda et al. Dec 2003 A1
20030227796 Miki et al. Dec 2003 A1
20040007730 Chou et al. Jan 2004 A1
20040012993 Kurihara Jan 2004 A1
20040013000 Torii Jan 2004 A1
20040014280 Willer et al. Jan 2004 A1
20040014290 Yang et al. Jan 2004 A1
20040021172 Zheng et al. Feb 2004 A1
20040027858 Takahashi et al. Feb 2004 A1
20040151034 Shor et al. Aug 2004 A1
20040153621 Polansky et al. Aug 2004 A1
20040157393 Hwang Aug 2004 A1
20040222437 Avni et al. Nov 2004 A1
20050117395 Maayan et al. Jun 2005 A1
20050117601 Anderson et al. Jun 2005 A1
20050140405 Do et al. Jun 2005 A1
20050213593 Anderson et al. Sep 2005 A1
20050232024 Atir et al. Oct 2005 A1
20060084219 Lusky et al. Apr 2006 A1
20060126382 Maayan et al. Jun 2006 A1
20060126983 Shappir et al. Jun 2006 A1
Foreign Referenced Citations (69)
Number Date Country
0 656 628 Jun 1995 EP
0751560 Jun 1995 EP
0693781 Jan 1996 EP
0 822 557 Feb 1998 EP
0 843 398 May 1998 EP
0580467 Sep 1998 EP
0461764 Jul 2000 EP
1 071 096 Jan 2001 EP
1073120 Jan 2001 EP
1 091 418 Apr 2001 EP
1126468 Aug 2001 EP
0740307 Dec 2001 EP
1164597 Dec 2001 EP
1 207 552 May 2002 EP
1 223 586 Jul 2002 EP
1 365 452 Nov 2003 EP
001217744 Mar 2004 EP
1297899 Nov 1972 GB
2157489 Mar 1985 GB
54-053929 Apr 1979 JP
60-200566 Oct 1985 JP
60201594 Oct 1985 JP
63-249375 Oct 1988 JP
3-285358 Dec 1991 JP
04-226071 Aug 1992 JP
04-291962 Oct 1992 JP
05021758 Jan 1993 JP
05-326893 Dec 1993 JP
06151833 May 1994 JP
06-232416 Aug 1994 JP
07193151 Jul 1995 JP
08-106791 Apr 1996 JP
08-297988 Nov 1996 JP
09-017981 Jan 1997 JP
09162314 Jun 1997 JP
10-106276 Apr 1998 JP
10 334676 Dec 1998 JP
11-162182 Jun 1999 JP
11-354758 Dec 1999 JP
2001-085646 Mar 2001 JP
2001-118392 Apr 2001 JP
2001-156189 Jun 2001 JP
2002-216488 Aug 2002 JP
3358663 Oct 2002 JP
WO 8100790 Mar 1981 WO
WO 9615553 May 1996 WO
WO 9625741 Aug 1996 WO
WO 9803977 Jan 1998 WO
WO 9931670 Jun 1999 WO
WO 9957728 Nov 1999 WO
WO 0046808 Aug 2000 WO
WO 0165566 Sep 2001 WO
WO 0165567 Sep 2001 WO
WO 0184552 Nov 2001 WO
WO 0243073 May 2002 WO
WO 03032393 Apr 2003 WO
WO 03036651 May 2003 WO
WO 03054964 Jul 2003 WO
WO 03063167 Jul 2003 WO
WO 03063168 Jul 2003 WO
WO 03079370 Sep 2003 WO
WO 03079446 Sep 2003 WO
WO 03083916 Oct 2003 WO
WO 03088258 Oct 2003 WO
WO 03088259 Oct 2003 WO
WO 03088260 Oct 2003 WO
WO 03088261 Oct 2003 WO
WO 03088353 Oct 2003 WO
WO 03100790 Dec 2003 WO
Related Publications (1)
Number Date Country
20060007612 A1 Jan 2006 US
Provisional Applications (1)
Number Date Country
60585088 Jul 2004 US