1. Technical Field
Embodiments of the invention relate to methods for coating a semiconductor substrate with a protective material to increase the mechanical strength and scratch resistance of the semiconductor substrate.
2. Description of Related Art
Semiconductor packages, especially packages which involve thin core or coreless substrate technologies, are prone to die defects on a back surface of a semiconductor die. In many instances, die defects may originate as scratches and dents introduced during assembly and test processes. Subsequently during reliability testing, these scratches and dents may develop into die cracks. Current practice requires semiconductor packages with cracked dies to be discarded which results in a yield loss. Especially in packages where thin substrate cores are used in combination with a thick semiconductor die, an unacceptably high die yield loss due to die cracks has been observed.
Embodiments of the invention are disclosed hereinafter with reference to the drawings, in which:
In the following description, numerous specific details are set forth in order to provide a thorough understanding of various illustrative embodiments of the invention. It will be understood, however, to one skilled in the art, that embodiments of the invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure pertinent aspects of embodiments being described. In the drawings, like reference numerals refer to same or similar functionalities or features throughout the various presented views.
The DLC material 202 suitable for use with embodiments of the invention may have sufficient hardness (e.g. Vickers hardness number of 1,000 to 3,000), low coefficient of friction (e.g. about 0.1), high chemical resistance (or is chemically inert), high thermal conductivity (e.g. 700 W/m.K to 110 W/m.K), high electrical resistivity (e.g. 106 to 1012 ohm-cm) and, high wear and scratch resistance. These properties are useful to protect a back surface 102 of a wafer 100 or a die 100A from defects by increasing mechanical strength, wear and scratch resistance of the wafer 100 or die 100A without adversely affecting the thermal performance of the final package product. The DLC material 202 may also have a low deposition temperature in order to preserve the integrity (e.g. physical shape and condition) of the wafer 100 or die 100A, and electronic functions of circuitry fabricated on a front surface of the wafer 100 or die 100A. For semiconductor wafers, deposition temperatures may be maintained at up to 350° C. For a semiconductor die mounted on a package substrate, deposition temperatures may be maintained between about 150° C. and about 260° C. depending on duration of the deposition process.
Various methods of depositing a DLC material 202 onto a back surface 102 of a semiconductor substrate (e.g. wafer 100) may be used. For example, ion beam sputter deposition (IBSD) methods may be employed. In another example, plasma-assisted chemical vapour deposition (PACVD) methods may be employed. Although the following paragraphs describe methods using IBSD and PACVD, it is to be appreciated that embodiments of the invention are not limited to these methods; other methods may be applicable with suitable modifications.
Reference is now made to
The ion beam sputter deposition apparatus (hereinafter “IBSD apparatus”) of
A first ion beam 310 emitted from the first ion source 306 is to energize a sputtering target which is to emit sputtered particles 314 containing a DLC material 202 to be deposited on a wafer 100 appropriately mounted on a substrate holder 316 in a path of the sputtered particles 314. A second ion beam 318 comprising energetic noble or reactive ions and emitted from the second ion source 308 may be directed at the deposited DLC material 202 on the wafer 100 to improve stability, density, dielectric and optical properties of the DLC coating.
In the embodiments of the invention, ion sources 306, 308 of “gridded” and/or “gridless” type may be used depending on required process conditions, maintenance costs, and deposition materials. Additionally, various ion beam sizes may be suitable depending on the size and geometry of the substrate. Further, a neutralizer (not shown) or an electron source may be provided to minimize charging effect of the ion beams 310, 318 on a wafer 100, sputtering targets and surfaces of the process chamber 300.
A flow sequence 500 for depositing a DLC material 202 on a wafer 100 using the IBSD apparatus of
Reference is now made to
The PACVD apparatus utilizes plasma to enhance chemical reaction rates of precursors containing a DLC material to be deposited on a semiconductor substrate (e.g. wafer 100). The PACVD apparatus comprises a process chamber 400 in which a vacuum environment may be formed. Two openings, namely a gas inlet 402 and an extraction outlet 404, are provided in the process chamber 400. The gas inlet 402 facilitates introduction of reaction gases into the process chamber 400 for creating plasma 406 containing a DLC material 202. Examples of the reaction gases include silane, oxygen, argon, ammonia and nitrogen. A combination of the reaction gases may be used in a PACVD apparatus depending on the material to be deposited. In one embodiment, the reaction gas includes a hydrocarbon-based precursor which enables the deposition of a DLC material 202 on a wafer 100. The extraction outlet 404 allows forming of a vacuum environment by drawing air and/or remnants of plasma 406 from the process chamber 400.
In the process chamber 400, a first electrode 410 and one or more second electrode 412 which is spaced apart from the first electrode 410 are provided. The first electrode 410 may be coupled to a substrate holder. A radio frequency (RF) signal may be applied to the first electrode 410 and the second electrodes 412 to generate an electric field therebetween. The electric field is to discharge a reaction gas in the process chamber 400 to produce plasma 406 containing a DLC material 202. The discharging may be by capacitive or inductive methods. Alternatively, a direct-current (DC) or alternating-current (AC) may alternatively be used to generate an electric field. Energy from the plasma 406 facilitates chemical reactions required for deposition of a DLC material on the wafer 100.
A flow sequence 600 for depositing a DLC material on a wafer 100 using the PACVD apparatus of
While the foregoing description does not include treating or preparing the semiconductor substrate prior to deposition of a DLC material 202, it is to be appreciated that such pre-treatment may be included in some embodiments if required. Possible pre-treatments includes, but are not limited to, wet-etching or plasma-etching of a back surface of a semiconductor substrate to remove oxide and/or modify surface roughness. Further, it is to be understood that embodiments of the invention are applicable, with suitable modifications, to a semiconductor substrate in various forms, e.g. a wafer (a bare wafer or a wafer mounted on a package substrate) and, one or more dice singulated from a wafer.
The thin layer of DLC material 202 is to protect a back surface 102 of a die 100A from defects, such as scratches and cracks. With the protection provided by a DLC material 202, improved mechanical strength and wear and scratch resistance are achieved in the die 100A and a semiconductor package containing the die 100A. This would greatly reduce die defects and die crack issues which may arise during assembly operations, and therefore improving yield. Because a DLC material 202 has high thermal conductivity and low junction temperature, coating a DLC material 202 on a wafer 100 or a die 100A would not adversely affect the thermal performance of the coated wafer or die.
Other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the invention. Furthermore, certain terminology has been used for the purposes of descriptive clarity, and not to limit the disclosed embodiments of the invention. The embodiments and features described above should be considered exemplary, with the invention being defined by the appended claims.