Claims
- 1. A data processing system comprising:a plurality of master devices; a plurality of node controllers, wherein a node controller organizes a subset of one or more of the plurality of master devices into a node; a plurality of memory subsystems; an address switch, wherein the address switch connects to each of the node controllers and to each of the memory subsystems, and wherein each of the memory subsystems connects to the address switch and to each of the node controllers; and a response combination block, wherein the response combination block connects to the address switch, to each master device, to each node controller, and to each memory subsystem in order to receive, from the plurality of master devices, the plurality of node controllers, the plurality of memory subsystems, and the address switch, command status signals and command response signals associated with commands issued by master devices and in order to generate command status signals and command response signals associated with commands issued by master devices.
- 2. A data processing system comprising:a plurality of master devices; a plurality of node controllers, wherein a node controller organizes a subset of one or more of the plurality of master devices into a node; a plurality of memory subsystems; an address switch, wherein the address switch connects to each of the node controllers and to each of the memory subsystems, and wherein each of the memory subsystems connects to the address switch and to each of the node controllers; and a response combination block, wherein the response combination block further comprises: broadcast signal receiving means for receiving a broadcast signal from the address switch indicating a broadcast of a command from the address switch to the master devices; and transaction source identifier receiving means for receiving a transaction source identifier from the address switch indicating a port of a node controller through which a master device transmitted a command.
- 3. A data processing system comprising:a plurality of master devices; a plurality of node controllers, wherein a node controller organizes a subset of one or more of the plurality of master devices into a node; a plurality of memory subsystems; an address switch, wherein the address switch connects to each of the node controllers and to each of the memory subsystems, and wherein each of the memory subsystems connects to the address switch and to each of the node controllers; and a response combination block, wherein a node controller comprises a plurality of master device ports, and wherein a master device bus connects a set of one or more master devices within a node to a master device port of the node controller, and wherein the response combination block further comprises, for each master device port of each node controller: a port-associated command status output receiving means for receiving a port-associated command status output signal of the master device bus of the master device port; a port-associated command response output receiving means for receiving a port-associated command response output signal of the master device bus of the master device port; a port-associated command status input transmitting means for transmitting a port-associated command status input signal for the master device bus of the master device port; a port-associated command response input transmitting means for transmitting a port-associated command response input signal for the master device bus of the master device port; a node-controller-associated command status output receiving means for receiving a node-controller-associated command status output signal from the node controller associated with the master device bus of the master device port; a node-controller-associated command response output receiving means for receiving a node-controller-associated command response output signal from the node controller associated with the master device bus of the master device port; a node-controller-associated command status input transmitting means for transmitting a node-controller-associated command status input signal to the node controller associated with the master device bus of the master device port; and a node-controller-associated command response input transmitting means for transmitting a node-controller-associated command response input signal to the node controller associated with the master device bus of the master device port.
- 4. The data processing system of claim 3 wherein the response combination block further comprises, for each memory subsystem of the plurality of memory subsystems:a memory-subsystem-associated command status output receiving means for receiving a memory-subsystem-associated command status output signal for the memory subsystem; a memory-subsystem-associated command status input transmitting means for transmitting a memory-subsystem-associated command status input signal to the memory subsystem; and a memory-subsystem-associated command response input transmitting means for transmitting a memory-subsystem-associated command response input signal to the memory subsystem.
- 5. The data processing system of claim 4 wherein the response combination block further comprises response combination means for logically combining one or more command status output signals and one or more command response output signals to generate one or more command status input signals and one or more command response input signals.
- 6. The data processing system of claim 5 wherein the response combination means further comprises:a first combination mode of operation based on whether a master device port is in a local cycle during which a master device issues a command on the master device port; a second combination mode of operation based on whether the data processing system is in a global cycle during which the address switch broadcasts a command.
- 7. The data processing system of claim 6 wherein the response combination means further comprises:a third combination mode of operation in which a master device port is in a local cycle during which a master device issues a command on the master device port and a remainder of the plurality of master device ports in the data processing system is in a global cycle during which the address switch broadcasts a command.
- 8. The data processing system of claim 6 wherein the response combination means generates, during the first combination mode of operation, a port-associated command status input signal, a port-associated command response input signal, a node-controller-associated command status input signal, and a node-controller-associated command response input signal in response to the receipt of a port-associated command status output signal, a port-associated command response output signal, a node-controller-associated command status output signal, and a node-controller-associated command response output signal.
- 9. The data processing system of claim 6 wherein the response combination means generates, during the second combination mode of operation, a port-associated command status input signal, a port-associated command response input signal, a node-controller-associated command status input signal, a node-controller-associated command response input signal, a memory-subsystem-associated command status input signal, and a memory-subsystem-associated command response input signal in response to the receipt of a port-associated command status output signal, a port-associated command response output signal, a node-controller-associated command status output signal, a node-controller-associated command response output signal, and a memory-subsystem-associated command status output signal.
- 10. A data processing system comprising:a plurality of master devices; a plurality of node controllers, wherein a node controller organizes a subset of one or more of the plurality of master devices into a node; a plurality of memory subsystems; an address switch, wherein the address switch connects to each of the node controllers and to each of the memory subsystems, and wherein each of the memory subsystems connects to the address switch and to each of the node controllers; and a response combination block, wherein the response combination block further comprises: command status signal receiving means for receiving a command status signal from each set of master devices connected to a master device port of a node controller, from each node controller for each of its master device ports, and from each memory subsystem; command response signal receiving means for receiving a command response signal from each set of master devices connected to a master device port of a node controller and from each node controller for each of its master device ports; command status signal generating means for generating a command status signal to each set of master devices connected to a master device port of a node controller, to each node controller for each of its master device ports, and to each memory subsystem; and command response signal generating means for generating a command response signal to each set of master devices connected to a port of a node controller and to each node controller for each of its ports.
- 11. A data processing system comprising:a plurality of master devices; a plurality of node controllers, wherein a node controller organizes a subset of one or more of the plurality of master devices into a node; a plurality of memory subsystems; an address switch, wherein the address switch connects to each of the node controllers and to each of the memory subsystems, and wherein each of the memory subsystems connects to the address switch and to each of the node controllers; and a response combination block that generates command status signals and command response signals in response to commands issued by the plurality of master devices, wherein the response combination block operates based on a plurality of cycle types.
- 12. The data processing system of claim 11 wherein the response combination block operates based on whether the data processing system is in a local cycle or a global cycle in which a master device issues a command during a local cycle and in which the address switch broadcasts a command during a global cycle.
- 13. The data processing system of claim 12 wherein the response combination block further comprises:command status signal receiving means for receiving, based on a command issued on a master device port during a local cycle, a pair of command status signals from the master device port of a node controller and from the node controller for the master device port; command response signal receiving means for receiving, based on the command issued on the master device port during the local cycle, a pair of command response signal from the master device port of the node controller and from the node controller for the master device port; command status signal generating means for generating, based on the command issued on the master device port during the local cycle, a pair of command status signals to the master device port of the node controller and to the node controller for the master device port; and command response signal generating means for generating, based on a command issued on the master device port during a local cycle, a pair of command response signals to the master device port of the node controller and to the node controller for the master device port.
- 14. The data processing system of claim 12 wherein the response combination block further comprises:command status signal receiving means for receiving, during a global cycle, a pair of command status signals from each set of master devices connected to a master device port of a node controller and from each node controller for each of its master device ports; command response signal receiving means for receiving, during the global cycle, a pair of command response signals from each set of master devices connected to a master device port of a node controller and from each node controller for each of its master device ports; command status signal generating means for generating, during the global cycle, a pair of command status signals to each set of master devices connected to a master device port of a node controller and to each node controller for each of its master device ports, except for a pair of command status signals to a set of master devices connected to a master device port of a node controller and to the node controller for the master device port corresponding to the master device port that issued the command; and command response signal generating means for generating, during the global cycle, a pair of command response signals to each set of master devices connected to a master device port of a node controller and to each node controller for each of its master device ports, except for a pair of command response signals to a set of master devices connected to a master device port of a node controller and to the node controller for the master device port corresponding to the master device port that issued the command.
- 15. The data processing system of claim 12 wherein the response combination block further comprises:command status signal combining means for combining command status signals on a per port per node controller basis; and command status response combining means for combining command response signals on a per port per node controller basis.
- 16. The data processing system of claim 11, wherein the plurality of cycle types includes a global cycle type and a local cycle type.
CROSS-REFERENCE TO RELATED APPLICATIONS
The present invention is related to the following applications entitled “METHOD AND APPARATUS FOR ACHIEVING CORRECT ORDER AMONG BUS MEMORY TRANSACTIONS IN A PHYSICALLY DISTRIBUTED SMP SYSTEM”, U.S. application Ser. No. 09/350,030, filed on Jul. 8, 1999; “METHOD AND APPARATUS USING A DISTRIBUTED SYSTEM STRUCTURE TO SUPPORT BUS-BASED CACHE-COHERENCE PROTOCOLS FOR SYMMETRIC MULTIPROCESSORS”, U.S. application Ser. No. 09/350,031, filed on Jul. 8, 1999; “METHOD AND SYSTEM FOR RESOLUTION OF TRANSACTION COLLISIONS TO ACHIEVE GLOBAL COHERENCE IN A DISTRIBUTED SYMMETRIC MULTIPROCESSOR SYSTEM”, U.S. application Ser. No. 09/392,833, filed on Sep. 9, 1999; “METHOD AND SYSTEM FOR IMPLEMENTING REMSTAT PROTOCOL UNDER INCLUSION AND NON-INCLUSION OF L1 DATA IN L2 CACHE TO PREVENT READ-READ DEADLOCK”, U.S. application Ser. No. 09/404,400, filed on Sep. 23, 1999; “METHOD AND SYSTEM FOR CONTROLLING DATA TRANSFERS WITH PHYSICAL SEPARATION OF DATA FUNCTIONALITY FROM ADDRESS AND CONTROL FUNCTIONALITY IN A DISTRIBUTED MULTI-BUS MULTIPROCESSOR SYSTEM”, U.S. application Ser. No. 09/404,280, filed on Sep. 23, 1999; “METHOD AND APPARATUS TO DISTRIBUTE INTERRUPTS TO MULTIPLE INTERRUPT HANDLERS IN A DISTRIBUTED SYMMETRIC MULTIPROCESSOR SYSTEM”, U.S. application Ser. No. 09/436,201, filed on Nov. 8, 1999; “METHOD AND APPARATUS TO ELLMINATE FAILED SNOOPS OF TRANSACTIONS CAUSED BY BUS TIMING CONFLICTS IN A DISTRIBUTED SYMMETRIC MULTIPROCESSOR SYSTEM”, U.S. application Ser. No. 09/436,203, filed on Nov. 8, 1999; “METHOD AND APPARATUS FOR TRANSACTION PACING TO REDUCE DESTRUCTIVE INTERFERENCE BETWEEN SUCCESSIVE TRANSACTIONS IN A DISTRIBUTED SYMMETRIC MULTIPROCESSOR SYSTEM”, U.S. application Ser. No. 09/436,204, filed on Nov. 8, 1999; “METHOD AND APPARATUS FOR INCREASED PERFORMANCE OF A PARKED DATA BUS IN THE NON-PARKED DIRECTION”, U.S. application Ser. No. 09/436,206, filed on Nov. 8, 1999; “METHOD AND APPARATUS FOR FAIR DATA BUS PARKING PROTOCOL WITHOUT DATA BUFFER RESERVATIONS AT THE RECEIVER”, U.S. application Ser. No. 09/436,202, filed on Nov. 8, 1999; “METHOD AND APPARATUS FOR AVOIDING DATA BUS GRANT STARVATION IN A NON-FAIR, PRIORITIZED ARBITER FOR A SPLIT BUS SYSTEM WITH INDEPENDENT ADDRESS AND DATA BUS GRANTS”, U.S. application Ser. No. 09/436,200, filed on Nov. 8, 1999; “METHOD AND APPARATUS FOR SYNCHRONIZING MULTIPLE BUS ARBITERS ON SEPARATE CHIPS TO GIVE SIMULTANEOUS GRANTS FOR THE PURPOSE OF BREAKING LIVELOCKS”, U.S. application Ser. No. 09/436,192, filed on Nov. 8, 1999; “METHOD AND APPARATUS FOR TRANSACTION TAG ASSIGNMENT AND MAINTENANCE IN A DISTRIBUTED SYMMETRIC MULTIPROCESSOR SYSTEM”, U.S. application Ser. No. 09/436,205, filed on Nov. 8, 1999; and “METHOD AND APPARATUS FOR DATA BUS LATENCY REDUCTION USING TRANSFER SIZE PREDICTION FOR SPLIT BUS DESIGNS ”, U.S. application Ser. No. 09/434,764, filed on Nov. 4, 1999; all of which are assigned to the same assignee.
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