Patent Application
20150235681
This application claims priority to Chinese Application No. 201410052592.1, filed on Feb. 14, 2014, which is incorporated herein by reference.
This application is directed, in general, to a data storage memory and, more specifically, to a memory read system and a method of reading a memory.
In dual port memory cells, read and write operations can be executed concurrently and therefore employ independent read and write bit lines that are controlled by corresponding separate read and write word lines. When the stored memory cell data represents a “TRUE” condition, a precharged voltage on the read bit line needs to be discharged in order to reflect this TRUE condition. A corresponding discharge time of the read bit line is affected by bit line capacitance and the discharge voltage level that is required to indicate the memory cell's TRUE storage condition. For longer discharge times, the reading speed of the memory cell can be relatively slow for large capacity memory arrays. This is due to read current capability, which is often limited in magnitude due to small memory cell areas. Additionally, larger discharge voltages typically require larger dynamic power expenditures. Therefore, improvements in these areas would prove beneficial to the art.
Embodiments of the present disclosure provide a memory read system and a method of reading a memory.
In one embodiment, the memory read system includes a memory column having a plurality of dual port memory cells that are controlled by separate read word lines and a read bit line structure organized into upper and lower read bit line portions. Additionally, the memory read system also includes a pseudo-differential memory read unit coupled to the read bit line structure, wherein the upper and lower read bit line portions respectively control corresponding upper and lower local bit lines to provide a global bit line for the memory column.
In another aspect, the method of reading a memory includes providing a memory column of dual port memory cells controlled by separate read word lines and organizing a read bit line structure for the memory column into upper and lower memory cell read bit line portions. The method also includes controlling corresponding upper and lower local read bit lines from the upper and lower memory cell read bit line portions during a read operation and controlling a global read bit line for the memory column from the upper and lower local read bit lines to provide a memory cell storage state during the read operation.
The foregoing has outlined preferred and alternative features of the present disclosure so that those skilled in the art may better understand the detailed description of the disclosure that follows. Additional features of the disclosure will be described hereinafter that form the subject of the claims of the disclosure. Those skilled in the art will appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present disclosure.
Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Embodiments of the present disclosure provide a pseudo-differential read capability for dual port memory cells (e.g., dual port static random access memory (SRAM) cells), which improves read speed and decreases dynamic power requirements by reducing a required read voltage swing. These attributes are especially beneficial as memory capacity increases.
In the illustrated embodiment, the memory column 105 includes a plurality of dual port memory cells that are controlled by separate read word lines (RWL<0> through RWL<127>), where only one of the separate read word lines is activated during a read operation. The upper and lower read bit line portions 110A, 110B constitute a read bit line structure for the memory column 105 that provides a memory cell storage condition for a selected read word line during a read operation. The read bit line structure provides for lower stray or intrinsic overall bit line capacitance thereby decreasing an overall read time for the memory column 105.
The pseudo-differential memory read unit 115 is coupled to the read bit line structure, as shown. The upper and lower read bit line portions 110A, 110B respectively control corresponding upper and lower local bit lines within the pseudo-differential memory read unit 115 to provide a global read bit line for the memory column 105.
The SRAMDP cell 200 also includes corresponding first and second write pass gate transistors N3 and N4 that are respectively connected between a write bit line WBL and the storage node Q and a complementary write bit line WBLB and the complementary storage node Q*. The first and second write pass gate transistors N3 and N4 are controlled by a write word line WWL.
The SRAMDP cell 200 additionally includes a read pass gate transistor PG that is connected between a read bit line RBL and an inverting transistor PD. The read pass gate transistor PG is controlled by a read word line RWL.
The SRAMDP cell 200 is representative of one of the memory cells in the memory column 105 of
Also included are control transistors P1 and P2, which are respectively used as read input devices for the upper and lower local bit lines LBLu, LBL1 and where their controlling gates are connected to upper (RBLu) and lower (RBL1) read bit line portions of a bit line structure (such as those previously discussed). Additionally included is a control transistor P3 that is employed to precharge the global bit line GBL to a supply voltage VDD, prior to a read operation.
Further included are transistors N1 and N2 that are employed as a reinforcing cross-coupling circuit between the upper and lower local bit lines LBLu, LBL1 to improve a noise margin of the global bit line GBL. Still further included are control transistors N3 and N4 that are employed to discharge the upper and lower local bit lines LBLu, LBL1 to ground potential outside of a read operation.
Yet further included are transistors N5 and N6 that perform as a wire NOR2 logic circuit and are employed to couple the upper and lower local bit lines LBLu, LBL1 to the global bit line GBL during a read operation. Correspondingly, the transistors N5 and N6 are employed to provide isolation of the upper and lower local bit lines LBLu, LBL1 from the global read bit line GBL outside of a read operation.
If the stored data of a corresponding memory cell represents a “FALSE” state (i.e., a logical “zero” condition), a voltage level of the upper (RBLu) and lower (RBL1) read bit line portions is maintained at a precharge voltage VDD and the READ DATA output reflects this FALSE state or zero condition. Otherwise, the READ DATA output will be changed to reflect a “TRUE” state or logical “one” condition of the corresponding memory cell.
Before a read operation begins (i.e., prior to time t0), the RWL waveform 405 indicates that a read word line RWL is in a LOW voltage state. Correspondingly, upper and lower read bit line portions RBLu, RBL1 of a bit line structure have been precharged to a precharge voltage VDD. The PCHG waveform 410 indicates that a precharge control signal PCHG is in a LOW voltage state, and the DISCHG waveform 415 indicates that a discharge control signal DISCHG is in a HIGH voltage state. Upper and lower local bit lines LBLu, LBL1 are discharged to a ground potential (control transistors N3, N4 are conducting and transistors N5, N6 are not conducting), and the global bit line GBL is precharged to a precharge voltage VDD. These conditions maintain the READ DATA output in a FALSE state, when not performing a read operation.
When the RWL waveform transitions to a HIGH voltage state at time t0, the read operation begins. The PCHG waveform 410 also transitions to a HIGH voltage state thereby deactivating the control transistor P3 and leaving the global bit line GBL charged to the precharge voltage VDD. The DISCHG waveform 415 transitions to a LOW voltage state thereby deactivating the control transistors N3, N4 and isolating the upper and lower local bit lines LBLu, LBL1. The precharge voltage VDD of the RBLu waveform 420 begins to discharge, which reflects a TRUE state for the memory cell being addressed for reading by the read word line RWL.
As this discharge continues, a threshold voltage Vt of the control transistor P1 is reached (at time t1) thereby causing it to conduct, which activates the transistor N5 and thereby pulls the global bit line GBL to ground potential. This global bit line state provides a TRUE state for the READ DATA waveform 425 indicating the TRUE state of the addressed memory cell. The read operation is concluded at time t2, and all of the waveforms return to their previous states before the read operation began.
Simulation results for embodiments of the present disclosure employing a 128 row random access memory indicates an 11 percent improvement in a worst case read speed over a traditional read scheme (411 picoseconds versus 460 picoseconds). Here, the worst case read speed is defined as the delay time from the rising edge of the read word line to the rising edge of the READ DATA output signal. Correspondingly, there is a 12 percent decrease in required RBLu discharge voltage (513 millivolts versus 584 millivolts), which translates to about a 12 percent dynamic power improvement.
In one embodiment, the upper and lower memory cell read bit line portions are initially precharged to a memory supply voltage level before a read operation. In another embodiment, the upper and lower local read bit lines are initially discharged before a read operation. Correspondingly, the discharge of the upper and lower local read bit lines isolates them from the global read bit line. In yet another embodiment, a voltage discharge from the initially precharged voltage level of one of the upper and lower memory cell read bit line portions controls a voltage discharge of the global bit line. In still another embodiment, a reinforcing cross-coupling between the upper and lower local read bit lines improves a global read noise margin.
In a further embodiment, the global read bit line is initially precharged to a memory supply voltage level before a read operation. In a yet further embodiment, the global read bit line is separately controlled by each of the upper and lower local read bit lines, wherein the separately controlled global read bit line employs a two transistor wire NOR circuit. In a still further embodiment, the global read bit line is coupled to an inverter circuit to provide a read data output. The method 500 ends in a step 530.
While the method disclosed herein has been described and shown with reference to particular steps performed in a particular order, it will be understood that these steps may be combined, subdivided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order or the grouping of the steps is not a limitation of the present disclosure.
In summary, advantages provided by embodiments of the present disclosure employing a pseudo-differential memory read approach include:
Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201410052592.1 | Feb 2014 | CN | national |
