Patent Application
20140146209
The present invention relates, in general, to a complementary metal oxide (CMOS) imager that includes a plurality of pumped pixels for storing pixel charge before readout.
In conventional dual pinned photo-diode pixels, one of the pinned photo-diodes is utilized as memory to store accumulated charge while reducing the effects of dark current. These conventional pixels, however, have well capacities that are limited to the difference in potential between adjacent wells. In general, a pinned photo-diode receiving charge must have a higher well potential than the well potential of a photo-diode supplying the charge. Charge transfer is performed similar to water transfer by pouring the charge from a lower well potential (shallow well depth) to a higher well potential (deep well depth). Due to limitations in voltage swing (i.e. potential between wells) in a pixel, the charge handling capacities are also limited.
As described below, the present invention provides a pumped pixel having dual photo-diodes (e.g. pinned photo-diodes) and at least one virtual charge barrier (e.g. a heavily p-doped region on the surface and an n-doped region underneath). One of the photo-diodes accumulates charge in response to impinging photons. The other photo-diode acts as a memory node that stores the accumulated charge.
In one example, the accumulated charge is pumped (by a pump gate) over the charge barrier and into the photo-diode for storage or into the floating diffusion for readout. In general, the charge barrier blocks the charge from leaking back into the photo-diode from where it was pumped. Being able to pump and store the charge may allow the imager to delay pixel readout and/or extend dynamic range without the need for large voltage differences (differences in well potentials) and/or doping between the photo-diode wells.
A six transistor (6T) circuit for a pixel 150 of a CMOS imager is illustrated in
It is noted that
Photodiode 162 accumulates photo-electrons generated in response to impinging photons. This accumulated charge is pumped over charge barrier 165 and into pinned photo-diode 164 for storage when activated by the PG control signal during a storage period. The stored charge is then transferred to floating diffusion stage node A through transfer transistor 190 when activated by the TX control signal during a readout period. The source follower transistor 186 has a gate terminal connected to node A and thus amplifies the signal appearing at floating diffusion node A. When a particular row containing pixel 150 is selected by an activated row select transistor 188, the signal amplified by the source follower transistor 186 is passed on a column line 170 to a column readout circuitry 242 (shown in
The gate terminal of transfer transistor 190 is coupled to a transfer control signal line 191 for receiving the TX control signal, thereby serving to control the coupling of the photodiode 164 to node A. A voltage source Vpix is coupled through reset transistor 184 to node A. The gate terminal of reset transistor 184 is coupled to a reset control line 183 for receiving the RST control signal to control the reset operation in which the voltage source Vpix is connected to node A, pinned photo-diode 164 and pinned photo-diode 162 for clearing charge.
A row select signal (RS) on a row select control line 160 is used to activate the row select transistor 188. Although not shown, the row select control line 160 may be used to provide a row select signal (RS) to all of the pixels of the same row of the array, as are the RST and TX lines. Voltage source Vpix is coupled to transistors 184 and 186 by conductive line 195. A column line 170 is coupled to all of the pixels of the same column of the array and typically has a current sink 176 at its lower end. The upper part of column line 170, outside of the pixel array, includes a pull-up circuit 111 which is used to selectively keep the voltage on column line 170 high. Maintaining a positive voltage on the column line 170 during an image acquisition phase of a pixel 150 keeps the potential in a known state on the column line 170. Signals from the pixel 150 are therefore selectively coupled to a column readout circuit through the column line 170 and through a pixel output (“Pix_out”) line 177 coupled between the column line 170 and the column readout circuit.
In general, Pix_out line 177 is coupled to the sample and hold (S/H) column capacitors 114 and 116 (i.e. two capacitors per column line to perform correlated double sampling). Transistors 110 and 112 are also included to ensure that the pixel output signals (i.e. the potentials after reset and integration) are each stored on the appropriate capacitor. These two potentials are compared (i.e. subtracted from each other) to perform correlated double sampling.
In general, a value can be read from pixel 150 in a two step correlated double sampling process. Prior to a charge integration period, node A and the photo-diodes 162 and 164 are reset to a high potential by activating reset transistor 184, transfer transistor 190 and pump gate 167. Photodiode 162 can alternatively be reset to a high potential by activating anti-blooming gate 166. During the charge integration period, photodiode 162 produces a charge from incident light. This is also known as the image acquisition period. Charges may be transferred from photo-diode 162 to photo-diode 164 by activating pump gate 167. Before charge transfer, node A and photo-diode 164 are reset to a high potential by activating reset transistor 184 and transfer transistor 190 to remove parasitic charges accumulated in photo-diode 164 due to mechanisms such as dark current and light leakage.
During the readout period, node A is again reset to a high potential. The charge (i.e. reset signal) at node A after reset is readout to column line 170 via the source follower transistor 186 and row select transistor 188. Readout circuitry 242 in
In general, the pixel signals from the array 230 are read out a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234, row drivers 240 and column addressing circuit 244. Signals corresponding to charges stored in the selected row of pixels and reset signals are provided on the column lines 170 to a column readout circuit 242 in the manner described above. The pixel signal read from each of the columns can be read out sequentially using a column addressing circuit 244. Pixel signals (Vrst, Vsig) corresponding to the readout reset signal and integrated charge signal are provided as respective outputs Vout1, Vout2 of the column readout circuit 242 where they are subtracted in differential amplifier 246, digitized by analog to digital converter 248, and sent to an image processor circuit 250 for image processing.
Shown in
During operation, pinned photo-diode 162 accumulates charge based on impinging photons. This accumulated charge is held in pinned photodiode 162 due to raised wells 151 and 153(A). The well depths of the various gates may be modulated (raised or lowered) based on the voltage applied to the gate terminals (i.e., based on the voltage signal AB, PG and TX).
For example, during the integration period, anti-blooming gate 166 and pump gate 167 are driven by a negative voltage which raises the wells so that charge is isolated in pinned photo-diode 162. Then, during a storage period (i.e., after and/or during integration), the pump gate 167 is driven by a positive voltage to lower a clock barrier in region 153(A) and a clock well in region 153(B). In general, the clock barrier and clock well are differently doped regions under the pump gate (e.g. the clock well is doped to be deeper than the dock barrier). This allows charge from pinned photo-diode 162 to transfer (i.e. spill over) into lowered clock well 153(B). Once the clock well is filled, pump gate 167 is then driven by a negative voltage which raises clock barrier 153(A) and clock well 153(B) thereby transferring (i.e. pumping) the charge over the top of barrier 165 and into pinned photo-diode 164 for storage. In general, the clock barrier (due to being higher than the clock well) prevents charge stored in the clock well from spilling back into the first pinned photo-diode during the pumping process. During both the integration and storage period, transfer gate 190 is closed by applying a negative voltage therefore raising the transfer gate well and blocking charge from spilling into floating diffusion A. However, during a readout period, transfer gate 190 is pulsed with a high positive voltage which lowers the transfer gate well thereby transferring the stored charge from pinned photo-diode 164 and into floating diffusion A where the pixel readout procedure (described above) is performed.
In general, the substrate may be designed (i.e., doped) such that the wells in pinned photo-diode 162 and 164 have equivalent capacity. In this example, pump gate 167 is able to pump the charge from pinned photo-diode 162 over the charge barrier and into pinned photo-diode 164 regardless of the well depth of the photodiodes.
In another example, the well capacity of pinned photo-diode 164 may be greater (i.e. deeper) than the well capacity of pinned photo-diode 162. This allows for increased dynamic range. As pinned photo-diode 162 is accumulating charge, pump gate 167 may periodically (during the integration period) pump the accumulating charge into pinned photo-diode 164 (which has a deeper well than 162) thereby allowing a longer integration time where pinned photo-diode 162 accumulates with charge multiple times. It is noted that pump gate 167 may be modulated one time or multiple time during or after integration in order to pump the charge from pinned photo-diode 162 into pinned photo-diode 164. It is also noted that clock well 153(B) may be designed to have the same capacity or smaller capacity than pinned photo-diode 162 in order to transfer the charge in a single pump or in multiple repeated pumps. It is also noted that anti-blooming gate 166 is optional. Anti-blooming gate 166 allows excess charge accumulated by pinned photo-diode 162 to spill over to potential Vpix rather than spilling over into adjacent pixels. Moreover, the anti-blooming gate 166 can be used to reset photo-diode 162.
The charge barrier may he positioned between other areas of the substrate. For example, shown in
In another example, as shown in
During operation, the charge accumulated by pinned photo-diode 162 may be pumped over charge barrier 165(A) and stored in pinned photo-diode 164. Then, during a readout period, the charge stored in pinned photo-diode 164 may be pumped over charge barrier 165B and into the floating diffusion A.
It is noted that in
Shown in
During an integration period, pump gate 167 and transfer gate 190 have negative voltage signals PG and TX thereby raising the dock barrier and clock well 390 and 392 and transfer well 394. During the integration time, the first pinned photo-diode 162 is accumulating charge 302. Since clock barrier 390 is raised, charge 302 is isolated in pinned photo-diode 162.
Then, during a storage period (which may be after the integration period or during the integration period), pump 167 voltage PG is increased to a positive voltage which lowers clock barrier 390 and clock well 392. When clock well 392 is lowered some or all of the charge (i.e., depending on the size of clock well 392) is transferred from the first pinned photo-diode 162 and into the clock well 392 as charge 304 (see
During the second half of the storage period, the pump gate 167 voltage PG is set to a negative voltage which raises clock harrier 390 and clock well 392 thereby pumping charge 304 over the top of the charge barrier and into the second pinned photo-diode 164 as charge 306 (see
The pumping period may be repeated a plurality of times to pump all of charge 302 from the first pinned photo-diode 162 over the charge barrier and into the second pinned photo-diode 164 (charge 302 has been moved to 306). In general, charge 306 is isolated in the second pinned photo-diode 164 due to the charge barrier and the raised transfer well 394 (see
After the storage period, (i.e., during the readout period), transfer gate 190 may have its TX voltage increased to a positive voltage which lowers transfer well 394 allowing charge 306 to spill over (i.e., transfer) into floating diffusion A as charge 308 (see
As shown in
During the storage period, the voltage on transfer gate 167 may be increased to a positive voltage which lowers transfer well 394 allowing charge to spill over into second photodiode 164 for storage. Then, during a readout period, the pump gate 190 may have its voltage increased to a positive voltage which lowers clock barrier 390 and clock well 392 to fill up with the charge from photodiode 164. Once a negative voltage is then applied to pump gate 190, the charge in clock well 392 will pour over the charge barrier 165 and into floating diffusion A as charge 320. As described above, the pumping may be performed in a single pump or multiple pumps depending on the amount of charge.
Similarly, in
It is noted that the well capacities of the pinned photo-diodes, pump gates, transfer gates and floating diffusions may be designed (i.e., doped and biased) differently. For example, the charge barrier 165 may be taller or shorter depending on the doping. Similarly, the clock barrier and the clock well on the pump gate may be able to pump more or less charge depending on their relative difference with respect to each other.
As described above, the imager may operate in a rolling shutter mode or a global shutter mode. In a rolling shutter mode, three pointers may be employed (i.e., a reset pointer, a storage pointer and a read pointer). In operation, the reset pointer may traverse from the top to the bottom of the array performing a row by row pixel reset (i.e. the pinned photo-diodes, floating diffusions and gate wells for the pixels in each row are reset to a potential).
Behind the reset pointer may be one of more storage pointers which may traverse from the top to the bottom of the array transferring (i.e., pumping) the charge accumulated in the photodiode into the second pinned photo-diodes for storage. Behind the storage pointer may be a read pointer which may also traverse from the top to the bottom of the pixel array to perform row by row charge transfer of the charge from the second pinned photo-diode into the floating diffusion for read out. In one example, a storage pointer is immediately positioned before the read pointer. Other storage pointers may also be positioned before the read pointer to increase dynamic range.
The storage pointer may be beneficial in rolling shutter mode to control pixels to avoid large voltage swings and or to increase dynamic range. Specifically, the first pinned photo-diode 162 may be controlled to accumulate charge repeatedly which is then periodically transferred over the barrier and stored (using the multiple storage pointers) in a second pinned photo-diode 164.
In a global shutter mode, each pixel in every row is exposed during the integration period simultaneously, while the rows are still read out sequentially similar to the rolling shutter. Thus, in global shutter mode, a storage of each pixel value may be beneficial for delaying readout. For example, the first pinned photo-diode 162 of every pixel may accumulate charge during the integration period and then have that charge pumped into the second pinned photo-diode 164 for storage. That stored charge may then be accessed (i.e., transferred into the floating diffusion) at a later time when the pixels are read out row by row, and while the first photo-diode 162 is accumulating charge for the next image.
Accordingly, the present invention provides a pumped pixel which includes at least one pump gate and one charge barrier. In general, charge is pumped over the charge barrier by modulating a clock barrier and clock well located below the pump gate. The combination of the pump gate and charge barrier in the pumped pixel allows for adjacent photodiodes to have similar well potentials while still being able to transfer charge (i.e., large well potential differences may be avoided).
Although the invention is illustrated and described, herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.
This application is a division of U.S. patent application Ser. No. 13/242,865, filed Sep. 23, 2011, which is a non-provisional of U.S. provisional patent application 61,467,561, filed Mar. 25, 2011, which are hereby incorporated by reference herein in their entireties. This application claims the benefit of and claims priority to U.S. patent application Ser. No. 13/242,865, filed Sep. 23, 2011 and U.S. provisional patent application 61,467,561, filed Mar. 25, 2011.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13242865 | Sep 2011 | US |
| Child | 14171181 | US |
