Claims
- 1. A method of manufacturing a quantum effect device comprising the steps of:
- forming a thin silicon layer by making an upper silicon layer on an SOI substrate thinner through etching of an entire main surface of said upper silicon layer;
- forming a first linear pattern of a field enhanced oxide film on said thin silicon layer by allowing a conductive tip to come close to a main surface of said thin silicon layer and effecting a field enhanced oxidation by scanning, with said conductive tip, the main surface of said thin silicon layer in a direction parallel to one side of said SOI substrate;
- forming, on said thin silicon layer, a second linear pattern of a field enhanced oxide film crossing said first linear pattern at a crossing portion by allowing said conductive tip to come close to a predetermined area in said first linear pattern and effecting the field enhanced oxidation by scanning, with said conductive tip, the main surface of said thin silicon layer in a direction vertical to said first linear pattern;
- forming a first quantum wire and a second quantum wire of silicon crossing each other at a crossing portion by effecting anisotropic etching on said thin silicon layer by using said first and second linear patterns as masks;
- after removing said first and second linear patterns, forming tunnel barriers of a field enhanced oxide film in first and second areas in said first quantum wire sandwiching said crossing portion by effecting the field enhanced oxidation with said conductive tip allowed to come successively close to said first and second areas; and
- forming insulating films of a field enhanced oxide film in third and fourth areas in said second quantum wire sandwiching said crossing portion by effecting the field enhanced oxidation with said conductive tip allowed to come successively close to said third and fourth areas.
- 2. A method of manufacturing a semiconductor device comprising the steps of:
- forming a thin silicon film by making an upper silicon layer on an SOI substrate thinner through etching of an entire main surface of said upper silicon layer;
- forming a first linear pattern of a field enhanced oxide film on said thin silicon layer by allowing a conductive tip to come close to a main surface of said thin silicon layer and effecting a field enhanced oxidation by scanning, with said conductive tip, the main surface of said thin silicon layer in a direction parallel to one side of said SOI substrate;
- forming, on said thin silicon layer, a second linear pattern of a field enhanced oxide film connected with said first linear pattern through a first branching portion by allowing said conductive tip to come close to a predetermined area in said first linear pattern and effecting the field enhanced oxidation by scanning, with said conductive tip, the main surface of said thin silicon layer in a direction vertical to said first linear pattern;
- forming, on said thin silicon layer, a third linear pattern of a field enhanced oxide film connected with said second linear pattern through a second branching portion by allowing said conductive tip to come close to a predetermined area in said second linear pattern and effecting the field enhanced oxidation by scanning, with said conductive tip, the main surface of said thin silicon layer in a direction vertical to said second linear pattern;
- forming a first quantum wire and a second quantum wire of silicon connected with each other through said first branching portion and a third quantum wire of silicon connected with said second quantum wire through said second branching portion by effecting anisotropic etching on said thin silicon layer by using said first, second and third linear patterns as masks;
- forming a first tunnel barrier of a field enhanced oxide film in a first area in said first quantum wire on one side of said first branching portion opposite to said third quantum wire by effecting the field enhanced oxidation with said conductive tip allowed to come close to said first area;
- forming a second tunnel barrier of a field enhanced oxide film in a second area in said first quantum wire on the same side of said first branching portion as said third quantum wire by effecting the field enhanced oxidation with said conductive tip allowed to come close to said second area;
- forming a third tunnel barrier of a field enhanced oxide film in a third area in said second quantum wire on the same side of said second branching portion as said first branching portion by effecting the field enhanced oxidation with said conductive tip allowed to come close to said third area;
- forming a fourth tunnel barrier of a field enhanced oxide film in a fourth area in said third quantum wire on one side of said second branching portion by effecting the field enhanced oxidation with said conductive tip allowed to come close to said fourth area;
- depositing an interlayer insulating film on an entire surface of said SOI substrate;
- forming a first control electrode on said interlayer insulating film above said first branching portion;
- forming a second control electrode on said interlayer insulating film above a part of said first quantum wire on the same side of said second tunnel barrier as said third quantum wire and above said third quantum wire; and
- forming a third control electrode on said interlayer insulating film above said second branching portion.
- 3. The method of manufacturing a semiconductor device of claim 2,
- wherein each of said first, second, third and fourth tunnel barriers is formed by completely oxidizing a section of said corresponding quantum wire.
- 4. The method of manufacturing a semiconductor device of claim 3,
- wherein said thin silicon layer on said SOI substrate has a thickness of 50 nm or less.
- 5. The method of manufacturing a semiconductor device of claim 2,
- wherein each of said first, second, third and fourth tunnel barriers is formed by partly oxidizing a section of said corresponding quantum wire.
- 6. The method of manufacturing a semiconductor device of claim 5,
- wherein said thin silicon layer on said SOI substrate has a thickness of 50 nm or less.
Priority Claims (2)
Number |
Date |
Country |
Kind |
8-083675 |
Apr 1996 |
JPX |
|
8-086176 |
Apr 1996 |
JPX |
|
Parent Case Info
This is a divisional of application Ser. No. 08/834,828, filed Apr. 3, 1997.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
5347140 |
Hirai et al. |
Sep 1994 |
|
5618760 |
Soh et al. |
Apr 1997 |
|
Divisions (1)
|
Number |
Date |
Country |
Parent |
834828 |
Apr 1997 |
|