Claims
- 1. A tunneling electronic semiconductor device comprising:
- a series of abutting material layers, the electron energy levels of which provide a quantum well layer between adjacent layers, the valence electron energy level of said quantum well layer being higher than the conduction electron energy level of said adjacent layer at a first selected bias voltage across said series of layers and the valence electron energy level of said quantum well layer being lower than the conduction electron energy level of said adjacent layers at a second selected bias voltage across said series of layers, whereby maximum tunneling current flows through said device during application of said first bias voltage and minimum tunneling current flows through said device during application of said second bias voltage.
- 2. The device recited in claim 1 wherein said series of material layers comprises InAs/AlSb/GaSb/AlSb/InAs.
- 3. The device recited in claim 1 wherein said device is a diode.
- 4. The device recited in claim 1 wherein said device is a transistor.
- 5. The device recited in claim 1 wherein the ratio of said maximum current to said minimum current is at least about 20 at room temperature and is at least about 88 at 77 degrees KELVIN.
- 6. A resonant interband tunneling electronic device comprising:
- a quantum well layer;
- a pair of barrier layers sandwiching said quantum well layer; and
- a pair of contact layers sandwiching said barrier layers and said well layer;
- the valence energy level of said well layer being higher than the conduction energy level of said contact layers at a first selected bias voltage across said device and the valence energy level of said well layer being lower than the conduction energy level of said contact layers at a second selected bias voltage across said device;
- whereby maximum tunneling current flows through said device during application of said first bias voltage and minimum tunneling current flows through said device during application of said second bias voltage.
- 7. The device recited in claim 6 wherein said quantum well layer comprises GaSb.
- 8. The device recited in claim 6 wherein said barrier layers comprise AlSb.
- 9. The device recited in claim 6 wherein said contact layers comprise InAs.
- 10. A heterostructure interband tunneling electronic device comprising:
- a quantum well layer;
- a barrier layer; and
- a contact layer;
- the valence energy level of said well layer being selectively adjustable to be higher and lower than the conduction energy level of said contact layer depending upon the bias voltage across said device;
- whereby maximum tunneling current flows through said device during application of a first bias voltage to raise said valance energy level above said conduction energy level and minimum tunneling current flows through said device during application of a second bias voltage to lower said valance energy level below said conduction energy level.
- 11. The device recited in claim 10 wherein said quantum well layer comprises GaSb.
- 12. The device recited in claim 10 wherein said barrier layer comprises AlSb.
- 13. The device recited in claim 10 wherein said contact layer comprises InAs.
- 14. The device recited in claim 10 further comprising a substrate of GaAs.
- 15. A quantum-effect transistor comprising:
- a epitaxially-grown series of material layers on a underlying substrate;
- said layers having a quantum well layer sandwiched between two barrier layers which are in turn, sandwiched between two contact layers;
- said well layer having a valence energy level which can be made selectively higher and lower than the conduction energy level of said contact layer depending upon the magnitude of a bias voltage established between said well layer and a contact layer;
- whereby maximum tunneling current flows through said transistor during application of a first bias voltage to raise said valence energy level above said conduction energy level and minimum tunneling current flows through said transistor during application of a second bias voltage to lower said valance energy level below said conduction energy level.
- 16. The transistor recited in claim 15 wherein said quantum well layer comprises GaSb.
- 17. The transistor recited in claim 15 wherein said barrier layers comprise AlSb.
- 18. The transistor recited in claim 15 wherein said contact layers comprise InAs.
- 19. The transistor recited in claim 15 wherein said well layer is the base of said transistor.
- 20. The transistor recited in claim 15 wherein said well layer is the collector of said transistor.
- 21. A quantum-effect electronic device of the type in which current flow is determined by the number of tunneling hole carriers, the device comprising:
- a quantum well layer of material;
- a barrier layer of material; and
- a contact layer of material;
- the valence energy band edge of the contact layer being selectively made higher and lower than the conduction energy band edge of the well layer depending upon the bias voltage magnitude applied across said layers;
- whereby maximum tunneling current flows through said device during application of a first bias voltage to raise said valance energy level above said conduction energy level and minimum tunneling current flows through said device during application of a second bias voltage to lower said valance energy level below said conduction energy level.
ORIGIN OF INVENTION
This invention was made with Government support under Grant No. N00014-89-J-1141 awarded by the Department of the Navy. The Government has certain rights in this invention.
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Foreign Referenced Citations (1)
Number |
Date |
Country |
63-174367 |
Jul 1988 |
JPX |
Non-Patent Literature Citations (2)
Entry |
Chang et al., IBM TDB, vol. 22 No. 7 Dec. 79 "GaSb-InAs-GaSb pnp . . . Speeds". |
IBM TDB, vol. 31 No. 7 Dec. 1988 "Negative Resistance Device". |