Claims
- 1. A process for the manufacture of a power integrated circuit having improved total dose resistance and resistance to single event failure, the process comprising the steps of forming gate oxides after forming high temperature diffusions in a high voltage junction isolation process so as to avoid exposing the gate oxides to high temperature processing steps.
- 2. The process of claim 1, further comprising the step of forming field oxides after forming high temperature diffusions in a high voltage junction isolation process so as to avoid exposing the field oxides to high temperature processing steps.
- 3. The process of claim 1, further comprising the steps of:
forming an epitaxial layer on an upper surface of a substrate, the epitaxial layer being separated into a control segment and a power segment by an isolation region; introducing a resurf region and a separate deep body in the power segment; providing control diffusions in the control segment; forming a layer of gate insulation on the control segment and on the power segment; and forming gate electrodes over layer of gate insulation and on the control segment and the power segment.
- 4. The process of claim 3, wherein the step of forming the epitaxial layer comprises forming a bottom epitaxial layer covered by a top epitaxial layer, the bottom layer having an increased charge concentration over that of the top epitaxial layer.
- 5. The process of claim 4, wherein the bottom epitaxial layer is As-doped, and the top epitaxial layer is P-doped.
- 6. The process of claim 3, wherein the thickness of the epitaxial layer is less than that of non-radhard PIC, to reduce parasitic bipolar gain.
- 7. The process of claim 3, further comprising the step of forming implant layers in the control segment for raising parasitic MOSFET thresholds with respect to native MOSFET thresholds.
- 8. The process of claim 3, further comprising reducing CMOS drain to source leakage and device to device leakage by laying out a poly gate to field oxide overlap and by individually ringing all CMOS devices with channel adjust layers.
- 9. A process for the manufacture of a power integrated circuit having improved total dose radiation resistance and resistance to single event failure, the method comprising the sequential steps of:
forming an epitaxial layer on a substrate; introducing dopants into an upper surface of the dual epitaxial layer to isolate a control segment and a power segment; introducing dopants into the upper surface of the isolated control and power segments to form a plurality of channel regions; and thereafter forming a gate insulation layer over at least the channel regions.
- 10. The process of claim 9, wherein the step of forming an epitaxial layer comprises forming a dual epitaxial layer having a higher concentration layer at a junction with the substrate.
- 11. The process of claim 9, further comprising the step of forming implant layers in the control segment for raising parasitic MOSFET thresholds with respect to native MOSFET thresholds.
- 12. The process of claim 9, further comprising the step of forming a radhard field oxide.
- 13. The process of claim 12, wherein the step of forming a radhard field oxide includes depositing undoped oxide on top of a thin thermally grown oxide.
- 14. The process of claim 12, wherein the radhard field oxide is a layer having a thickness of about 8000 Å.
Parent Case Info
[0001] This application claims the benefit of U.S. Provisional application Ser. No. 60/179,843, filed Feb. 2, 2000.
Provisional Applications (1)
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Number |
Date |
Country |
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60179843 |
Feb 2000 |
US |