The present invention relates to the field of static random access memory cells. More specifically, the present invention relates to static random access memory cells that comprise six transistors and are radiation hardened to achieve single event upset and soft error immunity using ferroelectric materials.
Single events and soft errors in circuits are the result of high energy particles interacting with and causing changes to the electrical states in certain electrical components. These phenomena are generally temporally and spatially random, although the effect that they have on a given circuit may be affected by the physical and electrical characteristics of the circuit. In general, as circuits scale down to smaller sizes they are more susceptible to single events and soft errors, due largely to reductions in drive currents and voltages which lead to smaller noise margins. At the 65 nm technology node and below, the high leakage currents that are expected with standard complementary metal oxide semiconductor (CMOS) circuits increases this susceptibility.
In memory cells, the results of single events and soft errors may be a change in the stored value. Specifically, a high-energy particle interacting with a node at a low electrical state may cause the node to jump to a high electrical state. In a dynamic random access memory (DRAM) cell, this increase in energy may easily change the value on the capacitive storage node. In a static random access memory (SRAM) cell comprising dual-feedback inverters, the interaction of high-energy particles may be sufficient to interrupt the feedback loop and drive the normally stable device to invert its stored binary state. Although hardening DRAM cells against single event and soft error phenomena is generally performed outside of the memory cell circuit, hardening of SRAM cells has generally been accomplished by altering the feedback properties of the cell so that an upset occurring at only one node will not propagate through the entire latch.
In a general SRAM cell comprising two inverters formed by CMOS logic, one method for hardening the circuit by altering the feedback may be through increasing the RC delay of one of the feedback nodes.
bshows a transistor-level schematic of the dual-inverter SRAM cell, where the inverters are implemented using CMOS logic. Each inverter comprises a matched pair of p-type metal oxide semiconductor (PMOS) transistors and n-type metal oxide semiconductor (NMOS) transistors. The source node of each PMOS device 106, 110 is coupled to a supply voltage rail, while the source node of each NMOS device 108, 112 is coupled to an electrical ground rail. For each inverter, the corresponding PMOS and NMOS gates are coupled to the inverter input while the drains are coupled to the inverter output.
As discussed above, the standard SRAM cell may be radiation hardened by augmenting one of the feedback loops with resistive or capacitive loads to create additional RC delay.
As a result, it would be desirable to design a SRAM cell that is protected against single event and soft error phenomena and that also requires as small of an increase in memory cell area as possible. Furthermore, it would be desirable for any modified SRAM cell designs to require few, if any, additional processing steps.
Exemplary embodiments of the invention are described below in conjunction with the appended figures, wherein like reference numerals refer to like elements in the various figures, and wherein:
1. Invention Overview
Much development in memory systems has been directed towards an increase in both the performance and capabilities of individual memory cells. The development of ferroelectric materials has led to new methods for improving both DRAM and SRAM devices. Due to their generally high dielectric constants and large resistance, ferroelectric materials are ideally suited as dielectric layers in capacitors. The high dielectric constant of ferroelectric materials results in capacitors of a given capacitance requiring a smaller overall area than those utilizing general oxide dielectrics. As a result, ferroelectric capacitors have been utilized in single-transistor single-capacitor (1T1C) DRAM cells to reduce the memory cell size, as well as in SRAM cells to increase the speed of the cell. In 1T1C DRAM cells, ferroelectric capacitors have been used to implement the storage capacitor. In SRAM cells, ferroelectric capacitors have been coupled to write lines as shadow capacitors in order to increase the drive and speed of the memory cell. However, the integration of ferroelectric devices, especially capacitors, has generally been limited to these applications.
The current invention takes advantage of the reduced size of ferroelectric capacitors in order to implement an SRAM cell with protection against soft errors and single event effects, such as single event upsets (SEU), single event effects (SEE), and single event transients (SET). The design comprises a dual-inverter SRAM cell with a ferroelectric capacitor coupled to the input of one of the inverters. The RC delay that results from the ferroelectric capacitor helps to reduce the adverse effects of bombardment by high-energy particles. Additionally, the use of ferroelectric material allows the capacitor to attain a high-capacitive value without the consumption of relatively large amounts of area. The design thereby allows a radiation-hardened cell to be implemented without sacrificing the optimization of memory cell area.
2. Memory Cell Design and Operation
A read operation may be performed on the memory cell by charging both the true bit line and the complement line. Once both lines are charged the word line signal may be enabled, thereby electrically coupling the storage nodes of the latch to the word lines. During the read operation the bit lines will then be pulled to the state stored on their respective nodes of the cell. A write operation may be performed on the memory cell by first charging the true bit line and the complement bit line to the desired complimentary states, and then enabling the first and second switches by driving the word line signal. The voltages charged on the bit lines will then drive the latch component of the memory cell to store the desired binary value and its compliment.
According to one embodiment of the invention, coupled to the output of the first inverter (and the input of the second inverter) may be a ferroelectric capacitor 302. The ferroelectric capacitor may be a parallel plate capacitor with ferroelectric material comprising the central spacing, or dielectric layer. The ferroelectric material may be any type of ferroelectric or other pyroelectric material in which the spontaneous polarization can be reoriented between equilibrium states by applying an electric field. The dielectric material may be lead zirconium titanate (PbZrxTi1−xO3), strontium bismuth tantalite (SrBi2Ta2O9), bismuth lanthanum titanate (Bi4−xLaxTiO12), or other type of ferroelectric material. One plate of the ferroelectric capacitor 302 may be connected to the output of the first inverter, with the second plate being connected to a reference voltage rail, such as the electrical ground rail. The ferroelectric capacitor 302 may induce a delay in the feedback loop between the output of the second inverter 104 and the input of the first inverter 102, thereby creating an imbalance in the propagation delay of the latch circuit that disrupts the race condition caused by a high-energy particle collision. As a result, the memory cell will not flip states. The ferroelectric capacitor 302 may be created after the underlayers of the memory cell have already been fabricated, where the underlayers generally consist of those components fabricated at a lower level than the metallization layers. In an SRAM memory cell, the device components fabricated in the underlayer processes may comprise any doped substrate regions, transistor gate dielectrics, and polysilicon gates. The ferroelectric capacitor 302 may then be fabricated with the subsequent metallization layers, and with a separate masking step being utilized to deposit the ferroelectric dielectric material. As a result, the plates of the ferroelectric capacitor 302 may be comprised of the same metals used for the manufacture of the memory cell at a given metallization step, such as the interconnect metals aluminum and copper.
Additionally, the effect of the capacitor in disrupting the effects of high-energy particle collisions may be augmented by altering the threshold voltage of the transistors in the first inverter with respect to the second inverter.
Exemplary embodiments of the present invention relating to a memory cell with single event and soft error protection using ferroelectric materials have been illustrated and described. It should be noted that more significant changes in configuration and form are also possible and intended to be within the scope of the system taught herein. For example, the ferroelectric capacitor may likewise be coupled to the output of the second inverter rather than the first inverter. In addition, the transistors of the second inverter may be thick-oxide transistors with the transistors of the first inverter being thin-oxide transistors consistent with the descriptions of such devices provided above. In addition, the inverters and latches of the SRAM cell may be implemented with other devices than CMOS devices.
Unless otherwise indicated in the description, the accompanying figures are not drawn to scale and should not be interpreted as such. For example, where it is not otherwise indicated the relative sizes of transistors are not to be taken from the figures nor are the specific lengths and routings of interconnects, and the figures are not intended to be limiting in this respect.
In view of the wide variety of embodiments to which the principles of the present invention can be applied, it should be understood that the illustrated embodiments are exemplary only, and should not be taken as limiting the scope and spirit of the present invention. Additionally, the claims should not be read as limited to the described order or elements unless stated to that effect.