The present disclosure relates to a reverse conducting IGBT (RC-IGBT).
An RC-IGBT is a semiconductor device in which an insulated gate bipolar transistor (IGBT) region and a diode region are provided on one semiconductor substrate. Japanese Patent Application Laid-Open No. 2019-186504 discloses an RC-IGBT that has an IGBT region, a diode region, a wiring region, and a termination region, and the termination region has a p-type well layer that is deeper than a p-type base layer and a trench in the IGBT region so as to act to relax an electric field when holding a reverse withstand voltage.
In the RC-IGBT of Japanese Patent Application Laid-Open No. 2019-186504, the p-type well layer in the termination region is deeper than the p-type base layer in the IGBT region. Therefore, a manufacturing step of forming a plurality of p-type diffusion layers having different depths one by one is required, and there is a problem that manufacturing cost increases.
An object of the present disclosure is to reduce manufacturing cost of an RC-IGBT.
The RC-IGBT of the present disclosure includes a semiconductor substrate. The semiconductor substrate has a cell region, a termination region, and a wiring region. The cell region includes an IGBT region and a diode region. The wiring region is provided between the cell region and the termination region. The semiconductor substrate has a first main surface and a second main surface that is a main surface on the opposite side of the first main surface. The semiconductor substrate includes a drift layer of a first conductivity type and a diffusion layer of a second conductivity type. The drift layer is provided in the cell region, the wiring region, and the termination region. The diffusion layer is provided on the first main surface side of the drift layer in the IGBT region, the diode region, the wiring region, and the termination region. The diffusion layer includes a base layer in the IGBT region, an anode layer in the diode region, a wiring well layer in the wiring region, and a termination well layer in the termination region. A plurality of trench gates are formed in the semiconductor substrate. The plurality of trench gates penetrate the diffusion layer from the first main surface to reach the drift layer. The plurality of trench gates include a plurality of active trench gates in the IGBT region, a plurality of diode trench gates in the diode region, and a plurality of wiring trench gates in the wiring region. A depth of the base layer is less than depths of the plurality of active trench gates, and is equal to or more than depths of the anode layer, the wiring well layer, and the termination well layer.
According to the RC-IGBT of the present disclosure, the diffusion layer of the second conductivity type can be simultaneously formed in the IGBT region, the diode region, the wiring region, and the termination region, and thus, the manufacturing cost can be reduced.
These and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings.
In the following description, n and p represent conductivity types of a semiconductor. Although description is given assuming that a first conductivity type is an n type and a second conductivity type is a p type in the present disclosure, the first conductivity type may be the p type, and the second conductivity type may be the n type. In addition, n-indicates an n-type impurity concentration lower than n, and n+ indicates an n-type impurity concentration higher than n. Similarly, p− indicates a p-type impurity concentration lower than p, and p+ indicates a p-type impurity concentration higher than p.
As illustrated in
As illustrated in
The control pad 41 includes, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad configured to sense a current flowing through the cell region of the RC-IGBT 101, and is a control pad electrically connected to a part of the IGBT cell or the diode cell in the cell region such that a current of a fraction to a fraction of tens of thousandths of a current flowing through the entire cell region flows when the current flows through the cell region of the RC-IGBT 101. The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for controlling on and off of the RC-IGBT 101 is applied. The Kelvin emitter pad 41b is electrically connected to a p-type base layer of the IGBT cell, and the gate pad 41c is electrically connected to a gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p+ type contact layer. The temperature sense diode pads 41d and 41e are control pads electrically connected to an anode and a cathode of a temperature sense diode provided in the RC-IGBT 101. A voltage between the anode and the cathode of the temperature sense diode (not illustrated) provided in the cell region is measured to measure the temperature of the RC-IGBT 101.
In
As illustrated in
As illustrated in
The active trench gate 11 has a configuration in which a gate trench electrode 11a is provided in a trench formed in a semiconductor substrate 50 with a gate trench insulating film 11b interposed therebetween. The dummy trench gate 12 has a configuration in which a dummy trench electrode 12a is provided in a trench formed in the semiconductor substrate 50 with a dummy trench insulating film 12b interposed therebetween. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode 6 on the front surface side of the RC-IGBT 101 or 102.
A n+ type source layer 13 is provided on both sides in a width direction of the active trench gate 11 so as to be in contact with the gate trench insulating film 11b. The n+ type source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as n-type impurities, and a concentration of the n-type impurities is 1.0×1017/cm3 or more and 1.0×1020/cm3 or less. The n+ type source layer 13 is provided alternately with a p+ type contact layer 14 along an extending direction of the active trench gate 11. Note that the n+ type source layer is also referred to as an n+ type emitter layer. The p+ type contact layer 14 is also provided between two adjacent dummy trench gates 12. The p+ type contact layer 14 is a semiconductor layer containing, for example, boron or aluminum as p-type impurities, and a concentration of the p-type impurities is 1.0×1015/cm3 or more and 1.0×1020/cm3 or less.
In
As illustrated in
On the first main surface S1 side of the n-type drift layer 1 in the IGBT region 10, an n-type carrier accumulation layer 2 having a higher n-type impurity concentration than the n-type drift layer 1 is provided. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as n-type impurities, and the concentration of the n-type impurities is 1.0×1013/cm3 or more and 1.0×1017/cm3 or less. Note that the RC-IGBT 101 or 102 does not necessarily include the n-type carrier accumulation layer 2. In this case, the n-type drift layer 1 is also provided in a region of the n-type carrier accumulation layer 2 illustrated in
Since the RC-IGBT 101 or 102 includes the n-type carrier accumulation layer 2, conduction loss when a current flows through the IGBT region 10 can be reduced. The n-type carrier accumulation layer 2 and the n-type drift layer 1 may be collectively referred to as a drift layer. The n-type carrier accumulation layer 2 is formed by ion-implanting the n-type impurities into the semiconductor substrate 50 forming the n-type drift layer 1, and then diffusing the implanted n-type impurities into the semiconductor substrate 50, which is the n-type drift layer 1, by annealing.
A p-type base layer 15 is provided as a p-type diffusion layer on the first main surface S1 side of the n-type carrier accumulation layer 2 in the IGBT region 10. The p-type base layer 15 is a semiconductor layer containing, for example, boron or aluminum as p-type impurities, and a concentration of the p-type impurities is 1.0×1012/cm3 or more and 1.0×1019/cm3 or less. The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface S1 side of the p-type base layer 15 in the IGBT region 10, an n+ type source layer 13 is provided in contact with the gate trench insulating film 11b of the active trench gate 11, and the p+ type contact layer 14 is provided in the remaining region. The n+ type source layer 13 and the p+ type contact layer 14 form the first main surface S1 of the semiconductor substrate 50. Note that the p+ type contact layer 14 is a region having a higher p-type impurity concentration than the p-type base layer 15. When the p+ type contact layer 14 and the p-type base layer 15 need to be distinguished from each other, each of them may be referred to separately. The p+ type contact layer 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.
On the second main surface S2 side of the n-type drift layer 1 in the IGBT region 10, an n-type buffer layer 3 having a higher n-type impurity concentration than the n-type drift layer 1 is provided. The n-type buffer layer 3 suppresses punch-through of a depletion layer stretching from the p-type base layer 15 to the second main surface S2 side when the RC-IGBT 101 or 102 is in an off state. The n-type buffer layer 3 is formed by injecting one or both of phosphorus (P) and proton (H+), for example. The concentration of n-type impurities in the n-type buffer layer 3 is 1.0×1012/cm3 or more and 1.0×1018/cm3 or less. Note that the RC-IGBT 101 or 102 does not necessarily include the n-type buffer layer 3. In this case, the n-type drift layer 1 is also provided in a region of the n-type buffer layer 3 illustrated in
The p-type collector layer 16 is provided on the second main surface S2 side of the n-type buffer layer 3 in the IGBT region 10. That is, the p-type collector layer 16 is provided between the n-type drift layer 1 and the second main surface S2. The p-type collector layer 16 is a semiconductor layer containing, for example, boron or aluminum as p-type impurities, and a concentration of the p-type impurities is 1.0×1016/cm3 or more and 1.0×1020/cm3 or less. The p-type collector layer 16 forms the second main surface S2 of the semiconductor substrate 50. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and a portion of the p-type collector layer 16 provided in the termination region 30 forms a p-type termination collector layer 16a (see
The trenches that penetrate the p-type base layer 15 from the first main surface S1 of the semiconductor substrate 50 to reach the n-type drift layer 1 are formed in the IGBT region 10. The gate trench electrode 11a is provided in the trench with the gate trench insulating film 11b interposed therebetween, thereby forming the active trench gate 11. The gate trench electrode 11a is opposite to the n-type drift layer 1 across the gate trench insulating film 11b. In addition, the dummy trench electrode 12a is provided in the trench with the dummy trench insulating film 12b interposed therebetween, thereby forming the dummy trench gate 12. The dummy trench electrode 12a is opposite to the n-type drift layer 1 across the dummy trench insulating film 12b. The gate trench insulating film 11b of the active trench gate 11 is in contact with the p-type base layer 15 and the n+ type source layer 13. When the gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.
An interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on a region of the first main surface S1 of the semiconductor substrate 50 where the interlayer insulating film 4 is not provided and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), titanium nitride, or TiSi obtained by alloying titanium and silicon (Si). The barrier metal 5 is in ohmic contact with the n+ type source layer 13, the p+ type contact layer 14, and the dummy trench electrode 12a, and is electrically connected to the n+ type source layer 13, the p+ type contact layer 14, and the dummy trench electrode 12a.
The emitter electrode 6 is provided on the barrier metal 5 in the IGBT region 10. The emitter electrode 6 may be made of, for example, an aluminum alloy such as an aluminum silicon alloy (Al—Si alloy). Alternatively, the emitter electrode 6 may have a configuration in which a plating film is formed by electroless plating or electrolytic plating on an electrode made of an aluminum alloy. Here, the plating film may be, for example, a nickel (Ni) plating film. In a case where there is a fine region between adjacent interlayer insulating films 4 or the like and it is difficult to obtain favorable embedding with the emitter electrode 6 in the region, tungsten having better embedding properties than the emitter electrode 6 may be arranged in the region, and the emitter electrode 6 may be provided on the tungsten.
Note that the barrier metal 5 is not necessarily provided in the IGBT region 10. In this case, the emitter electrode 6 is directly provided on the n+ type source layer 13, the p+ type contact layer 14, and the dummy trench electrode 12a. In addition, the barrier metal 5 may be provided only on an n-type semiconductor layer such as the n+ type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as an emitter electrode.
A collector electrode 7 is provided on the second main surface S2 side of the p-type collector layer 16 in the IGBT region 10. The collector electrode 7 may be made of an aluminum alloy or an aluminum alloy and a plating film, which is similar to the emitter electrode 6. In addition, the collector electrode 7 may have a configuration different from that of the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.
A cross-sectional configuration of the IGBT region 10 illustrated in
As illustrated in
As illustrated in
As illustrated in
The p-type anode layer 25 is provided on the first main surface S1 side of the n-type carrier accumulation layer 2 in the diode region 20. The p-type anode layer 25 is provided between the n-type drift layer 1 and the first main surface S1 of the semiconductor substrate 50. The p-type impurity concentration of the p-type anode layer 25 may be the same as the p-type impurity concentration of the p-type base layer 15 in the IGBT region 10. In that case, it is possible to simultaneously form the p-type anode layer 25 and the p-type base layer 15. Alternatively, the p-type impurity concentration of the p-type anode layer 25 may be lower than the p-type impurity concentration of the p-type base layer 15 in the IGBT region 10. As a result, the number of holes injected into the diode region 20 during a diode operation of the RC-IGBT 101 or 102 decreases, so that recovery loss during diode operation is reduced.
The p+ type contact layer 24 is provided on the first main surface S1 side of the p-type anode layer 25. The p-type impurity concentration of the p+ type contact layer 24 may be the same as or different from the p-type impurity concentration of the p+ type contact layer 14 in the IGBT region 10. The p+ type contact layer 24 forms the first main surface S1 of the semiconductor substrate 50. The p+ type contact layer 24 has the p-type impurity concentration higher than that of the p-type anode layer 25. When the p+ type contact layer 24 and the p-type anode layer 25 need to be distinguished from each other, each of them may be referred to separately. The p+ type contact layer 24 and the p-type anode layer 25 may be collectively referred to as a p-type anode layer.
The n+ type cathode layer 26 is provided on the second main surface S2 side of the n-type buffer layer 3 in the diode region 20. The n+ type cathode layer 26 is provided between the n-type drift layer 1 and the second main surface S2 of the semiconductor substrate 50. The n+ type cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as n-type impurities, and a concentration of the n-type impurities is 1.0×1016/cm3 or more and 1.0×1021/cm3 or less. The n+ type cathode layer 26 is provided in a part or a whole of the diode region 20. The n+ type cathode layer 26 forms the second main surface S2 of the semiconductor substrate 50. Although not illustrated, p-type impurities may be further selectively injected into a region where the n+ type cathode layer 26 is formed as described above, and a p-type cathode layer may be provided using a part of the region where the n+ type cathode layer 26 is formed as the p-type semiconductor.
As illustrated in
As illustrated in
The emitter electrode 6 is provided on the barrier metal 5 in the diode region 20. The emitter electrode 6 of the diode region 20 is formed continuously with the emitter electrode 6 of the IGBT region 10. Note that the barrier metal 5 is not necessarily provided in the diode region 20, which is similar to the IGBT region 10. In this case, the diode trench electrode 21a and the p+ type contact layer 24 are in ohmic contact with the emitter electrode 6. In a case where the barrier metal 5 is not provided, the p+ type contact layer 24 is not necessarily provided, either, and the p-type anode layer 25 and the emitter electrode 6 may be in ohmic contact with each other.
Note that
The collector electrode 7 is provided on the second main surface S2 side of the n+ type cathode layer 26. The collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 of the IGBT region 10, which is similar to the emitter electrode 6. The collector electrode 7 is in ohmic contact with the n+ type cathode layer 26 and is electrically connected to the n+ type cathode layer 26.
A cross-sectional configuration of
As illustrated in
A p-type termination well layer 31 is provided on the first main surface S1 side of the n-type drift layer 1 in the termination region 30, that is, between the first main surface S1 of the semiconductor substrate 50 and the n-type drift layer 1. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as p-type impurities, and a concentration of the p-type impurities is 1.0×1014/cm3 or more and 1.0×1019/cm3 or less. The p-type termination well layer 31 is provided to surround the cell region including the IGBT region 10 and the diode region 20. A plurality of the p-type termination well layers 31 are provided in a ring shape, and the number of the p-type termination well layers 31 is appropriately selected according to the withstand voltage design of the RC-IGBT 101 or 102. On the further outer edge side of the p-type termination well layer 31, an n+ type channel stopper layer 32 is provided between the first main surface S1 of the semiconductor substrate 50 and the n-type drift layer 1. The n+ type channel stopper layer 32 surrounds the p-type termination well layer 31.
The p-type termination collector layer 16a is provided between the n-type drift layer 1 and the second main surface S2 of the semiconductor substrate 50 in the termination region 30. The p-type termination collector layer 16a is formed continuously and integrally with the p-type collector layer 16 provided in the cell region. Therefore, the p-type termination collector layer 16a may be referred to as the p-type collector layer 16. In the configuration in which the diode region 20 is provided adjacent to the termination region 30 as in the RC-IGBT 101 in
The collector electrode 7 is provided on the second main surface S2 of the semiconductor substrate 50 in the termination region 30. The collector electrode 7 is integrally formed to be continuous from the cell region including the IGBT region 10 and the diode region 20 to the termination region 30. On the other hand, on the first main surface S1 of the semiconductor substrate 50 in the termination region 30, the emitter electrode 6 continuous from the cell region and a termination electrode 6a separated from the emitter electrode 6 are provided.
The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 is, for example, semi-insulating silicon nitride (sinSiN). The termination electrode 6a, the p-type termination well layer 31, and the n+ type channel stopper layer 32 are electrically connected via a contact hole formed in the interlayer insulating film 4 provided on the first main surface S1 of the semiconductor substrate 50. In addition, in the termination region 30, a termination protective film 34 is provided to cover the emitter electrode 6, the termination electrode 6a, and the semi-insulating film 33. The termination protective film 34 is made of polyimide, for example.
As illustrated in
The RC-IGBT 201 includes the n-type drift layer 1 formed of the semiconductor substrate 50 in the wiring region 302. The first main surface S1 and the second main surface S2 of the semiconductor substrate 50 in the wiring region 302 are the same as the first main surfaces S1 and the second main surfaces S2 of the semiconductor substrate 50 in the IGBT region 10 and the diode region 20, respectively. The n-type drift layer 1 of the wiring region 302 has the same configuration as the n-type drift layers 1 in the IGBT region 10 and the diode region 20, and is formed continuously and integrally with these.
A p-type wiring well layer 35 is provided on the first main surface S1 side of the n-type drift layer 1 in the wiring region 302, that is, between the first main surface S1 of the semiconductor substrate 50 and the n-type drift layer 1. A configuration on the second main surface S2 side of the n-type drift layer 1 in the wiring region 302 is similar to the configuration on the second main surface S2 side of the n-type drift layer 1 in the IGBT region 10.
In the wiring region 302, a trench that penetrates the p-type wiring well layer 35 from the first main surface S1 of the semiconductor substrate 50 to reach the n-type drift layer 1 is formed. A wiring trench electrode 36a is provided in the trench with a wiring trench oxide film 36b interposed therebetween, thereby forming a wiring trench gate 36. The wiring trench gate 36 is deeper than the p-type base layer 15 in the IGBT region 10. The wiring trench electrode 36a is opposite to the n-type drift layer 1 across the wiring trench oxide film 36b. The wiring trench oxide film 36b is in contact with the p-type wiring well layer 35 and the n-type drift layer 1.
In the wiring region 302, the interlayer insulating film 4 is provided on the first main surface S1 of the semiconductor substrate 50. In addition, a wiring electrode 6c is provided on the interlayer insulating film 4 of the wiring region 302. The wiring electrode 6c and the emitter electrode 6 in the cell region are electrically connected via the semi-insulating film 33. Note that the wiring trench gate 36, the active trench gate 11, the dummy trench gate 12, and the diode trench gate 21 are also collectively referred to as a trench gate.
The RC-IGBT 201 includes the n-type drift layer 1 formed of the semiconductor substrate 50 in the termination region 301. The first main surface S1 and the second main surface S2 of the semiconductor substrate 50 in the termination region 301 are the same as the first main surfaces S1 and the second main surfaces S2 of the semiconductor substrate 50 in the cell region and the wiring region 302, respectively. The n-type drift layer 1 in the termination region 301 has the same configuration as the n-type drift layer 1 in the cell region, and is formed continuously and integrally with the n-type drift layer 1.
The p-type termination well layer 31 is provided on the first main surface S1 side of the n-type drift layer 1 in the termination region 301, that is, between the first main surface S1 of the semiconductor substrate 50 and the n-type drift layer 1. The p-type termination well layer 31 in the termination region 301 is formed continuously with the p-type wiring well layer 35 in the wiring region 302. On the further outer edge side of the p-type termination well layer 31 in the termination region 301, the n+ type channel stopper layer 32 is provided between the first main surface S1 of the semiconductor substrate 50 and the n-type drift layer 1. The n+ type channel stopper layer 32 surrounds the p-type termination well layer 31. A configuration on the second main surface S2 side of the n-type drift layer 1 in the termination region 301 is similar to the configuration on the second main surface S2 side of the n-type drift layer 1 in each of the IGBT region 10 and the wiring region 302.
The termination electrode 6a and a channel stopper electrode 6b are provided on the first main surface S1 of the semiconductor substrate 50 in the termination region 301 across the interlayer insulating film 4. The channel stopper electrode 6b is electrically connected to the channel stopper layer. The emitter electrode 6 in the cell region, the wiring electrode 6c in the wiring region 302, the termination electrode 6a in the termination region 301, and the channel stopper electrode 6b are electrically connected via the semi-insulating film 33. Although the termination protective film 34 is not illustrated in
In the RC-IGBT 201, maximum depths of the p-type anode layer 25, the p-type wiring well layer 35, and the p-type termination well layer 31 are equal to or less than a depth of the p-type base layer 15. That is, the depth of the p-type base layer 15 is less than depths of the active trench gate 11, the dummy trench gate 12, the diode trench gate 21, and the wiring trench gate 36, and is equal to or more than depths of the p-type anode layer 25, the p-type wiring well layer 35, and the p-type termination well layer 31. As a result, the p-type anode layer 25, the p-type base layer 15, the p-type wiring well layer 35, and the p-type termination well layer 31 can be simultaneously formed, and manufacturing cost of the RC-IGBT 201 is significantly reduced.
In the RC-IGBT 201, an integrated concentration, which is an integrated value per unit area in a plan view seen from a top surface of a chip, of the p-type impurity concentration of the p-type anode layer 25 may be lower than an integrated concentration of the p-type base layer 15. It is possible to suppress a recovery current of a diode and accompanying energy loss without affecting withstand voltage characteristics by lowering the p-type impurity concentration of the p-type anode layer 25.
The RC-IGBT 201 may be configured such that an electric field generated when a high-voltage reverse bias is applied between the emitter electrode 6 and the collector electrode 7 is the highest in the wiring region 302. As a result, a withstand voltage can be designed and controlled in the wiring region 302 where the withstand voltage is likely to be the lowest.
In the RC-IGBT 202, a trench depth of at least one wiring trench gate 36 is shallower than trench depths of the diode trench gate 21 and the active trench gate. A withstand voltage of the RC-IGBT 202 is determined by an electric field at the bottom of the wiring trench gate 36. Therefore, when the trench depth of the wiring trench gate 36 is made shallow, an electric field in the wiring region 302 is relaxed, and the withstand voltage is secured.
In the RC-IGBT 202, the trench depth of the wiring trench gate 36 gradually decreases from the center toward the outer periphery of the semiconductor substrate 50. As a result, the electric field in the wiring region 302 is relaxed.
In the RC-IGBT 202, the wiring trench gate 36 is formed such that a trench width is narrower as the trench depth is shallower. In other words, the wiring trench gate 36 includes a first wiring trench gate and a second wiring trench gate deeper than the first wiring trench gate, and a width of the first wiring trench gate is smaller than a width of the second wiring trench gate. With such a configuration, the trench depth of the wiring trench gate 36 can be easily controlled using a loading effect of etching. Therefore, the configuration in which the trench depth of the wiring trench gate 36 gradually decreases toward the outer periphery of the semiconductor substrate 50 can be realized without a cost increase due to an additional process.
In the RC-IGBT 203, at least one pitch of the wiring trench gates 36 is narrower than a pitch of the active trench gates 11 in the IGBT region 10. A withstand voltage of the RC-IGBT 203 is determined by an electric field at the bottom of the wiring trench gate 36, and thus, when the pitch of at least some of the wiring trench gates 36 is made narrow, an electric field in the wiring region 302 is relaxed, and the withstand voltage of the RC-IGBT 203 is secured.
In the RC-IGBT 203, the pitches of the wiring trench gates 36 gradually decrease from the center toward the outer periphery of the RC-IGBT 203. The electric field in the wiring region 302 can be relaxed by gradually decreasing the pitches of the wiring trench gates 36.
In the RC-IGBT 204, the n-type carrier accumulation layer 2 is provided only in the IGBT region 10 on the first main surface S1 side of the n-type drift layer 1. As a result, it is possible to improve loss of the IGBT while suppressing a decrease in a withstand voltage due to the n-type carrier accumulation layer 2. Here, the p-type base layer 15 may have a depth less than or equal to a depth of the p-type wiring well layer 35. In other words, the p-type wiring well layer 35 may have a depth less than depths of the plurality of active trench gates 11 and more than the depth of the p-type base layer 15. Even such a structure allows simultaneous formation of the p-type anode layer 25, the p-type base layer 15, the p-type wiring well layer 35, and the p-type termination well layer 31. Thus, the manufacturing cost of the RC-IGBT 201 is significantly reduced. In the RC-IGBT 204, the n-type carrier accumulation layer 2 may be formed partly or entirely in the diode region 20.
In the RC-IGBT 205, the n-type carrier accumulation layer 2 is arranged within 1 μm from each of the active trench gate 11, the diode trench gate 21, and the wiring trench gate 36 in the IGBT region 10, the diode region 20, and the wiring region 302. Although the n-type carrier accumulation layer 2 is formed in the diode region 20 and the wiring region 302 in
In the RC-IGBT 206, the n+ type cathode layer 26 is provided on the second main surface S2 side of the n-type drift layer 1 in at least a part of the wiring region 302, that is, between the n-type buffer layer 3 and the collector electrode 7. Since the n+ type cathode layer 26 is provided in the wiring region 302 where a withstand voltage is the lowest, secondary breakdown caused by a vertical pnp structure in the wiring region 302 is suppressed. As a result, it is possible to improve the withstand voltage in the wiring region 302 and suppress breakdown during an avalanche operation.
The RC-IGBT 207 includes a p-type trench bottom layer 37 at each of the bottoms of the active trench gate 11, the dummy trench gate 12, and the wiring trench gate 36. As a result, electric fields at the bottoms of the active trench gate 11, the dummy trench gate 12, and the wiring trench gate 36 are relaxed. As a result, an electric field in the wiring region 302 is relaxed, and a withstand voltage of the RC-IGBT 207 is secured.
A top view of an RC-IGBT 208 that is a semiconductor device according to an eighth preferred embodiment is the same as illustrated in
In the RC-IGBT 208, when viewed from a top surface of a chip, the wiring trench gate 36 is arranged while maintaining a constant distance from the termination region 301. That is, the distance between the wiring trench gate 36 closest to the termination region 301 and the termination region 301 is constant in the entire circumferential direction of the semiconductor substrate 50. When the distance from the termination region 301 to the wiring trench gate 36 is maintained uniform in this manner, a depletion layer stretches uniformly, and a withstand voltage is improved.
In the RC-IGBT 208, the active trench gate 11, the dummy trench gate 12, or the diode trench gate 21 may be provided in the signal pad region 42.
In the RC-IGBT 209, an intra-cell wiring region 43 is provided to straddle the IGBT region 10 and the diode region 20. A configuration of the intra-cell wiring region 43 is similar to the configuration of the wiring region 302. The active trench gate 11 or the dummy trench gate 12 in the IGBT region 10 or the diode trench gate 21 in the diode region 20 may be arranged to extend to the intra-cell wiring region 43. In addition, the wiring trench gate 36 extending in a direction perpendicular to an extending direction of the active trench gate 11, the dummy trench gate 12, or the diode trench gate 21 may be provided in the intra-cell wiring region 43.
In the RC-IGBT 210, the p-type collector layer 16 is provided between the n-type buffer layer 3 and the collector electrode 7 in at least a part of the diode region 20.
In the RC-IGBT 210, the wiring electrode 6c in the wiring region 302 and the termination electrode 6a in the termination region 301 are connected.
In the RC-IGBT 210, a field plate (FP) electrode 6d may be provided between the termination electrode 6a and the channel stopper electrode 6b in the termination region 301. The field plate electrode 6d is opposite to the p-type termination well layer 31 across the interlayer insulating film 4. The field plate electrode 6d is electrically connected to the termination electrode 6a and the channel stopper electrode 6b via the semi-insulating film 33. The semi-insulating film 33 may be a semi-insulating single-layer film or laminated film.
Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described preferred embodiments and the like, and various modifications and substitutions can be made to the above-described preferred embodiments and the like without departing from the scope described in the claims.
Hereinafter, various aspects of the present disclosure will be collectively described as appendices.
An RC-IGBT comprising a semiconductor substrate that includes a cell region including an IGBT region and a diode region, a termination region surrounding the cell region, and a wiring region provided between the cell region and the termination region, wherein
The RC-IGBT according to Appendix 1, wherein a depth of at least one wiring trench gate of the plurality of wiring trench gates is less than the depths of the plurality of active trench gates.
The RC-IGBT according to Appendix 1 or 2, wherein depths of the plurality of wiring trench gates gradually decrease toward an outer periphery of the semiconductor substrate.
The RC-IGBT according to any one of Appendices 1 to 3, wherein the plurality of wiring trench gates include a first wiring trench gate and a second wiring trench gate deeper than the first wiring trench gate, and a width of the first wiring trench gate is smaller than a width of the second wiring trench gate.
The RC-IGBT according to any one of Appendices 1 to 4, wherein at least one pitch of the plurality of wiring trench gates is narrower than pitches of the plurality of active trench gates.
The RC-IGBT according to any one of Appendices 1 to 5, wherein pitches of the plurality of wiring trench gates decrease toward an outer periphery of the semiconductor substrate.
The RC-IGBT according to any one of Appendices 1 to 6, wherein the semiconductor substrate further includes a carrier accumulation layer provided on the drift layer on the side close to the first main surface only in the IGBT region.
The RC-IGBT according to any one of Appendices 1 to 6, wherein the semiconductor substrate further includes a carrier accumulation layer provided on the drift layer on the side close to the first main surface within 1 μm from each of the plurality of trench gates in the IGBT region, the diode region, and the wiring region.
The RC-IGBT according to any one of Appendices 1 to 8, wherein an integrated concentration, which is an integrated value per unit area in a plan view, of an impurity concentration of the anode layer is lower than the integrated concentration of the base layer.
The RC-IGBT according to any one of Appendices 1 to 9, wherein
The RC-IGBT according to any one of Appendices 1 to 10, wherein the semiconductor substrate includes a trench bottom layer of the second conductivity type at each of bottoms of the plurality of trench gates.
The RC-IGBT according to any one of Appendices 1 to 11, wherein a distance between the termination region and a wiring trench gate closest to the termination region among the plurality of wiring trench gates is constant in an entire circumferential direction of the semiconductor substrate.
An RC-IGBT comprising a semiconductor substrate that includes a cell region including an IGBT region and a diode region, a termination region surrounding the cell region, and a wiring region provided between the cell region and the termination region, wherein
The RC-IGBT according to Appendix 13, wherein
The RC-IGBT according to Appendix 13 or 14, wherein a depth of at least one wiring trench gate of the plurality of wiring trench gates is less than the depths of the plurality of active trench gates.
The RC-IGBT according to any one of Appendices 13 to 15, wherein depths of the plurality of wiring trench gates gradually decrease toward an outer periphery of the semiconductor substrate.
The RC-IGBT according to any one of Appendices 13 to 16, wherein the plurality of wiring trench gates include a first wiring trench gate and a second wiring trench gate deeper than the first wiring trench gate, and a width of the first wiring trench gate is smaller than a width of the second wiring trench gate.
The RC-IGBT according to any one of Appendices 13 to 17, wherein at least one pitch of the plurality of wiring trench gates is narrower than pitches of the plurality of active trench gates.
The RC-IGBT according to any one of Appendices 13 to 18, wherein pitches of the plurality of wiring trench gates decrease toward an outer periphery of the semiconductor substrate.
The RC-IGBT according to any one of Appendices 13 to 19, wherein an integrated concentration, which is an integrated value per unit area in a plan view, of an impurity concentration of the anode layer is lower than the integrated concentration of the base layer.
The RC-IGBT according to any one of Appendices 13 to 20, wherein
The RC-IGBT according to any one of Appendices 13 to 21, wherein the semiconductor substrate includes a trench bottom layer of the second conductivity type at each of bottoms of the plurality of trench gates.
The RC-IGBT according to any one of Appendices 13 to 22, wherein
An RC-IGBT comprising a semiconductor substrate that includes a cell region including an IGBT region and a diode region, a termination region surrounding the cell region, and a wiring region provided between the cell region and the termination region, wherein
The RC-IGBT according to Appendix 24, wherein
The RC-IGBT according to Appendix 24 or 25, wherein
The RC-IGBT according to any one of Appendices 24 to 26, wherein
The RC-IGBT according to any one of Appendices 24 to 27, wherein
The RC-IGBT according to any one of Appendices 24 to 28, wherein
The RC-IGBT according to any one of Appendices 24 to 29, wherein
The RC-IGBT according to any one of Appendices 24 to 30, wherein
The RC-IGBT according to any one of Appendices 24 to 31, wherein
The RC-IGBT according to any one of Appendices 24 to 32, wherein
While the disclosure has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised.
Number | Date | Country | Kind |
---|---|---|---|
2023-039756 | Mar 2023 | JP | national |
2023-215473 | Dec 2023 | JP | national |