Patent Application
20060288194
1. Field of the Invention
The invention relates to a real-time processor. More particularly, the invention relates to a real-time processor that controls the execution of instructions for timely implementation. In addition, the invention relates to the use of a real-time processor in controlling time critical processes employed in industrial and military applications.
2. Description of the Prior Art
As computer systems have become responsible for handling a wide variety of industrial and military applications, the underlying systems developed for these applications have become more and more complicated. With the ever-developing complexity of these systems, the time critical execution of various instructions associated with the proper implementation of these systems has become very important.
However, current off-the-shelf processors do not provide for the ability to adequately control these programs in which time critical execution of instruction is of the utmost importance. With this in mind, a need exists for a processor ensuring the execution of computer based instructions optimizing the performance of these complex systems. The present invention provides such a processor.
It is an object of the present invention to provide a real-time processor for a data processing system. The real-time processor includes a continuous clock counter, an instruction parser parsing instructions based upon whether they are a clock command or no timing specific instruction, a comparator only operating upon instruction including a clock command and a mechanism for executing a series of instruction in a timely manner based upon absolute timing of the clock counter such that events may be scheduled from the beginning of a sequence.
It is also an object of the present invention to provide a launch station test set which emulates a control system and missiles to step the launcher through a simulated launch with time critical issues. The launch station test set includes a missile launcher, a missile simulator and a real time processor as discussed above.
It is another object of the present invention to provide an engagement control system—factory test emulator which emulates precision signals issued over a serial data link, the signals and serial data link being synchronized due to serial messages such that missiles are synchronized with messages to operate in tandem. The system includes a launching system and a real time processor as discussed above.
It is another object of the present invention to provide a real-time processor for a data processing system. The real-time processor includes a continuous clock counter, an instruction parser parsing instructions based upon whether they are an input instruction, and an input operator which has the ability to execute an input instruction upon receipt of an input signal and the output operator.
Other objects and advantages of the present invention will become apparent from the following detailed description when viewed in conjunction with the accompanying drawings, which set forth certain embodiments of the invention.
The detailed embodiments of the present invention are disclosed herein. It should be understood, however, that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. Therefore, the details disclosed herein are not to be interpreted as limiting, but merely as the basis for the claims and as a basis for teaching one skilled in the art how to make and/or use the invention.
With reference to
In operation, and as discussed below in greater detail, a compiled program (executable) is loaded into the memory 15 and the instruction parser 14 begins execution of the program. As illustrated in
When a clock command is encountered, the appropriate time value is transferred to the time register 17 and the next instruction is loaded into the instruction execution unit 18. The instruction execution unit 18 is inhibited from executing the instruction by an inhibit control signal 36. When the value of the clock counter 12 matches the value of the time register 17, the clock comparator 16 de-asserts the inhibit control signal 36.
The present real-time processor 10 is synchronized to an oscillator 30. Appropriate distribution of the oscillator signal 32 allows the instruction parser 14 and other units to operate properly. The oscillator scaler 13 allows the clock counter 12 to operate on time intervals shorter than the primary oscillator frequency. The oscillator scaler 13 allows the clock counter 12 to increment on the proper time intervals by controlling the counter enable signal 34. The oscillator scaler 13 may be controlled by special instructions stored in the memory 15 and interpreted by the instruction parser 14. Oscillator scaling instructions are expressly anticipated for future implementations so that the timing interval may be dynamically adjusted.
The clock counter 12, or master clock, in accordance with a preferred embodiment of the present invention, works in conjunction with the instruction parser 14, clock comparator 16, time register 17, and instruction execution mechanism 18 so the instructions are executed at exactly the time specified in accordance with the instructions. The clock counter 12 is incremented under the control of the oscillator scaler 13 on specific time intervals, for example, seconds, milliseconds or microseconds, and the clock commands are, therefore, incremented with the specific time intervals considered by the clock counter 12.
In practice, the clock counter 12 counts “ticks” generated by the oscillator 30 when enabled by the oscillator scaler 13 via the counter enable signal 34 and translates these “ticks” into a count time based upon predetermined increments applied in accordance with specific functions for which the present processor 10 is applied. This method is basically the same as scaling the oscillator signal 32, but allows for a more synchronous system as is commonly practiced in high speed digital electronics today. Dividing the oscillator frequency and providing this slower oscillator to the clock input of the clock counter 12 would provide the same effect but is slightly less synchronous and can cause problems at high oscillator frequencies.
For instance, if the clock counter 12 is to increment in milliseconds, the oscillator scaler 13 provides a counter enable signal (or oscillator scaler output) 34 once every millisecond allowing the clock counter 12 to count an oscillator “tick” generated each millisecond by the oscillator 30. This counting will be used to identify the passage of milliseconds and the clock commands employed in the instruction set will be incremented in milliseconds.
Operation of the present real-time processor is enhanced by the ability to set the oscillator scaler 13 from a program instruction as discussed above. The oscillator scaler 13 allows the clock counter 12 to increment on the proper time intervals by controlling the counter enable signal 34. The oscillator scaler 13 may be controlled by special instructions stored in the memory 15 and interpreted by the instruction parser 14. Oscillator scaling instructions are expressly anticipated for future implementations so that the timing interval may be dynamically adjusted.
As will be discussed below in greater detail, the clock counter 12 operates continuously to provide for absolute time during the execution of a series of instructions. That is, the clock counter 12 starts at some “Time 0” and all clock command and/or delay command instructions are thereafter referenced exactly to “Time 0.” As is discussed below in greater detail, the present processor 10 only resets the clock counter 12 at the beginning of long sequences or at the beginning of a loop iteration under the specific control of the “WRITE_Clock” command. Due to this, the present real-time processor 10 utilizes absolute timing so that events can be scheduled exactly from the beginning of a sequence or the beginning of a loop iteration. The present real-time processor 10 allows for the explicit reset of the clock counter 12 and only resets the clock counter 12 when explicitly commanded.
Further, because of the implementation of the oscillator scaler 13, the clock counter 12 always remains synchronized to the specific time increment that is being used. When a “WRITE_Clock” instruction is encountered by the instruction parser 14, the instruction parser 14, operating at the frequency of the fast oscillator signal 32, writes the new counter value to the clock counter 12 and the clock counter 12 will still increment at the proper interval of time. Because of this, iterative loops of operations can be performed with exact timing in reference to each other.
In
As illustrated in
Next the “WRITE_clock 0” instruction is immediately executed, causing the value of the clock counter 12 to change to 0. At the next point in time when the oscillator scaler output 34 is true, the value of the clock counter 12 increments to 1. Counter incrementing is kept uniform by the oscillator scaler output 34 regardless of other instructions executed and the interval between each clock increment is always uniform as indicated by the Interval X dimension in
As soon as the “WRITE_clock 0” instruction has been parsed, the next clock command (that is, “CLOCK 2”) is parsed. Because of the parsing of the “CLOCK 2” instruction, the value in the time register 17 is changed to 2 and the execution inhibit control signal 36 is activated. Now the “PTT OFF” instruction is parsed by loading the appropriate values into the instruction execution unit 18. Again, the instruction execution unit 18 performs no action at this time because of the execution inhibit control signal 36.
When the clock counter 12 value and the time register 17 values become equal (both equal to 2 in this example) the clock comparator 16 clears (de-asserts) the execution inhibit control signal 36 allowing the instruction execution unit 18 to immediately execute the “PTT OFF” instruction which has already been loaded into its registers.
The program segment and its execution described above demonstrate how the present real-time processor 10 executes instructions in an extremely timing accurate manner. This also demonstrates how a program loop can be constructed to repeatedly generate a precision signal for testing purposes or repeat a precision sequence of events for automation purposes.
As discussed above, the real-time processor 10 includes an instruction parser 14 parsing instructions based upon whether they include a clock command, a delay command or no timing specific instruction. With this in mind, the programmed instruction sets utilized in conjunction with the present real-time processor 10 may be provided with various commands including a clock command and/or a delay command. Clock commands are used to designate an absolute time at which the associated instruction should be executed by the processor 10. When a clock command is issued in conjunction with an executable instruction, the next following instruction is fetched from the memory 15 and prepared for execution. At this point, instruction execution is suspended until the clock counter 12 reaches the time specified in the clock command. As discussed above, when the clock counter 12 reaches the appropriate time, instruction execution is extremely fast and accurately timed due to the pre-fetching of the instruction.
The delay command allows for close synchronization to asynchronous events. When a delay command is encountered, the execution of the program is suspended for approximately the length of time indicated by the delay command. For instance, when a “Delay 100” instruction (that is, the delay command) is encountered, the real-time processor 10 inserts 100 clock counter 12 cycles of delay.
This is accomplished in the following manner. When the delay command is parsed, a value is loaded into the time register 17 that is equal to the present value in the clock counter 12 plus the value of the delay increment and the execution inhibit control signal 36 is asserted. As those skilled in the art will certainly appreciate, the process of adding the delay value from the instruction to the counter value is easily accomplished in the instruction parser 14 with a digital adder (not shown) of appropriate size for the two values. This process is easily accomplished in programmable logic or in hard silicon and easily designed using either schematic techniques or hardware description language. The next instruction is parsed to the instruction execution unit 18 just as in the case of the clock command.
When the clock comparator 16 determines that the value in the clock counter 12 equals the value in the time register 17, the instruction inhibit control signal 36 is de-asserted and the parsed instruction waiting in the instruction execution unit 18 is allowed to execute.
The utility of the delay command is related to timely reaction to external events. In accordance with a preferred embodiment of the present invention, the real-time processor 10 includes an input operator 11. There are various input functions and instructions designed into the two existing implementations. Some of these operate on parallel data (or single event inputs) and some of these operate on serial data or multiple event data streams.
When the instruction parser 14 decodes an “INPUT” instruction, the instruction execution unit 18 loads information on the expected input into the input operator 11. The input information includes details on what input signal(s) the input is expected on, whether any change or a specific value is expected, and how long to wait for the input event. The input operator 11 includes its own mechanism for comparing a target time against the clock counter 12 and thereby providing a timing window during which the input event is expected. This function is implemented with a time register 44 and comparator 46 within the input operator 11 similar to time register 17 and clock comparator 16. The comparator 46 in the input operator 16 also compares its respective time register 44 to the clock counter 12. This mechanism allows the input operator 11 to recognize a “time window” and to “look” for an input (incoming event) during a specific time window. If the event occurs during the specified window, the program execution continues to the next instruction. If the event does not occur during the window, the program branches to an alternative execution path.
In the event that the input operator 11 detects the proper input during the time window specified, the program can execute a delay command that responds to the input in a precisely timed manner. The input could be an indication of the position of an object and the delayed command a mechanical operation timed to precisely operate on the object based on the timing of the input. The input could also be a communication message and the delayed response could be a responding message, precisely timed to emulate an actual response. The present implementations utilize both of these example cases.
The following example is presented for understanding and demonstrating the delay command and the input and output instructions.
This program segment is executed with a successful input as illustrated in
After the execution of other instructions, the instruction parser 14 fetches and parses the instruction “CLOCK 10”. In keeping with the established operation of the clock command, the execution inhibit control signal 36 is asserted and the time register 17 is loaded with the value “10”. The “INPUT” instruction is then immediately fetched from memory 15 and parsed by loading the appropriate values into the instruction execution unit 18 and the input operator 11. When the “INPUT” instruction is parsed, the input feedback signals 38 are set to 00 (cleared from whatever value they may have held from a previous operation). As discussed previously, the “INPUT” instruction is not executed until the clock counter 12 reaches count value 10. When the clock counter 12 reaches count value 10, the clock comparator 16 de-asserts the execution inhibit control signal 36 and the “INPUT” instruction commences. The instruction parser 14 does not fetch any other instructions until the result of the “INPUT” operation is established.
When the Input Signal X 40 matches the expected value, the input operator 11 provides input feedback 38. The input feedback 38 may be as many or as few signals as required to communicate the input results. In the implementation described here, two input feedback terms are used, the most significant bit indicates that the input function has completed; the least significant bit indicates that the input is the expected value. Sometime during counter cycle 15, the input achieves the expected state and the input operator 11 provides input feedback 38 to the instruction parser 14.
After the instruction parser 14 receives the input feedback 38, the next instruction (“Delay 10”) is fetched from memory 15. The “Delay 10” instruction is parsed and executed which causes the execution inhibit control signal 36 to be asserted and the value 25 (clock counter 12 value plus delay value) to be loaded into the time register 17. It is contemplated the delay command may also be designed to load a value equal to the clock counter 12 value plus the delay value plus some constant. The constant may be equal to one to adjust the accuracy tolerance of the delay command. Additionally, the delay command may add the delay value times some constant to the clock counter 12 value in order to scale the function. The operation of the delay command is identical to the operation of the clock command after this point.
The instruction parser 14 now fetches and parses the “Output” function based on the successful outcome of the “INPUT” instruction. The appropriate values for the “Output” function are loaded into the instruction execution unit 18 and the output operator 19 but execution does not proceed due to the execution inhibit control signal 36. When the clock comparator 16 determines that the clock counter 12 matches the time register 17 value 25, the execution inhibit control signal 36 is de-asserted and the “Output” instruction executes forcing the output bus Z 42 to the hexadecimal value 0x7A. Next, the “Write clock 0” instruction is fetched, parsed, and executed so that the clock counter 12 exhibits a count value of 1 at the next count increment.
As demonstrated here, the delay command allows the present real-time processor 10 to produce responses to events (outputs) with precise timing relationship to external events (inputs). In the example shown with reference to
The event or timing window of the “INPUT” function is implemented with a time register 44 and comparator 46 within the input operator 11 similar to time register 17 and clock comparator 16. The comparator 46 in the input operator 11 also compares its respective time register 44 to the clock counter 12. The input operator time register 44 is loaded with a value equal to the time register 17 value plus the “WAIT” value (11 for this example). The input operator time register 44 can be loaded when the “INPUT” instruction is parsed since the value in the time register 17 indicates the time the instruction will begin. The value in the input operator time register 44 indicates the time that the event window will expire. When the clock counter 12 reaches a value 21, the “INPUT” function terminates due to the expiration of the event window. When the event window expires, the instruction is said to have “timed out”. Because of the “timed out” situation without an acceptable input, the input operator 11 produces input feedback 38 of value 10. The most significant bit indicates that the “INPUT” function has terminated, the least significant bit (a zero in this case) indicates that the expected input did not occur.
Based on the input feedback 38 values, the instruction parser 14 requests the instruction stored at the memory location indicated by the “XFAIL” pointer. In this implementation of the “INPUT” instruction, the “BRANCH” pointer is taken on an instruction failure (“BRANCH” on fail). The instruction branched to is a “CLOCK 25” instruction which will inhibit the next instruction from executing until the clock counter 12 reaches a value of 25. It is significant to note that in the case of a missed input, the counter value need not be reset; the system is still synchronized.
The “CLOCK 25” instruction is fetched from memory 15 and parsed by instruction parser 14 which includes asserting execution inhibit control signal 36 and loading the value 25 into time register 17. Next the “Output” instruction is fetched from memory 15 and parsed by instruction parser 14. The appropriate values are loaded into the instruction execution unit 18 and output operator 19 but execution is inhibited. When the clock comparator 16 determines that the clock counter 12 value matches the time register 17 value, the execution inhibit control signal 36 is de-asserted and the value 0x80 is output on output bus Z 42.
As briefly discussed above, the timely fetching and execution of instructions is achieved by a clock comparator 16 only operating upon instructions including a clock command or a delay command and an execution mechanism 18 for executing a series of instructions in a timely manner based upon absolute timing of the clock counter 12 such that events may be scheduled from the beginning of a sequence.
The preferred syntax employed when specifying a clock command in accordance with the present invention is as follows:
An example of executable instructions in conjunction with the present processor is presented below with reference to
Referring to
Instructions are implemented sequentially (just like a typical processor) until the next clock command occurs (in this case “CLOCK 2”) at which point the processor 10 fetches the next instruction from memory 15 and places the appropriate values in the processor registers (as described in detail earlier). Instruction execution is again suspended until the clock counter 12 reaches the appropriate time (“CLOCK 2” or 2 milliseconds in this example).
The “wRITEclock” command at “Clock 1600” resets the clock counter 12 and the “READloop” instruction serves as a loop that forces execution back to the point indicated by “LABEL1:”. In this manner, a highly repetitive operation can be easily implemented. In the system implemented in these examples, most of the instructions are real world output and input. For example, PTT (Push To Talk), a single event output, turns on an open collector switch; LAMS and SYNC instructions output detailed serial data packets.
Both of the existing implementations of this processor are realized in field programmable gate arrays (FPGA), although the present processor may be implemented in various programmable logic devices. In addition, the present real-time processor is implemented using various Hardware Descriptive Languages, for example, AHDL and VHDL, although other programming languages or schematic design technique may be used without departing from the spirit of the present invention.
In accordance with a preferred embodiment of the present invention, the real-time processors 10 of the present invention utilize a PC 24 to compile the instruction sequences (programs) into machine code. The compiled program (executable) is transferred from the PC 24 to the present real-time processor 10 and stored in memory 15 until the PC 24 instructs the real-time processor 10 to execute the program. As those skilled in the art will certainly appreciate, these components making up the present system may be separate or integrated into a single housing. The various implementations differ in the various input and output functions that are implemented, but they are identical in the use and implementation of the clock and delay command.
In accordance with a preferred embodiment of the present invention, the clock command is implemented using a clock comparator 16 employing a time register 17 that is loaded with the value from the clock command. The value in the time register 17 is compared to the current value of the clock counter 12. When the values match (as indicated by the clock comparator 16), a control signal 36 is exerted that allows the execution of the suspended instruction to proceed. This simple implementation allows for extremely accurate timing of signals for real time interfaces such as factory automation and emulation of real world hardware for test purposes.
As mentioned above and in accordance with a preferred embodiment of the present invention, operation of the present processor is achieved using Hardware Description Languages. The implementations described below are both achieved using AHDL (Altera Hardware Description Language). In accordance with a first embodiment (that is, the fist processor used in a Launch Station Test Set (LSTS)), it was implemented in an Altera 10K50 FPGA. The second embodiment (that is, the second processor used in an Engagement Control System—Factory Test Emulator (ECS FTE)) was implemented in an Altera Cyclone FPGA.
In practice, the implementations achieved through use of the present real-time processor 10 apply to equipment tested by interfacing with signals that must accurately emulate timing critical functions. For example, and with reference to
An example of an instruction set for use in conjunction with the Launch Station Test Set is present below. In this example the following instructions apply:
#—comment delimiter.
A second embodiment employs the real time processor 10 in an Engagement Control System—Factory Test Emulator 200 (see
In accordance with preferred embodiments of the systems discussed above, the Launch Station Test Set 100 uses 10-millisecond timing for the clock counter 12 and the Engagement Control System—Factory Test Emulator 200 uses 1-millisecond timing for the clock counter 12.
While those skilled in the art will appreciate that various functions and instructions may be employed in accordance with the present invention, the following presents an overview allowing for implementation of the present real-time processor:
The ECS Sequencer has LAM/LRM (Launcher Response Message) Capability. All Sequences begin execution at Address 0x0.
I. Function Types—each of these functions can be executed at a specified time during a test sequence.
28-bit 1 millisecond counter allows a 74 hour test with no loops (clock resets).
Test Script Example:
B. WRITE Clock—allows a specific time to be written to the ECS Test Time Counter register so that a branch allows timing to continue operating correctly.
C. DELAY—Causes a specified delay.
When executed, the DELAY instruction will cause Sequencer execution to suspend for the specified duration of time (in addition to the time remaining in the present, one-millisecond period). It should be further understood that external events are asynchronous and, when received into the system and registered or synchronized by the system, will always have an uncertainty of between 0 and 1 time periods. It is contemplated future implementations of the Delay instruction will determine in which half of the time period the instruction was executed and automatically adjust the delay by adding either 0 or 1 time period thereby always achieving the exact, specified delay in a repeatable fashion.
Test Script Example, occurring at Test Time 5-milliseconds:
DELAY 100 # [mnemonic 0xF8000064]
In the test script example, the DELAY instruction was encountered during the 5-millisecond period of sequence execution, and therefore delayed until the present 5-millisecond Test Time period ended.
D. WRITEADDRESS—Changes the value of the Sequencer Address Register. This causes Sequencer execution to unconditionally continue at the specified address, which can be a label or a hex value in the Sequencer's address space (not global address space).
E. WRITE Loop—changes the value of the Loop Counter Register.
Using the WRITE Loop function to write a zero to the Loop Register is considered an illegal action and should be prohibited by the Sequence Compiler.
The LRM Function explicitly expects either an RF or FO LRM. This is determined by the RF/FO bit in Data Word 8. If RF/FO=0, the expected LRM is FO; If RF/FO=1, the expected LRM is RF.
G. PTT—outputs the RF Push To Talk function. Writing a 1 to this register activates PTT, writing 0 de-activates PTT.
Test Script Example:
H. READ Loop—Checks the Loop register for a zero value. A non-zero value is considered a “BRANCH on FAIL” condition causing the function to load the Address register with the value stored in the data bits and forcing the sequencer to begin execution at the indicated address. When a READ Loop is executed, the Loop register is automatically decremented.
H. READ Status—Checks the Status register for a predetermined value.
Test Script Example:
I. CLR Status—Clears the status register so that no status data may be checked.
J. END—Stops sequencer execution. Clears ECS_Sequencer_Active signal.
K. LAMD—Dual LAM. The LAM functions utilize indirect addressing to simplify implementation. Because of this, the mnemonic does not represent the instruction. All of the data sent by the LAM generator is stored at the address specified in the mnemonic. The complete LAM (with the exception of the FO “time of day” word) is generated by the software residing on the PC.
L. LAMS—Single LAM. The LAM functions utilize indirect addressing to simplify implementation. Because of this, the mnemonic does not represent the instruction. The detailed LAM data is stored at the address specified in the mnemonic.
M. REPORT—Sends a predefined message word back to the PC.
N. Data Word—All Data words in each function begin with a zero nibble. A word with a non-zero Most Significant Nibble, indicates a Function word.
While the preferred embodiments have been shown and described, it will be understood that there is no intent to limit the invention by such disclosure, but rather, it is intended to cover all modifications and alternate constructions falling within the spirit and scope of the invention as defined in the appended claims.
This application is based upon U.S. Provisional Patent Application Ser. No. 60/691,242, filed Jun. 17, 2005, entitled “REAL-TIME PROCESSOR”.
| Number | Date | Country | |
|---|---|---|---|
| 60691242 | Jun 2005 | US |
