The present invention relates to semiconductor devices and in particular to nanowire semiconductor devices.
Conventionally, electrical contacts for axial nanowire devices are made by encapsulating the nanowires in an insulator and then etching the insulator to expose the tops of each wire. A conducting material is then deposited to make the electrical contacts to the nanowires.
The present inventors observed that 1×1 mm2 prior art InP nanowire solar cells have an average open circuit voltage, Voc, which is significantly lower (500-700 mV) than what would be expected from an ideal InP solar cell (900 mV). In addition to the lower average Voc of the nanowire solar cells, the spread in Voc is typically large, with a standard deviation of several 100 mV. Thus, nanowire solar cells with a higher open circuit voltage and a small spread in open circuit voltage are desired.
An embodiment relates to a semiconductor nanowire device which includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor nanowire is dominated by the contact to the top surface of the semiconductor nanowire.
Another embodiment relates to semiconductor nanowire device comprising at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire and extends above the top surface of the nanowire to create a recess between a sidewall of the insulating material and the top surface of the nanowire, and an electrode filling the recess and ohmically contacting the top surface of the nanowire.
Another embodiment relates to a method of making a semiconductor nanowire device, comprising forming at least one semiconductor nanowire, the semiconductor nanowire having a catalyst particle on a top surface of the semiconductor nanowire or a sacrificial portion comprising the top surface, forming an insulating material around the semiconductor nanowire, removing the catalyst particle or the sacrificial portion to recess the top surface of the nanowire below a top surface of the insulating material, and forming an electrode in ohmic contact with the top surface of the nanowire.
For the purposes of this application, nanowires are nanoscale structures that have a diameter (for cylindrical nanowires) or width (for non-cylindrical nanowires, such as nanowires having a hexagonal cross sectional shape in a plane perpendicular to its axis) less than 1 micron, such as 2-500 nm such as 100-300 nm. The length, however, may be at least 0.5 microns, such as 0.5 to 3 microns, such as 1 to 2 microns.
Efficient solar cells made from Group IV or III-V materials, such as but not limited to Si, InP and GaAs, have the pn-junction very close to the top surface. Preferably, the pn-junction is on the order of only a few 100 nm from the top of the surface. This is also true for semiconductor nanowire devices. Both modeling and experiment indicate that the most efficient semiconductor nanowire solar cells have a wire diameter of at least 180 nm. Thus, from a contacting perspective, the semiconductor nanowire may be viewed as a small piece of planar material.
To make optoelectric devices from arrays of semiconductor nanowires, such as LEDs or solar cells, the top contact preferably incorporates a transparent conducting oxide (TCO). The contact between the TCO and the active device preferably has as low resistance as possible, and is preferably ohmic. In the case of solar cells, it is also preferable that the contact itself not be optically active, i.e., the contact should not subtract from the open circuit voltage (Voc) of the device.
In the case of semiconductor nanowires grown from metal catalysts, such as Au, the conventional wisdom is that the Au seed particle is advantageous for forming an ohmic contact to the nanowires. Therefore, the Au particle is typically not removed, especially since removal would require additional processing steps. However, metal catalyst seed particles are known to reduce efficiency because of light shading. In addition to light shading and in contrast to conventional wisdom, an integrated metal particle may also provide poor electrical contact. Au has been found to make a Schottky-type contact to III-V semiconductors. The Schottky-type contact shows up in the current-voltage characteristics as a reverse diode in addition to any diode that may exist in the semiconductor nanowire. Therefore, the total device typically includes the semiconductor nanowire diode in series with a reverse Schottky diode as illustrated in
Additionally, an insulating or dielectric layer surrounds at least a portion of the sidewalls of the semiconductor nanowire 101, thereby forming an insulating shell 108 around the semiconductor nanowire 101. In an embodiment, the insulating shell 108 is made of a transparent material, such as SiO2. If the semiconductor nanowire 101 is grown by the VLS process, or another process using metal catalyst particles, such as the Aerotaxy™ process (as described in PCT Published Application WO 11/142,717 (the '717 publication), assigned to Qunano AB and hereby incorporated by reference in its entirety), the metal catalyst particle 106 is located on top of the second portion 104 of the semiconductor nanowire 101.
As discussed above, a reverse Schottky diode 122 may be formed between the metal catalyst particle 106 and the second portion 104 of the semiconductor nanowire 101. The TCO electrode 110 encapsulates the semiconductor nanowire 101, including the insulating shell 108. In those portions of the semiconductor nanowire 101 that are not covered by the insulating shell 108, direct contact may be made between the TCO electrode 110 and the semiconductor nanowire 101. This contact is typically ohmic as illustrated by symbol 124. An additional ohmic contact may be formed between the metal catalyst particle 106 and the TCO electrode 110 as indicated by symbol 126. The ohmic contact connection 124 is in parallel with the gold particle—nanowire Schottky connection 122. Alternatively, this contact may form another Schottky diode with different electrical characteristics from the diode 120 or the reverse Schottky diode 122.
In one aspect of the first embodiment, the semiconductor nanowire 101 has a diameter or width and the TCO electrode 110 contacts a side portion 101b of the semiconductor nanowire 101 below the top surface 101a such that the length Δh1 of the side portion 101b is less than the diameter/width 101c of the semiconductor nanowire 101. For example, diameter/width 101c may be 10% to 500% greater, such as 50-100% greater than the length Δh1 of the side portion 101b. In another aspect of the first embodiment, Δh1 equals to zero and no side portion of the nanowire is exposed by the shell 108, such that the nanowire and the shell have about the same height. In this configuration, the electrode 110 contacts only (exclusively) the top surface 101a of the nanowire but not the side portion 101b of the nanowire.
Thus, in the first embodiment, the electrode 110 contact to the semiconductor material of the nanowire is dominated by the contact to the top surface 101a where Δh1 is less than a diameter or width 101c of the top surface 101a of the nanowire 101 (i.e., where Δh1=0, or 0<Δh1<101c in the first embodiment).
To allow for process variations, including uneven nanowire height, a longer side portion 101b of the nanowire is exposed than would otherwise be necessary so as not to accidentally leave some nanowires uncontacted. Thus, when the top electrical contact/electrode 110 is formed, varying portions of the nanowire tips make contact with the electrode 101. That is, the top electrode 110 is formed along longer side portions 101b in the longer nanowires than in the shorter nanowires (where Δh1 may equal to zero in shorter nanowires and the electrode 110 only contacts the top surface 101a). The difference in the contact area between longer and shorter nanowires to the electrode 110 leads to undesirable non-uniformity in output and performance between different nanowires in the same device.
Thus, the electrode contact with the nanowires 101 is preferably made only to the top surface of each semiconductor nanowire 101, or with as little as possible contact to the side of the semiconductor nanowire 101, as described above. Further, a benefit of allowing the insulating shell 108 to extend above the top end of the semiconductor nanowire 101 in the final device structure reduces the influence of process variations either due to varying nanowire length or to other process variations. The structure illustrated in
As illustrated in
Specifically,
Experimental results from 1×1 mm2 InP nanowire solar cells show that when Au catalyst particles 106 are present on the nanowires 101, the average Voc is significantly lower (500-700 mV) than that of standard planar InP solar cells (880 mV). In addition to the lower average Voc, the spread in Voc is typically large, with a standard deviation of several 100 mV.
The main contribution to the improvement in efficiency is believed to be due to the higher Voc, where the device of the embodiments also exhibits a smaller spread Voc, indicating a more homogeneous contact. A second source of improvement is the improvement in the short circuit current Jsc. This improvement is expected due to the lower shading and reflectivity of the device, illustrated in
Alternatively, as-grown nanowires may be deposited on the support as follows. The nanowires are grown in the gas or vapor phase using the catalyst nanoparticles by the Aerotaxy™ process (as described in the above noted PCT Published Application WO 11/142,717). The collected nanowires are then positioned on the support 100, such as a semiconductor, conductive (e.g. metal) or insulating (e.g., glass, ceramic or plastic) substrate. The nanowires may be aligned with their axes substantially perpendicular to the top surface of the underlying support by any suitable method.
For example, the nanowires may be aligned by selective chemical functionalization. Specifically, the method includes selectively functionalizing portions (e.g., first portions 102) of the nanowires 101 with a charged organic functionalizing compound, dispersing the plurality of nanowires in a polar or semi-polar solvent, and aligning the nanowires 101 on a support 100 such that longitudinal axes of the nanowires are oriented substantially perpendicular to a major surface of the support. The major surface of the support 100 may also be functionalized with an organic attachment ligand which forms a binding pair with the functionalizing compound, typically by forming a covalent bond. That is, the functionalizing compound covalently binds to the attachment ligand to fix the plurality of nanowires to the support.
Alternatively, the nanowires may be aligned by applying an electric field over the population of nanowires, whereby an electric polarization in the nanowires makes them align along the electrical field, as described in PCT Published Application WO 11/078,780 published on Jun. 30, 2011 and its U.S. national stage application Ser. No. 13/518,259, both of which are incorporated herein by reference in their entirety. Preferably the nanowires are dispersed in a fluid (gas or liquid) during the steps of providing and aligning over the support. In addition to the polarization to make the nanowires align in the electric field, an optional electric dipole may be induced in the pn junction containing nanowires to provide further directionality and to enhance the nanowire alignment by illuminating the nanowires with radiation (e.g., visible light) during alignment, effectively inducing an open circuit photo voltage between the ends of the nanowires.
Preferably, the nanowires 101d, 101e include a first portion 102 having a first conductivity type (e.g., p-type) and a second portion 104 having a second conductivity type (e.g., n-type). If desired, each portion may comprise two or more sub-regions. For example, the second portion may contain a heavily doped upper sub-region (e.g., n+) and a lower lighter or lightly doped lower sub-region (e.g., n or n−) adjacent to the pn junction 103. Each sub-region may be 75-150 nm in length (i.e., in a direction parallel to axis of nanowire).
If the lower sub-region is intrinsic, then the device includes a p-i-n junction instead of a pn junction 103. The pn junction 103 preferably extends parallel to a major surface of the support (e.g., substrate) 100 and perpendicular to the nanowire axis. The pn junction is preferably located within 300 nm of the top surface of the semiconductor nanowires 101d, 101e.
As illustrated in
Next, as illustrated in
If the ALD process is used to form the insulating shell 108 and the insulating shell 108 is made of SiO2, the precursors for ALD deposition may be Tris(tert-butoxy)silanol (TTBS) and Trimethylaluminum (TMAl). TTBS and TMAl may be pulsed into the reaction chamber containing the nanowire devices. Preferably, the reaction chamber is heated. The TTBS and TMAl chemisorb to the heated nanowires 101d, 101e and form a thin conformal layer of SiO2. Excess precursor and ligands/molecules may be removed by purging the chamber with N2. In an embodiment, the base pressure in the reaction chamber is 2 mTorr and the temperature is 255° C. In an embodiment, the ALD SiO2 process is conducted by performing of 3 pulses of TTBS followed by 1 pulse of TMAl. This process may be repeated as desired to achieve the desired layer thickness. For example, the process may be repeated 20-24 times to get a desired thickness of 50 nm SiO2 around the NWs. The number of pulses may be increased or decreased to produce thicker or thinner insulating shells 108.
In addition to the ALD process, other method of coating/passivating the nanowires may be used, such as spin-on-glass, plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), curing of tetraethyl orthosilicate (TEOS) and sputtering. In addition to SiO2, other suitable insulating/passivating materials include polymers, such as benzocyclobutene (BCB), Al2O3 and HfOx.
Next, as illustrated in
Next, as shown in
To open up and expose the nanowire tips for contact formation, any suitable etching technique may be used, such as reactive ion etching (RIE). In an embodiment, RIE is performed with a gas mixture of CF4, CHF3 and Ar, at flow rates of 5-50 sccm, such as 20, 20 and 10 sccm, respectively. In an embodiment, RIE may be performed with a RF plasma power of 200-300 W, such as 250 W at a pressure of 200-400 mTorr, such as 300 mTorr. The highly anisotropic nature of the RIE results in preferential etching of the insulating shell 108 on top of the nanowires 101d, 101e. The RIE parameters may be varied as desired. In an alternative embodiment, wet etching is used instead of RIE. Wet etching may be used by controlling the etch rate and the thickness of the sacrificial layer 502.
Next, as shown in
For GaAs nanowires, a cyanide-based etch may be used to remove the catalyst particles 106. In an embodiment, the cyanide etch includes the following steps:
For nanowires grown from seed particles other than Au (e.g., Cu, Ag, Al, Fe, Ni, In, Ga, and their alloys, including alloys with Au) other etch chemistries may be used.
As illustrated in
Next, as illustrated in
In an alternative embodiment shown in
The process then proceeds as described above with respect to
Optionally, both the top electrode 110 and the bottom electrode 510 contact to the nanowires 101 may be made using the method described above with respect to
As shown in
Then, openings 113 are formed in the growth mask 111. The openings are preferably well controlled, both in regards to their diameter and their relative positioning. Several techniques known in the art can be used for the procedure including, but not limited to lithography, such as electron beam lithography (EBL), nanoimprint lithography, optical lithography, followed by etching, such as reactive ion etching (RIE) or wet chemical etching methods. Preferably the openings have approximately the same diameter as the nanowire 101 diameter 101c (e.g., 500 nm or less), and pitched 0.5-5 μm apart. The openings define the position and the diameter 101c of the nanowires 101 to be produced.
Then, as shown in
The process of the third embodiment then continues in the same manner as in
In another embodiment, the semiconductor nanowire is grown using the catalyst particle using one of the methods described above, and both the sacrificial portion (e.g., sacrificial region) 116 of the nanowire and the catalyst particle are later removed. In one non-limiting aspect of this embodiment, a GaAs core-shell nanowire comprised of an axial GaAs nanowre core and radial AlGaAs cladding layer(s) is grown using a catalyst particle. This is followed by growing a sacrificial Si, InP or InAs region 116. Then, as described above, both the catalyst particle and the sacrificial region are removed. The sacrificial region may be selectively removed using any suitable etching medium, such as HCl for InP, NH4OH for InAs or KOH for Si at the later stage in the process to provide a deeper recess than with just removing the catalyst particle alone.
Although the foregoing refers to particular preferred embodiments, it will be understood that the invention is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the invention. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
The present application is a divisional of U.S. application Ser. No. 13/723,413 filed on Dec. 21, 2012, which is incorporated herein by reference in its entirety.
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Child | 14671666 | US |