Patent Grant
7152027
The present invention relates to the field of test and measurement, and in particular, to a test system which provides reconfigurable testing of a wide variety of test devices.
Product testing is in many ways essential to the successful development of new products and the refinement of existing products. The type of testing applied to a product is likely to evolve as the product itself matures from an initial prototype to a marketable system. For a product which is ready for mass production, it is quite typical for the product manufacturer to design dedicated test instruments for testing the product and/or its subsystems. A test instrument often includes dedicated hardware which is especially adapted for the target unit under test or UUT (i.e., the device which is to be tested) and/or for the specific series of test procedures to be applied to the target UUT. Such a test instrument is generally useless for testing devices apart from the target UUT (or set of UUTs) for which it was designed. Furthermore, a test instrument typically looses it utility when its target UUT is modified, or when the test procedures to be applied to the target UUT require alteration. The costs associated with redesigning the test instrument for the modified target UUT or for the updated test procedures contributes significantly to the overall cost of the product.
The telecommunication industry is a prime example of an industry which suffers from the rapid obsolescence of test systems. The telecommunication industry has expanded rapidly in response to improvements in device technologies and escalating public demand for telecommunication services. This expansion can be measured by the number of new telecommunication products/devices marketed each year. In order to test and validate a telecommunication device, manufacturers may rely on a test system which has been custom designed for the telecommunication device.
Consider the example of cellular phone technology. Cellular phones are quite typically designed with an RF transceiver card and a controller card which communicate with one another via a serial bus. One prior art solution for testing cellular phones involves the use of a specialized hardware test board. The hardware test board couples to a card which is to be tested, and emulates the complementary card. The hardware test board is typically connected to a host computer. A software program running on the host computer controls and monitors a test procedure which is implemented by the hardware test board. Because the hardware test board typically includes dedicated hardware adapted for communicating with the card under test, its utility may come to an end when the card under test is modified. The time required to redesign a hardware test board is a burden on the development cycle of new products, and contributes significantly to the end cost of these products.
Thus, there exists a substantial need for a test system with reconfigurable hardware which could rapidly and inexpensively adapt to changes in a target UUT, or changes in the test procedures to be applied to the target UUT. Similarly, there exists a significant need for a test system with reconfigurable hardware which could be rapidly and inexpensively modified to support any desired target UUT and any desired set of test procedures.
Another problem inherent in telecommunication testing is the proliferation of telecommunication protocols. Manufacturers of test systems attempt to provide support for any existing telecommunication protocols that are likely to be of interest to their customers. Because test systems quite often commit the details of protocol handling to dedicated hardware, test systems quickly become useless or obsolete when new protocols emerge. In addition, telecommunication companies utilize many internal communication standards which are proprietary. Such companies may be forced to design their own test system for testing products conforming to the internal standards. Thus, there is a profound need for a test system with reconfigurable hardware which may be rapidly configured to handle any desired communication protocol.
The problems outlined above are largely resolved by the reconfigurable test system and method of the present invention. The reconfigurable test system includes a host computer coupled to a reconfigurable test instrument (RTI). The RTI is configured for coupling to a unit under test through a communication medium. The RTI preferably includes a reconfigurable hardware module, a reconfigurable front end, and optionally an embedded processor with local memory. The reconfigurable hardware module preferably includes one or more reconfigurable or programmable hardware devices such as Field Programmable Gate Arrays (FPGAs). Thus, the reconfigurable hardware module may be programmed to realize any desired hardware architecture. The reconfigurable front end preferably includes programmable transceivers which may be programmed to interface with any desired types of signals using any desired line encoding scheme, voltage levels, etc. If an embedded processor is present on the RTI, an additional measure of programmability is afforded by appropriate selection of the embedded instruction code to be executed by the embedded processor.
Because of the combination of reconfigurable technologies incorporated in the RTI, the RTI may be programmed to operate with any desired type of UUT, any desired communication medium, any desired protocol(s) for signal exchange over the communication medium, and any desired test procedure, etc. Furthermore, these reconfigurable technologies also allow the RTI to be rapidly reprogrammed or updated in response to changes in the UUT, changes in the communication medium, changes in the protocol(s) used for signal exchange over the communication medium, changes in the desired test procedure, etc.
A user may specify a set of desired operational characteristics for the reconfigurable test system utilizing a software configuration utility running on the host computer. The software configuration utility presents the user with a variety of choices of operational features such as, for example: a desired number of communication channels to be programmed into the RTI for signal exchange with the UUT; a desired directionality (input/output) for each of the communication channels; telecommunication protocols to be used for each of the communication channels; a line encoding scheme for receiving or transmitting signals from/to the UUT on each communication channel; voltages levels to be used for multi-level signal reception or transmission on each of the channels; synchronous versus asynchronous transfer; etc. In response to the user selections, a component selector program selects a hardware architecture file from a hardware architecture library, a front-end configuration file from a front-end configuration library, a number of host driver modules from a host software library, and optionally one or more embedded software programs from an embedded code library. The libraries include files for any possible combination of user choices. The hardware architecture file is downloaded to the reconfigurable hardware module on the RTI. The front end configuration file is downloaded to the reconfigurable front end on the RTI. The host driver modules are registered with a host software driver. The one or more embedded software programs are downloaded to embedded memory for execution by a local processor on the RTI. The downloaded files and registered modules posits or configures the reconfigurable test system with the operational attributes selected by the user with the configuration utility. A software test application executing on the host computer controls and monitors the reconfigurable test system 100 by making calls to the software driver.
Alternatively, a user may create a graphical program in a graphical programming environment which allows the user to select, manipulate, and interconnect graphical icons. The graphical icons represent a variety of processing operations, functions, and/or transformations which may be of interest to the user such as signal processing blocks, standard software operations, hardware devices, circuits, elements, etc. The user thus builds a graphical program which represents a desired test system architecture. Various portions of the graphical program may then be compiled into one or more of (1) software for execution on the host processor, (2) software for execution on the embedded processor in the RTI, (3) configuration information to be downloaded to the reconfigurable hardware of the RTI, i.e. the reconfigurable hardware module, and/or the reconfigurable front end.
A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:
While the invention is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and will herein be described in detail. It should be understood however, that drawings and detailed descriptions thereto are not intended to limit the invention to the particular forms disclosed. But on the contrary the invention is to cover all modifications, equivalents and alternatives following within the spirit and scope of the present invention as defined by the appended claims.
Incorporation by Reference
U.S. patent application Ser. No. 08/912,427 filed Aug. 18, 1997, now issued as U.S. Pat. No. 6,219,628, entitled “System and Method for Converting Graphical Programs into Hardware Implementations” whose inventors are Jeffrey L. Kodosky, Hugo Andrade, Brian Keith Odom and Cary Paul Butler, is hereby incorporated by reference in its entirety as though fully and completely set forth herein.
U.S. patent application Ser. No. 08/912,445 filed Aug. 18, 1997, now issued as U.S. Pat. No. 6,173,438, entitled “Embedded Graphical Programming System” whose inventors are Jeffrey L. Kodosky, Darshan Shah, Samson DeKey and Steve Rogers, is hereby incorporated by reference in its entirety as though fully and completely set forth herein.
In the preferred embodiment, the reconfigurable test system and method are used for telecommunication test applications, and this embodiment is discussed below. However, the present invention is not intended to be limited to telecommunication test applications, but can be used for any of various test and/or measurement applications as alluded to above. Thus, the following description describes the present invention in the specific domain of telecommunication testing.
As shown in
The RTI 130 is configured for coupling to a unit under test (UUT) 150 through a communication medium 140. It is noted that unit under test 150 may comprise a plurality of separate entities being tested. Also, the communication medium 140 may represent a plurality of distinct communication media. The RTI 130 preferably includes a reconfigurable hardware module, a reconfigurable front end, and optionally an embedded (i.e. local) processor with local memory as shown, e.g., in
The reconfigurable hardware module preferably includes one or more reconfigurable hardware devices such as Field Programmable Gate Arrays (FPGAs). Thus, the reconfigurable hardware module may be programmed to realize any desired hardware architecture. The reconfigurable front end may be programmed to interface with any desired types of signals using any desired line encoding scheme, voltage levels, etc. If an embedded processor is present on the RTI 130, an additional measure of programmability is afforded by appropriate selection of the embedded instruction code to be executed by the embedded processor.
Because of the combination of reconfigurable technologies incorporated in the RTI 130, the RTI may be programmed to operate with any desired type of UUT 150, any desired communication medium 140, any desired protocol(s) for signal exchange over the communication medium 140, and any desired test procedure, etc. Furthermore, these reconfigurable technologies also allow the RTI 130 to be rapidly reprogrammed in response to changes in the UUT 150, changes in the communication medium 140, changes in the protocol(s) used for signal exchange over the communication medium, changes in the desired test procedure, etc.
The host computer 110 is representative of any of a variety of computing devices such as personal computers, desktop computers, workstations, portable computers, laptop computers, etc. In the preferred embodiment, the RTI 130 is configured as an internal add-in board for insertion into a slot of the host computer 110. Alternatively, the RTI 130 may reside external to host computer 110, or may involve a combination of internal and external parts. In one embodiment, the RTI 130 is situated at a location which is remote from host computer 110. For example, the RTI 130 may be located at a remote test site close to UUT 150 which may be hazardous or otherwise unsuitable for host computer 110.
The interconnecting bus 120 may be realized by any of various bus connectivity technologies such as, e.g., a Peripheral Component Interconnect (PCI) bus, a PXI bus, a Universal Serial Bus (USB), an IEEE 394 bus, etc., or any combination thereof.
The communication medium 140 is representative of any of a variety of physical media including, e.g., metallic wire/cable, optical fiber, the atmosphere, etc., or any combination thereof. The RTI 130 may include connectors such as screw terminals or spring loaded terminals for coupling to wires. The RTI 130 may include connectors for one or more types of conductive cable or optical fiber. In addition, the RTI 130 may include connectors for coupling to one or more external antennas for atmospheric transmission or reception of signals. Various embodiments of the RTI 130 are contemplated with varying numbers of connectors and varying combinations of connector types.
The unit under test (UUT) 150 represents one or more devices, systems, components, or combination thereof which are to be tested. UUT 150 interacts with the RTI 130 through the communication medium 140. UUT 150 may be a digital, analog, or a hybrid analog-digital device. In order to communicate with the RTI 130, the UUT 150 may utilize any of a wide variety of communication protocols including proprietary internal protocols. The reconfigurable test system 100 of the present invention may be rapidly programmed, reprogrammed or reconfigured to operate with any desired protocol.
Referring ahead briefly to
In response to the user selections, a component selector 510 accesses one or more libraries 530, 540, 550 and/or 560, and selects from the libraries a collection of files which match the user's selections. The component selector 510 selects a hardware architecture file from a hardware architecture library 550, a front-end configuration file from a front-end configuration library 560, a number of host driver modules from a host software library 530, and optionally one or more embedded software programs from an embedded code library 540. The libraries include files for any possible combination of user choices. The hardware architecture file is downloaded to the reconfigurable hardware module 325 (
According to the present invention, the RTI 130 is capable of rapid reconfiguration of its operational/functional organization. Whenever the user desires to change some aspect of the reconfigurable test system 100, he/she may invoke the software configuration utility and reprogram the reconfigurable test system 100.
Bus bridge 205 is coupled to host CPU 200, system memory 210, and expansion bus 120. Bus bridge 205 mediates the high speed transfer of digital data between any two of the host CPU 200, system memory 210 and expansion bus 120. The input devices, non-volatile memory 225 and peripheral device 230 are preferably coupled to the expansion bus 120. Non-volatile memory 225 is representative of a variety of a variety of storage devices such as, e.g., disk drives, CD-ROM drives, zip drives, magnetic tape drives, optical storage, etc., or any combination thereof.
In the preferred embodiment, the RTI 130 is configured for coupling to the expansion bus of host computer 110. Under the control of test software running on host CPU 200 and/or embedded code running on an embedded processor, the RTI 130 executes a test procedure on UUT 150. The RTI sends stimulus signals/patterns to the UUT 150 and receives response signals/patterns from the UUT 150 through the communication medium 140. By analyzing the response signals, the host computer 110 or RTI 130 is able to either validate the UUT 110 or identify defects in the UUT 110.
In the preferred embodiment the expansion bus 120 comprises a Peripheral Component Interconnect (PCI) bus or the PXI (PCI eXtensions for Instrumentation) bus. However, it is noted that the expansion bus 120 may be realized any of a variety of interconnecting buses or combination thereof. For example, in alternate embodiments the expansion bus 120 comprises an Industry Standard Architecture (ISA) bus or Extended Industry Standard Architecture (EISA) bus.
Non-volatile memory 225 stores one or more software programs according to the present invention which control the operation of host computer 110. These software programs are loaded into system memory 210 prior to execution by host CPU 200.
The reconfigurable test instrument (RTI) 130 of the present invention may have any of a variety of architectures and forms of which several are illustrated in
The RTI 130 includes local memory 310, local (i.e. embedded) CPU 305, bus interface 315, bus connector 317, internal bus 320, reconfigurable hardware module 325, reconfigurable front end (RFE) 330, programmable clock generator 327, and I/O connectors 335. Local memory 310, local CPU 305, bus interface 315, reconfigurable hardware module 325, programmable clock generator 327 and reconfigurable front end 330 couple to internal bus 320. Programmable clock generator (PCG) 327 couples to the reconfigurable hardware module 325. Reconfigurable hardware module may have a dedicated coupling 326 to RFE 330 apart from internal bus 320 in order to facilitate higher speed data transfer. Bus interface 315 couples to bus connector 317.
Local CPU 305 may be directly coupled to local memory 310 through memory bus 306. Thus, local CPU 305 may access local memory 310 even when internal bus 320 is busy with other transfer operations. In addition, RHM 325 may be coupled directly to local memory 310.
Bus connector 317 is configured for coupling to expansion bus 120. I/O connectors 135 represent a collection of connectors for coupling to various kinds of communication media including, e.g., wires, cables, antennas, optical fibers, or any combination thereof. In the preferred embodiment, communication medium 140 represents a plurality of communication channels between the RTI 130 and UUT 150. According to the present invention, the user of reconfigurable test system 100 may configure the RTI 130 and a host software driver (i.e. software driver which is to run on host CPU 200) to operate with any combination of communication protocols for communicating with UUT 150 over the plurality of communication channels.
Bus interface 315 is provided for mediating data transfer between the internal bus 320 and expansion bus 120. Local CPU 305 executes instruction code stored in local memory 310. Local memory 310 comprises Random Access Memory (RAM) and preferably also Read Only Memory (ROM), and stores program variables, data structures, buffers for use by local CPU 305.
Reconfigurable hardware module (RHM) 325 includes one or more programmable devices such as Field Programmable Gate Arrays (FPGAs). Thus, the RHM 325 includes one or more reconfigurable or programmable hardware elements whose interconnectivity and functionality may be programmed by downloading configuration information to the RHM 325. The configuration information posits or configures the RHM 325 with a desired hardware architecture. For this reason, the configuration information downloaded to the RHM 325 is referred to herein as a hardware architecture file. The RHM 325 may be reprogrammed to achieve a new hardware architecture whenever desired.
In the preferred embodiment, as discussed above, the host computer 110 maintains library 550 of hardware architecture files which represent a variety of different hardware architectures. Any of these hardware architecture files may be downloaded to the RHM 325 to achieve corresponding hardware architectures.
In one embodiment, the reconfigurable test system 100 includes a hardware design utility. The hardware design utility provides a graphical user design environment for developing a hardware architecture, and for compiling the hardware architecture into a hardware architecture file. The hardware design utility preferably includes a graphical programming interface in which a user may select and configure graphical icons which represent hardware elements, blocks, subsystems, etc. which are generally referred to as cells. The user graphically specifies the connections between hardware cells as for example by drawing a path between a terminal of one cell to a terminal of another cell using the mouse 215. Examples of selectable hardware elements may include transistors, logic gates, flip-flops, etc, or function blocks such as add blocks, multiply blocks, etc. Examples of selectable hardware blocks may include registers, buffers, parallel-to-serial converters, serial-to-parallel converters, counters, clock frequency dividers, pattern detector circuits, edge detectors, multiplexers, demultiplexers, trigger circuits, shift registers, parity checkers, and arithmetic function circuits. Examples of selectable hardware subsystems may include input channels or output channels. In the preferred embodiment, the hardware design utility is LabVIEW graphical programming software available from National Instruments Corporation. The hardware design utility may use a hardware description language, such as VHDL. The resulting hardware diagram may be compiled to a hardware architecture file. The hardware architecture file may be downloaded to RHM 325 for immediate test system operation, or may be stored in the hardware architecture library 550 for later use.
Programmable clock generator (PCG) 327 generates one or more clock signals which are supplied to RHM 325. The frequencies of the one or more clock signals are programmable. Programming information may be supplied through internal bus 320. Alternatively, PCG 327 may receive programming information from RHM 325. The programmable clock generator 325 preferably includes a numerically controlled oscillator.
Reconfigurable front end (RFE) 330 includes various reconfigurable digital and/or analog circuitry for reconfigurable interfacing of RHM 325 with the communication medium 140. The front-end behavior of the RFE 330 is determined by configuration information supplied to the RFE 330 preferably through internal bus 320. This configuration information is herein referred to as a front end configuration file. RFE 330 mediates the exchange of signals between RHM 325 and UUT 150. RFE 330 receives one or more signals from the UUT 150 transmitted through the communication medium 140 over one or more communication channels. RFE 330 operates on, i.e. decodes, demodulates, conditions, and/or detects these signals in a manner determined by the front-end configuration file. The resultant digital signal(s) are provided to the RHM 325 preferably through dedicated coupling 326. In the reverse direction, RFE 330 receives one or more digital signals supplied by the RHM 325 through the dedicated coupling 326. The RFE 330 operates on, i.e. encodes, modulates, and/or conditions these digital signals in a manner determined by the front end configuration file. The RFE 330 then transmits the resultant signals to the UUT 150 through the communication medium 140 over one or more communication channels which are not necessarily the same as those mentioned above in the receive direction.
Reconfigurable front end (RFE) 330 may be configured for receiving and transmitting any of various kinds of analog, digital, and/or multi-level signals through communication medium 140, and for modulating and/or demodulating these signals according to their respective modalities. A multi-level signal refers to a signal that that may have multiple amplitude levels. A digital signal is a multi-level with two amplitude levels. RFE 300 preferably includes one or more programmable transceivers which allow operation with multilevel signals. The number of amplitude levels and the voltages of these amplitude levels are programmable preferably on a per channel basis.
In the preferred embodiment, RFE 330 includes an array of programmable transceivers. Each programmable transceiver forms part of a serial channel as, e.g., serial channel 402-K of
RFE 330 may include programmable switching circuitry (not shown) for switching analog and/or digital signals between the conductors of I/O connectors 335 and the reconfigurable circuitry of the RFE 330.
RFE 330 may also include one or more A/D converters and D/A converters (not shown) for transmitting analog signals over one or more analog channels. Also RFE 330 may include modulation and demodulation circuitry for transmitting and receiving modulated signals. For example, RFE 330 may include FSK mod/demod circuitry for handling a number of FSK channels. The present invention contemplates the use of any of a variety of modulation schemes, and therefore RFE 330 may include any of a variety of mod/demod circuits.
In one embodiment of reconfigurable test system 100, RFE 330 includes one or more Field Programmable Analog Arrays (FPAAs). An FPAA is an integrated circuit which can be configured to implement various analog functions using a set of configurable analog blocks and a programmable interconnection network. In this embodiment, the front end configuration file includes information for programming the FPAA(s).
In embodiments of the RFE 330 which include FPAA(s), the hardware design utility described above may additionally provide a graphical FPAA design environment for designing an analog circuit diagram, and for compiling the analog circuit diagram into a FPAA definition file. The analog design environment allows the user to select and interconnect graphical icons using, e.g., the mouse 215 of host computer 110. The interconnections may represent conductive paths. The graphical icons represent those analog elements, devices, blocks, or subsystems which are realizable in the FPAA(s). The resultant analog circuit diagram may be compiled into a FPAA definition file, and immediately downloaded to the FPAA(s), or stored in a library of such FPAA definition files for later use.
In yet another embodiment, the hardware design utility includes a graphical front end design environment which allows a user to configure the reconfigurable digital and/or analog hardware of the RFE 330.
It is noted that the digital, analog and front-end design environments provided by the hardware design utility may be integrated into a single design environment. Thus, a user may be able to select both digital cells and analog cells, and interconnect these cells in one circuit diagram subject to any design constraints which may be imposed by the physical hardware, i.e. the RHM 325 and RFE 330. The user may designate the target destination for each cell, block, or subsystem of the combined circuit diagram. Alternatively, the hardware design utility may be delegated the task of optimizing the distribution of cells, blocks, or subsystems between the various target destinations. Target destinations include the RHM 325, the FFPA(s) in the RFE 330, and the remaining hardware in the RFE 330.
Local CPU 305 executes a local control program which is stored in local memory 310. (Local CPU 305 may be variously referred to herein as the embedded CPU, the dedicated CPU, or the on-board CPU. The local control program may be variously referred to herein as the embedded software program or embedded instruction code.) The local control program is downloaded to the local memory 310 by the software configuration utility 500 running on the host CPU 200. Operating under the control of the local control program, local CPU 305 reads out-going data, i.e. data which is to be transmitted to UUT 150, from system memory 210 and/or local memory 310. Local CPU 305 supplies the out-going data to one or more output channels of the RHM 325. The RHM 325 and RFE 330 then transmit the out-going data to UUT 150. Conversely, local CPU 305 reads in-coming data, i.e. data originating from the UUT 150, from one or more input channels of the RHM 325. The in-coming data is then transferred to system memory 210 and/or local memory 310. In addition, the local CPU 305 may perform processing tasks on the in-coming data or out-going data as determined by the local control program.
Therefore, the reconfigurable test instrument (RTI) 130 according to the present invention allows a combination of software programmability by virtue of the local control program and hardware programmability by virtue of the configuration information downloaded to the RHM 325 and RFE 330. The hardware architecture file downloaded to the RHM 325 determines the hardware personality of the RHM 325. Similarly, configuration information downloaded to the RFE 330 determines structure of the RFE 330.
In the embodiment of reconfigurable test instrument 130 shown in
RHM 325 includes a pair of virtual channel slots, i.e., VCS 405A and VCS 405B. RFE 330 includes a corresponding pair of programmable transceivers, i.e., PT 410A and PT 410B. While only two virtual channel slots and two programmable transceivers are depicted in
Each serial channel 402 may be independently programmed as either an input channel or output channel. The hardware architecture file downloaded to the RHM 325 determines the directionality (i.e. input or output) of each virtual channel slot. In addition, the front-end configuration file downloaded to the RFE 330 determines the directionality of each programmable transceiver in a manner which is consistent with the directionality of the corresponding virtual channel slot. Once programmed, each serial channel achieves a high-speed input or output channel for communication with the UUT 150. High data transfer rates are attainable because the serial channels 402 are hardware programmed into the RHM 325 and 330 as opposed to being implement by a CPU in software.
For the sake of discussion, suppose serial channel 402A is an output channel and serial channel 402B is an input channel. Out-going data, i.e. data to be transmitted to the UUT 150 through conductor 425A, is first transferred to the virtual channel slot 405A over internal bus 320. Virtual channel slot 405A is preferably programmed to include an input buffer for temporarily storing the out-going data. Local CPU 305 or host CPU 200 may load the input buffer with out-going data. The virtual channel slot 405A may then transfer the outgoing data to programmable transceiver 410A over serial bus 408A. Virtual channel slot 405A is preferably programmed to include a parallel-to-serial converter for transforming the out-going data into a serial form. Programmable transceiver 410A conditions, encodes, and/or modulates the out-going data in a manner determined by the front-end configuration file. The resultant signal is transmitted by programmable transceiver 410A to UUT 150 over conductor 425A. For example, the out-going data may be encoded as a four-level signal, i.e., a signal with four discrete amplitude levels. The front-end configuration file may then specify the line encoding scheme to be four-level coding, and provide the four voltage levels for transmitting the signal data.
An in-coming signal, i.e., a signal transmitted from the UUT 150, may be received from conductor 425B by programmable transceiver 410B. Programmable transceiver 410B decodes, demodulates, and/or operates on the received signal in a manner determined by the front-end configuration file. The programmable transceiver 410B may then supply a digital data stream to virtual channel slot 405B over serial bus 408B. Virtual channel slot 405B is preferably programmed to include a serial-to-parallel converter for converting the data stream into parallel form. Virtual channel slot 405B may store the received data in an output buffer. The output buffer may be configured as part of virtual channel slot 405B or may reside external to the virtual channel slot 405B. The output buffer may be read by local CPU 305 and/or host CPU 200 for further processing and/or storage of the received data. For example, the received data may be transferred to system memory 210, or local memory 310.
In addition, virtual channel slot 405B may perform various operations on the received data as determined by the hardware architecture file. For example, the virtual channel slot 405B may be programmed to perform pattern detection, edge detection, parity checking, etc. on the received data stream. A pattern matching circuit encoded into the virtual channel slot 405B may scan for the occurrence of a given pattern in the received data stream. Upon detection of the pattern, the pattern matching circuit asserts a pattern match signal. The pattern match signal may be used to trigger one or more other events. The pattern match circuit may be useful for detecting the start and/or end of a data frame. The search pattern may be programmed into a register or buffer of the pattern match circuit.
As an example of decode programmability, programmable transceiver 410B (and any of the programmable transceivers 410) may be programmed to decode the received signal as a multi-level signal. The front-end configuration file specifies the number of levels in the multi-level signal and the voltage value associated with each of the multiple levels.
One or more of the virtual channel slots 405 may be programmed to include a triggering circuit to be described in detail somewhat later. The triggering circuit may receive various signals of interest to the user such as a pattern match signal, an edge detection signal, an external trigger, etc. The trigger circuit may generate a trigger signal as a function of the input signals. The trigger signal may be used to initiate or terminate the transmission and/or reception of channel data. For example, the trigger signal may be supplied to virtual channel slot 405A to initiate data transfer to the UUT 150. Alternately, the trigger signal may be supplied to virtual channel slot 405B to initiate the buffering of received data.
Virtual channel slot 405A may be coupled to programmable transceiver 410A by a control bus 407A. The control bus 407A allows the virtual channel slot 405A to control various operations of the programmable transceiver 410A. Similarly, virtual channel slot 405B may be coupled to programmable transceiver 410B to control the operation of programmable transceiver 410B.
Programmable clock generator 327 is configured to generate a clock signal and supply the clock signal to the RHM 325. The frequency or period of the clock signal is programmable. The local CPU 305 and/or the host CPU 200 may load the clock frequency or period information into a register of the PCG 327. The PCG 327 generates a clock signal whose frequency is determined by the value stored in the register. One or more serial channels 402 may use the clock signal. For example, the clock signal may be used to control synchronous reception or transmission of serial data. In one embodiment of the PCG 327 may generate one or more clock signals each with a programmable clock rate.
An external clock line 420 may be provided to the reconfigurable test instrument 130. The external clock line 420 allows an external clock signal to be used in addition to or instead of the internal clock supplied by the PCG 327. For example, a first subset of the serial channels 402 may perform synchronous transfers based on the external clock, while a second subset of the serial channels 402 may perform synchronous transfers based on the internal clock. It is noted that a third subset of serial channels may perform asynchronous transfers using digital phase locked loops to synchronize with an input serial stream. These features, i.e. external synchronicity, internal synchronicity, or asynchronous transfer are programmed into the structure of each of the virtual channel slots 405 by the hardware architecture file which is downloaded to the RHM 325.
The software configuration utility 500 preferably comprises a graphical user interface (GUI) for configuring the reconfigurable test system 100. The software configuration utility 500 accepts user input 501 and sends graphical output 502 to the user through display 235. The software configuration utility 500 sends commands to the component selector 510 in response to choices made by the user. In response to these commands, the component selector 510 selects files from the driver component library 530, the embedded software library 540, the hardware architecture library 550, and the front-end configuration library, and registers these files with the software driver 520. In the preferred embodiment, the software configuration utility 500, the component selector 510, and the software driver 520 programs execute on host CPU 200.
The software driver 520 comprises a collection of software routines which provide a software interface for interacting with peripheral devices including the reconfigurable test instrument 130. Software programs including the software test application may call the driver routines in order to arrange data transfer to/from reconfigurable test instrument 130 and other peripheral devices as desired. The software driver 520 exchanges various control signals with the reconfigurable test instrument 130. In
The driver component library 530 comprises a collection of software modules which perform various functions which may be of interest to a user for building a test application. One or more of these software modules may be registered with the software driver 520. After this registration, host programs including the software test application 565 may call the registered software modules. The driver component library 530 preferably includes software modules which perform functions such as protocol handling, fundamental test procedures, etc.
Software test application 565 serves to control a test procedure in part by making calls to the software driver 520, and especially to the driver software modules which have been registered in the software driver 520 in response to user configuration selections. For example, the software test application 565 may induce the transfer of data/control signals to/from UUT 150 through one or more serial channels by calling appropriate driver software modules of the software driver 520.
As shown in
It is noted that protocol handling may be implemented (a) by driver software modules as illustrated above, (b) by programming the RHM 325 with a hardware architecture file, (c) by programming the RFE 330 with a front-end configuration file, (d) by downloading embedded software programs for execution on local CPU 305, or any combination thereof. In particular, the reconfigurable test system 100 allows a system user/developer to achieve an optimal distribution of protocol processing tasks to each of these reconfigurable targets.
The configuration utility 500 preferably provides the user with a choice of one or more telecommunication protocols to be implemented by the reconfigurable test system 100. The configuration utility also validates the compatibility of the one or more telecommunication protocols to guide the user in selection of appropriate combinations of protocols.
The component selector 510 selects one or more user selected modules from the driver component library 530 and registers the selected modules with the software driver 520. The software driver 520 has a flexible structure which allows software modules to be inserted to provide specific kinds of test functionality.
It is noted that certain telecommunication protocols fall into a hierarchical organization. For example, the HDLC protocol is a superstructure imposed on top of RS232, and the SLIP protocol is a superstructure on top of HDLC. In the preferred embodiment, the software modules of the software component library reflect the compatibility structure of such hierarchical organizations. Thus, the RS232 module 531, HDLC module 532, and the SLIP module 533 may be simultaneously chosen by component selector 510 for incorporation into the software driver structure, and together they are capable of implementing the SLIP protocol. Block generation software can be used, such as LabVIEW or VHDL, to generate the above software modules or blocks.
The configuration utility 500 prompts the user to specify how the virtual channel slots 405 of the RHM 325 are to be configured. For example, in the case that RHM 325 includes two virtual slots 405 as shown in
The embedded software library 540 preferably includes a rich variety of embedded software programs for performing processing and/or control tasks which may be of interest to the user. One or more of these embedded software programs may be downloaded to local memory 310 and executed by local CPU 305. For example, embedded software library 540 may include embedded software programs for handling any of a variety of protocols, for performing real-time signal processing tasks, etc. The software configuration utility 500 preferably allows the user to choose one or more of the embedded software programs for downloading to the reconfigurable test instrument 130.
The front end configuration library 560 preferably includes a collection of front end configuration files for achieving a rich variety of front end configurations. Each of these embedded software programs may be downloaded to the reconfigurable front end (RFE) 330 to realize a particular front-end operational structure. For embodiments of the RFE 330 which include one or more Field Programmable Analog Arrays (FPAAs), the front end configuration file preferably includes information for programming the FPAA(s). A front end configuration file includes information for programming the reconfigurable hardware of the RFE 330. For example, a front end configuration file preferably includes information for programming the directionality (i.e. input or output), line encoding scheme, etc. for each of the programmable transceivers 410 of the RFE 330.
In response to these choices, the component selector 510 selects one or more driver modules from the driver component library 530, one or more embedded software programs from the embedded software library 540, a hardware architecture file from the hardware architecture library 550, and a front end configuration file from the front end configuration library 560 as shown in step 720.
In addition to selecting components, i.e. driver modules, embedded software programs, hardware architecture files, and front end configuration files, from the respective libraries, the user has the option of creating and/or modifying these components using any or all of the design utilities described above as indicated by step 715. Thus, the components selected in step 720 may be those created and/or modified by the user in step 715.
The component selector 510 registers the selected one or more driver modules, one or more embedded software programs, hardware architecture file and front end configuration file with the software driver 520 as shown in step 730.
In step 740 the software driver 520 loads the registered software modules into its internal structure. In step 750 the software driver 520 downloads the registered embedded software program(s) to local memory 310 on the reconfigurable test instrument 130. In step 760 the software driver 520 downloads the registered hardware architecture file to the reconfigurable hardware module 325 in the reconfigurable test instrument 130. In step 770 the software driver downloads the registered front end configuration file to the reconfigurable front end 330 on the reconfigurable test instrument 130. It is noted that steps 740, 750, 760 and 770 may be performed in any order.
The entire process from user selection to system configuration is preferably performed in real-time and can be repeated whenever the user deems necessary. For example, if the user has finished testing a first device or first plurality of devices of a common type and desires to test a different type of device as the UUT 150, the user reconfigures the reconfigurable test system 100 by entering new choices in the configuration utility 500.
In addition, the features of the configuration utilities are available programmatically, meaning that during a test operation the user could select new functionality using the GUI, or the program is created such that it automatically changes the configuration in response to some event.
Quite often, testing a new device will imply the use of a different telecommunication protocols and/or channel structure for signal exchange over communication medium 140. Thus, when reconfiguring the reconfigurable test system 100, the user may specify choices of one or more new telecommunication protocols, a new test scenario, and/or new hardware architecture using the configuration utility 500. In addition, when creating the program in the reconfigurable test system 100, the user may create the program such that choices of one or more new telecommunication protocols, a new test scenario, and/or new hardware architecture are automatically selected and implemented by the program in response to one or more events that occur during program execution.
In the preferred embodiment of the invention, most of the operations connected with handling telecommunication protocols are implemented in software using the driver modules and the embedded software modules. As described above, one or more driver modules from the driver component library 530 may be incorporated into the software driver 520, and one or more embedded software modules may be downloaded to the local memory 310 for execution by the local CPU 305.
As described above, the input/output configuration of virtual channel slots 405 are determined by the hardware architecture file downloaded to the configuration information downloaded to the RHM 325. For example, if the hardware architecture file denoted by Input/Output::Asynch in
Hardware architecture files which specify asynchronous operation may program a digital phase locked loop into one or more of the virtual channel slots 405. Alternatively, digital phase locked loops may be included as part of the reconfigurable hardware of RFE 330.
In one embodiment of the present invention, the user creates a graphical program using a graphical programming environment, such as LabVIEW from National Instruments Corporation. The graphical programming environment preferably executes on the host CPU 200. A portion of the graphical program is compiled into a hardware architecture file for downloading to the reconfigurable hardware module 325 which contains one or more FPGAs. In addition, a portion of the graphical program is compiled into a front end configuration file for downloading to the reconfigurable front end 330. Another portion of the graphical program may be compiled into an embedded software program for downloading to local memory 305 and execution by local CPU 310. Yet another portion of the graphical program may be compiled into software modules for registry/incorporation into the software driver 520. Also, portions of the graphical program may be compiled into instruction code for execution on host CPU 200. For example, the software test program described above may be generated from portions of the graphical program which are compiled into instruction code for the host CPU 200. In this embodiment, the local memory 310 preferably stores a kernel providing basic OS services, as well as a graphical programming system run-time engine for real-time execution of compiled graphical programs. The local memory 310 is also operable to receive and store a portion or all of a compiled graphical program for execution in the reconfigurable test instrument 130. The embedded CPU 305 executes code and data from the embedded memory 310 to implement at least a portion of a virtual instrumentation or industrial automation function, such as a telecommunication test function. The user may specify which portions of the graphical program are to be targeted for the respective destinations: reconfigurable hardware module 325, reconfigurable front end 330, embedded software for execution by local CPU 200, host driver modules for registry with the software driver 520, or host program code. Alternatively, an optimization utility may be invoked to automatically optimize the distribution of portions of the graphical program to the various target destinations. Thus, by creating, compiling, and downloading such a graphical program, the user may generate a desired configuration for the reconfigurable test system 100.
Thus, in one embodiment, after one or more graphical programs have been created, at least a portion of the one or more of the graphical programs are compiled for execution on the local CPU 305 and execute locally on the reconfigurable test instrument 130 via the local CPU 305 and local memory 310, and at least a portion of the one or more graphical programs is translated or converted into a hardware executable format and downloaded to reconfigurable hardware module 325 which includes one or more FPGAs.
For more information on these embodiments including a reconfigurable or programmable logic device, such as an FPGA, and/or a local or embedded CPU, please see U.S. patent application Ser. No. 08/912,427 filed Aug. 18, 1997, entitled “System and Method for Converting Graphical Programs into Hardware Implementations” whose inventors are Jeffrey L. Kodosky, Hugo Andrade, Brian Keith Odom and Cary Paul Butler, and U.S. patent application Ser. No. 08/912,445 filed Aug. 18, 1997, entitled “Embedded Graphical Programming System” whose inventors are Jeffrey L. Kodosky, Darshan Shah, Samson DeKey and Steve Rogers, referenced above.
The trigger circuit 800 includes a first multiplexer M1 and a second multiplexer M2. Each multiplexer is provided with a plurality of inputs denoted I1, I2, I3, and I4. The multiplexers M1 and M2 receive control or select inputs C1 and C2 respectively. The value asserted on control input C1 determines which of inputs I1 through I4 is coupled to the output of multiplexer M1. Similarly, control or select input C2 determines which of the inputs I5 through I8 is coupled to the output of multiplexer M2. The outputs of the multiplexers M1 and M2 are supplied as inputs to combinational logic CL. Combinational Logic CL receives a control input C3 which determines a combinational logic function which operates on the outputs of the multiplexers. In one embodiment of the invention, the combinational logic CL is configured to perform an logical AND operation, or a logical OR operation depending on a value asserted on control input C3. In a second embodiment, the combinational logic CL is configured to perform additional logic functions which include any or all of the logical functions in two binary variables (A XOR B, A OR -B, . . . ).
The output of combinational logic CL is supplied as an input to J/K flip-flop 810. The output of J/K flip-flop 810 represents a dual-event triggering signal (i.e. a triggering signal which is sensitive to two input conditions) and comprises the output of the trigger circuit 800. This output signal may be used to trigger the acquisition of data for an input channel and/or the transmission of data from a serial output channel. Thus, the signal at the output of the J/K flip-flop is referred to as the trigger signal. The trigger signal is coupled to a timer TMR. An output from the timer TMR is coupled to the reset input of the J/K flip-flop. The timer TMR is loaded with an initial count value through timer load line TL. In response to the rising edge of the trigger signal, the timer TMR starts to decrement its internal count value. When the count value reaches zero, the timer TMR asserts an output signal which resets the J/K flip-flop 810. Thus, when the trigger signal is asserted, it remains in the asserted state for a period of time determined by the initial count value.
It is noted that the signals I1 through I4 and I5 through I8 are not necessarily distinct sets of signals. The signals I1 through I8 comprise various signals which may be of interest to a user in building a triggering signal. Signals I1 through I8 may represent signals such as a pattern match signal, an edge detection signal, an external trigger signal, etc. For example, the signal I1 may be a rising (or falling) edge detection signal provided by an edge detection circuit. The signal I2 may be an external trigger signal (not shown in
Thus, the trigger circuit 800 of the present invention enables the reconfigurable test instrument 130 to trigger on any desired combination of events represented by I1 through I8. The control inputs C1, C2, and C3, and timer load line TL may be determined by control information asserted by the software driver 520 on normal control flow 570 and data I/O path 575 as well as by the hardware architecture file which is downloaded to the RHM 325.
Although the system and method of the present invention has been described in connection with the specific embodiments, it is not intended to be limited to the specific forms set forth herein, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents, as can be reasonably included within the spirit and scope of the invention as defined by the appended claims.
This application is a continuation of U.S. patent application Ser. No. 09/229,695, filed Jan. 13, 1999, entitled “Reconfigurable Test System” whose inventors are Arthur Ryan, Hugo Andrade and Brian Keith Odom which claims benefit of priority of provisional application Ser. No. 60/074,806 entitled “Dynamic Hardware and Software Reconfiguration for Telecommunication Testing” filed Feb. 17, 1998, whose inventors are Arthur Ryan and Hugo Andrade.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4849880 | Bhaskar et al. | Jul 1989 | A |
| 4901221 | Kodosky et al. | Feb 1990 | A |
| 5005119 | Rumbaugh et al. | Apr 1991 | A |
| 5109504 | Littleton | Apr 1992 | A |
| 5164911 | Juran et al. | Nov 1992 | A |
| 5197016 | Sugimoto et al. | Mar 1993 | A |
| 5309556 | Sismilich | May 1994 | A |
| 5437464 | Terasima et al. | Aug 1995 | A |
| 5497498 | Taylor | Mar 1996 | A |
| 5535342 | Taylor | Jul 1996 | A |
| 5541849 | Rostoker et al. | Jul 1996 | A |
| 5555201 | Dangelo et al. | Sep 1996 | A |
| 5566295 | Cypher et al. | Oct 1996 | A |
| 5583749 | Tredennick et al. | Dec 1996 | A |
| 5603043 | Taylor et al. | Feb 1997 | A |
| 5630164 | Williams et al. | May 1997 | A |
| 5638299 | Miller | Jun 1997 | A |
| 5652875 | Taylor | Jul 1997 | A |
| 5684980 | Casselman | Nov 1997 | A |
| 5732277 | Kodosky et al. | Mar 1998 | A |
| 5737235 | Kean et al. | Apr 1998 | A |
| 5784275 | Sojoodi et al. | Jul 1998 | A |
| 5847955 | Mitchell et al. | Dec 1998 | A |
| 6064409 | Thomsen et al. | May 2000 | A |
| 6226776 | Panchul et al. | May 2001 | B1 |
| 6230307 | Davis et al. | May 2001 | B1 |
| 6311149 | Ryan et al. | Oct 2001 | B1 |
| 6564368 | Beckett et al. | May 2003 | B1 |
| Number | Date | Country |
|---|---|---|
| WO 94 10627 | May 1994 | WO |
| WO 94 15311 | Jul 1994 | WO |
| WO 96 14618 | May 1996 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20020055834 A1 | May 2002 | US |
| Number | Date | Country | |
|---|---|---|---|
| 60074806 | Feb 1998 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 09229695 | Jan 1999 | US |
| Child | 10034565 | US |
