Patent Application
20210157738
The present invention generally relates to memory, and more specifically, to a recoverable user cache within recoverable application memory within volatile memory.
User application memory does not survive an initial program load (IPL). After an initial program load, memory must be reallocated and repopulated with data. For large areas of memory, this reallocation and repopulation can be costly in terms of I/O and CPU processing immediately after an initial program load.
Embodiments of the present invention are directed a recoverable user cache within recoverable application memory within volatile memory. A non-limiting example computer-implemented method includes designating, by a processor, a portion of the processor memory as recoverable application memory and establishing, by the processor, a portion of the recoverable application memory as recoverable user cache. The method accesses, by the processor, the recoverable user cache following an initial program load.
Other embodiments of the present invention implement features of the above-described method in computer systems and computer program products.
Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings.
The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The diagrams depicted herein are illustrative. There can be many variations to the diagrams or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term “coupled” and variations thereof describe having a communications path between two elements and do not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.
One or more embodiments of the present invention provide a recoverable application memory, which is an area of processor memory that can be accessed by all processes and is usable by both system code and user application code. This allows users, as well as the recoverable user cache, to have continued, uninterrupted access to the data stored in memory even after an initial program load. The recoverable user cache utilizes the recoverable application memory described above to implement a cache where the data in the cache persists over an initial program load without using specialized hardware and without having to repopulate the cache after the initial program load under most circumstances.
Traditional cache implementations provide either data storage in volatile memory which does not survive an initial program load, or they back the cache with a non-volatile data storage mechanism, such as disk or specialized non-volatile memory that is referred to herein as specialized hardware. Implementations using specialized hardware are typically not available to the user/application. Although some implementations may provide continued access to cached data after an initial program load, they do this by either using specialized non-volatile memory or by reloading the data into the cache, which requires a significant amount of CPU processing or disk I/O before the data is fully available in the cache.
The ability for a user/application to have continued access to cache data after an initial program load, without specialized hardware and without undergoing a significant amount of CPU processing or disk I/O in order to repopulate a cache, is lacking. Cache data can be simple data read directly from the disk or the result of many complex calculations involving data from various sources, such as, for example, disk, memory, or other calculations. Some users have caches that are large enough where repopulating the cache after an unplanned initial program load, i.e., an outage, is not an option due to the work and overall time required to complete the repopulation of the cache. The lack of data in cache during this time may cause severe performance degradation that could cause a subsequent outage.
Lastly, changing the size of the cache with most user cache implementations requires deleting and recreating the cache causing the loss of all cached data. This results in the same performance degradation with respect to repopulating the cache.
One or more embodiments of the present invention address one or more of the above-described shortcomings of the prior art by providing an area of system memory designated as recoverable across both planned and unplanned IPL's, where the hardware and memory configurations are not changed. This provides the ability to keep data in memory when a software initial program load occurs or when a hard initial program load without clear is done. The recoverable application memory is implemented within volatile memory and without specialized hardware. The recoverable application memory is an area of system memory that can be accessed by all processes and is usable by both system code and user application code. This allows users, as well as the recoverable user cache, to have continued, uninterrupted access to the data stored in memory even after an initial program load. A user cache that is recoverable over an initial program load without being key-pointed to disk or to specialized non-volatile memory.
Turning now to
As shown in
The computer system 100 comprises an input/output (I/O) adapter 106 and a communications adapter 107 coupled to the system bus 102. The I/O adapter 106 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 108 and/or any other similar component. The I/O adapter 106 and the hard disk 108 are collectively referred to herein as a mass storage 110.
Software 111 for execution on the computer system 100 may be stored in the mass storage 110. The mass storage 110 is an example of a tangible storage medium readable by the processors 101, where the software 111 is stored as instructions for execution by the processors 101 to cause the computer system 100 to operate, such as is described herein below with respect to the various Figures. Examples of computer program product and the execution of such instruction is discussed herein in more detail. The communications adapter 107 interconnects the system bus 102 with a network 112, which may be an outside network, enabling the computer system 100 to communicate with other such systems. In one embodiment, a portion of the system memory 103 and the mass storage 110 collectively store an operating system, which may be any appropriate operating system, such as the z/OS or AIX operating system from IBM Corporation, to coordinate the functions of the various components shown in
Additional input/output devices are shown as connected to the system bus 102 via a display adapter 119 and an interface adapter 116 and. In one embodiment, the adapters 106, 107, 115, and 116 may be connected to one or more I/O buses that are connected to the system bus 102 via an intermediate bus bridge (not shown). A display 119 (e.g., a screen or a display monitor) is connected to the system bus 102 by a display adapter 115, which may include a graphics controller to improve the performance of graphics intensive applications and a video controller. A keyboard 121, a mouse 122, a speaker 123, etc. can be interconnected to the system bus 102 via the interface adapter 116, which may include, for example, a Super I/O chip integrating multiple device adapters into a single integrated circuit. Suitable I/O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols, such as the Peripheral Component Interconnect (PCI). Thus, as configured in
In some embodiments, the communications adapter 107 can transmit data using any suitable interface or protocol, such as the internet small computer system interface, among others. The network 112 may be a cellular network, a radio network, a wide area network (WAN), a local area network (LAN), or the Internet, among others. An external computing device may connect to the computer system 100 through the network 112. In some examples, an external computing device may be an external webserver or a cloud computing node.
It is to be understood that the block diagram of
A recoverable user cache 230 is recoverable over an initial program load without being key-pointed to disk or to specialized non-volatile memory. The recoverable user cache utilizes the recoverable application memory 220 to implement a cache where the data in the cache persists over an initial program load without using specialized hardware and without having to repopulate the cache after the initial program load under most circumstances. For large caches (10 GB+), the time saved in avoiding cache repopulation can be significant given that the source data does not need to be recalculated or read in from disk, involving a significant amount of I/O. Without incurring the penalties associated with repopulating the cache, work can resume much more quickly after an initial program load. After an unscheduled initial program load (outage), the risk of another unscheduled outage shortly after recovering from an unscheduled outage, is abated. The primary purpose of the recoverable cache is to keep critical data in memory across an unscheduled IPL so that performance degradation will not happen after an outage. Lastly, changing certain attributes of the cache, such as the size of the cache, whether backed by non-recoverable or recoverable memory, is done without the loss of cached data via a recycle operation, avoiding the performance degradation associated with cache re-population for changes to these attributes.
An application program interface (“API”) provides the user with the ability to allocate, release, and find a piece of recoverable application memory 220. The system provides each allocated piece of recoverable application memory 220 a unique token via this API. The token is used to locate a particular piece of allocated memory after an initial program load via this API. On a recoverable application memory allocation request, there is an option to allocate non-recoverable memory instead of recoverable memory if the request for recoverable memory cannot be satisfied. There is also the ability to group multiple pieces of recoverable application memory under one unique token. Although there are multiple non-contiguous pieces of memory, this grouping allows all of it to be located or released with a single API call. Various APIs and commands used to manage and monitor memory on the system are updated to incorporate the recoverable application memory feature set.
A recoverable user cache 230 is established in the recoverable application memory in block 320. The recoverable user cache is a modification of the existing user cache support that provides the option of backing a processor unique cache with either non-recoverable or recoverable memory. Existing user cache APIs that handle the creation of non-recoverable caches, do so for the recoverable user caches 230 as well. For both non-recoverable and recoverable user caches 230, if the cache already exists a cache token is returned for the existing cache. Otherwise, for recoverable user caches 230, if existing recoverable application memory 220 is found using the recoverable application memory API described with respect to block 210, instead of allocating new memory as the method would do for non-recoverable user caches, the recoverable memory is reattached to the cache control area and return the cache token for the cache. If neither the cache or the recoverable heap exists then the appropriate type of memory (non-recoverable or recoverable) is allocated, the cache is setup, attached to the cache control area, and the cache token is returned. This is the low level implementation that makes use of the recoverable application memory 220. All other existing user cache APIs behave the same whether interacting with a non-recoverable or recoverable user cache 230.
Changing certain cache attributes, such as the size of the cache, whether backed by non-recoverable or recoverable memory, is done without the loss of cached data via a recycle operation. This avoids the same problems that are associated with repopulating a cache after an IPL, for some cache attribute changes. For this to be used, the resources required for both the existing cache and the new cache need to be available. The sum of the resources (memory) necessary for both the old and new caches is needed because the recycle operation will allocate a new cache while the old cache still exists. The recycle operation will link the two caches for a period of time while the new cache is populated via normal cache activity. The new cache is installed such that the same cache token used for the old cache will now map to the new cache. The old cache will be secondary to the new cache internally and will not be directly accessible. During this recycle period, a hit in the new cache will result in a hit for the user's read request. A miss in the new cache will result in a read from the old cache. A miss in this internal read of the old cache will finalize the miss for the user's read request. A hit in this internal read from the old cache will cause an update of the new cache with the read data and a hit being returned for the user's read request.
After this period of time the cache support will delete the old cache. The period of time will not be longer than the maximum timeout for entries in the old cache, as reads from the old cache after this point would result in a miss anyway. A hard stop time period exists, so that the larger of the two timeout periods will be used to determine when the old cache is deleted. After this period, a subsequent user read of the cache is used to trigger the actual delete. This prevents caches with long or no timeouts from persisting in the “recycle” state indefinitely. No updates will be made to the old cache during this (recycle) time. This command is only allowed for processor unique caches. This is transparent to the user. The user uses the cache as usual during the recycle operation, without interruption.
In block 330, the recoverable user cache 230 is used following an IPL without having to be rebuilt.
Various embodiments of the invention are described herein with reference to the related drawings. Alternative embodiments of the invention can be devised without departing from the scope of this invention. Various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein.
One or more of the methods described herein can be implemented with any or a combination of the following technologies, which are each well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc.
For the sake of brevity, conventional techniques related to making and using aspects of the invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs to implement the various technical features described herein are well known. Accordingly, in the interest of brevity, many conventional implementation details are only mentioned briefly herein or are omitted entirely without providing the well-known system and/or process details.
In some embodiments, various functions or acts can take place at a given location and/or in connection with the operation of one or more apparatuses or systems. In some embodiments, a portion of a given function or act can be performed at a first device or location, and the remainder of the function or act can be performed at one or more additional devices or locations.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
The diagrams depicted herein are illustrative. There can be many variations to the diagram or the steps (or operations) described therein without departing from the spirit of the disclosure. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term “coupled” describes having a signal path between two elements and does not imply a direct connection between the elements with no intervening elements/connections therebetween. All of these variations are considered a part of the present disclosure.
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include both an indirect “connection” and a direct “connection.”
The terms “about,” “substantially,” “approximately,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.
The present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instruction by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.
