Patent Application
20140054710
Not applicable.
Not applicable.
This invention is in the field of integrated circuit manufacture. Embodiments of this invention are more specifically directed to metal-oxide-semiconductor field-effect transistors (MOSFETs) to which strain engineering technology is applied.
Recent advances in semiconductor technology as applied to integrated circuits include the use of “strain engineering” (or, alternatively, “stress engineering”) in the manufacture of semiconductor device structures. As is fundamental in MOS device technology, the source/drain current (i.e., drive) of a MOS transistor in both the triode and saturation regions is proportional to carrier mobility in the channel region. It has been discovered that the tuning of strain in the crystal lattice of metal-oxide-semiconductor (MOS) transistor channel regions can enhance carrier mobility in those regions. In a general sense, compressive stress enhances hole mobility in the channel region of a p-channel MOS transistor, and tensile stress enhances electron mobility in the channel region of an n-channel MOS transistor.
Various strain engineering approaches are known in the art. According to the approach known as “embedded SiGe” (also referred to as “eSiGe”), source and drain regions of a p-channel MOS transistor structure are etched from the silicon substrate or well region, and are replaced with a silicon-germanium alloy formed by selective epitaxy. By containing as much as 50% (atomic) or more germanium in the crystal lattice, the resulting alloy exhibits a larger lattice constant than does silicon (i.e., the distance between unit cells in the crystal lattice for SiGe is greater than in single-crystal silicon). Embedded SiGe source/drain regions thus apply compressive stress to the adjacent channel region of the p-channel MOS transistor being formed. This compressive stress in the channel increases the hole mobility of the p-channel MOS transistor, and enhances transistor performance. As known in the art, p-channel MOS transistors inherently exhibit lower drive capability than n-channel MOS transistors in typical modern integrated circuits. This weaker p-channel MOS performance can be a limiting factor in CMOS switching speed. Accordingly, eSiGe is an attractive technology for improving the performance of p-channel MOS transistors and thus the overall circuit performance.
a through 1d illustrate, in cross section, the fabrication of a conventional p-channel MOS transistor including eSiGe source/drain regions.
To form the embedded SiGe source/drain regions in this conventional process, gate dielectric 7 is removed from the source/drain regions, and exposed locations of n-well 6 are etched, at locations outside of gate electrode 8, to form recesses 10 into the underlying single-crystal silicon, as shown in
By way of further background, a “cap” layer of silicon without Ge dopant may be formed at the surface of SiGe structures 12 in some conventional integrated circuits. This cap layer may be on the order of 50 to 200 Å for a 600 Å deep recess 10, and allows direct react silicidation to form a metal silicide cladding at the source and drain regions of the transistor; the cap layer of silicon is consumed in that silicidation reaction.
As suggested in
By way of background, as described in Choi et al., “Layout Variations in Advanced MOSFETs: STI-Induced Embedded SiGe Strain Relaxation and Dual-Stress-Liner Boundary Proximity Effect”, Trans. on Electron Devices, Vol. 57, No. 11 (IEEE, November 2010), pp. 2886-91, incorporated by reference, it has been found that shallow trench isolation structures proximate to the gate edge of an p-channel MOS transistor with embedded SiGe source/drain structures relax the strain applied to the transistor channel region by the SiGe material. This strain relaxation is detrimental in that it reduces the effectiveness of the SiGe structures in improving carrier mobility in the transistor. It has also been observed that the undesired relaxation effect caused by the shallow trench isolation structures increases as the spacing between the edge of the isolation structure and the gate edge decreases.
As known in the art, many modern logic integrated circuits, as well as solid-state memory devices, are now implemented in regular arrays at the transistor level. This regularity is often expressed by arranging gate electrodes of similar size in parallel rows over an area of the integrated circuit. Particularly for minimum feature size gate electrodes, such as in the deep sub-micron regime, this regularity reduces variation due to photolithographic effects, thus improving the controllability of feature sizes and the matching of transistors over the integrated circuit.
However, the proximity effect of shallow trench isolation structures on the effectiveness of embedded SiGe degrades the matching that is otherwise expected from this regularity in transistor array layouts.
As mentioned above, it has been observed that the proximity of shallow trench isolation structures 5 parallel to the edges of gate electrodes 8 can degrade the beneficial compressive strain applied by SiGe structures 12, 12′ to transistor channel regions 14. This strain relaxation has been observed to vary with the spacing SA between the edge of shallow trench isolation structures 5 and the near edges of gate electrodes 8. For example, as shown in
By way of further background,
By way of further background, commonly assigned U.S. Pat. No. 8,183,117, entitled “Device Layout in Integrated Circuits to Reduce Stress from Embedded Silicon-Germanium”, incorporated by reference herein, describes an integrated circuit including one or more MOS transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated.
Embodiments of this invention provide an integrated circuit and method of fabricating the same having metal-oxide-semiconductor (MOS) transistors with embedded silicon-germanium source/drain structures, in which transistor performance is less sensitive to proximity effects from nearby shallow trench isolation structures.
Embodiments of this invention provide such an integrated circuit and method in which adjacent transistors defined by parallel gate electrodes sharing the same active region can be more precisely matched to one another.
Embodiments of this invention provide such an integrated circuit and method that is especially beneficial for transistors having deep sub-micron gate widths.
Embodiments of this invention provide such an integrated circuit and method that are compatible with direct-react silicidation of the source/drain regions and gate electrodes.
Other objects and advantages of embodiments of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
Embodiments of this invention may be implemented into an integrated circuit and method of forming the same, in which embedded SiGe structures are formed as the source and drain regions of one or more MOS transistors, for example one or more p-channel MOS transistors. Shallow trench isolation structures define one or more active regions in the integrated circuit. The SiGe material is disposed in recesses on either side of a gate electrode, and extend above the surface of the active region (i.e., from the interface between the silicon channel region and the overlying gate dielectric) by at least about 30% of the depth of the recess into the active region within which the SiGe structure is disposed. A cap layer of silicon may be formed over the SiGe structures for consumption in direct react silicidation; alternatively, additional SiGe beyond the at least about 30% overfill may be provided for consumption in silicidation.
In a regular array of transistors sharing a single active region, in which multiple parallel gate electrodes define matched transistors, the gate electrode closest to a parallel edge of a shallow trench isolation structure is separated from that edge by at least 150 Å to reduce the proximity effect of that isolation structure on the performance of the transistor.
Embodiments of the invention provide uniform transistor performance in a structure and fabrication method compatible with modern deep sub-micron transistor technology, and without inserting a significant chip area penalty.
a through 1d are cross-sectional views of a conventional metal-oxide-semiconductor (MOS) transistor at various stages of manufacture incorporating conventional embedded SiGe source/drain technology.
a and 2c are plan views, and
a and 3b are cross-sectional views, and
a through 4g are cross-sectional views of a MOS transistor at various stages of manufacture according to embodiments of the invention.
This invention will be described in connection with certain embodiments, namely as implemented into an integrated circuit fabricated according to a metal-oxide-semiconductor (MOS) technology as applied to planar p-channel MOS transistors formed in bulk silicon, as it is contemplated that this invention is especially beneficial in such an application. However, it is also contemplated that this invention may be used in other types of integrated circuits, including n-channel MOS transistors, complementary MOS (CMOS) integrated circuits, integrated circuits fabricated in silicon-on-insulator (SOI) structures, non-planar transistors, other types of field-effect transistors, and the like. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.
a and 3b illustrate, in cross-section, the construction of p-channel MOS transistor 20 according to an embodiment of this invention. As shown in
Transistor 20 is disposed in an active region of the surface of n-well 26 between shallow trench isolation structures 25 (or surrounded by a single such structure 25, depending on the larger-scale layout of the integrated circuit). For purposes of this description, the term “shallow trench isolation structure” refers to an element of dielectric material formed by deposition or the like into a recess etched into a surface of the semiconductor material at which transistors are to be formed; the term “shallow” is intended to convey that the isolation provided by the structure is the electrical isolation of the adjacent surface semiconductor regions on one side of the structure from semiconductor regions on the other side of the structure. Shallow trench isolation structures 25 thus do not necessarily isolate semiconductor structures formed deeper into the semiconductor material, such as buried collectors, diffusion-under-field (DUF) structures, and the like. Typically, shallow trench isolation structures 25 are formed of deposited silicon dioxide, but may alternatively be formed of other dielectric materials. Active regions, at which transistors such as transistor 20 of
Transistor 20 includes gate electrode 28, which in this embodiment of the invention is formed of p-type doped polycrystalline silicon material; alternatively, gate electrode 28 may be formed of a metal or conductive metal compound, such as titanium, tungsten, tantalum, titanium nitride, tantalum nitride, tungsten nitride, or the like. Gate electrode 28 overlies the surface of n-well 26, with gate dielectric 27 disposed therebetween. Gate dielectric 27 consists of a thin layer of a dielectric material such as silicon dioxide, silicon nitride, or a combination thereof; alternatively, gate dielectric 27 may be a “high-K” material such as HfO2 or the like. Sidewall hard mask spacers 31′ remain disposed on the sides of gate electrode 28, as will be described further below.
Transistor 20 includes embedded SiGe structures 32, which serve as the source and drain regions of the device. As discussed above, embedded SiGe structures 32 are disposed within recesses of n-well 26, and are constructed from a silicon-germanium alloy such as may be deposited by selective epitaxy. Typically, as known in the art, this alloy may include from as much as about 30% (atomic) to 50% (atomic) or more of germanium, resulting in SiGe structures 32 having a larger lattice constant than single-crystal silicon. As suggested by
According to embodiments of this invention, the SiGe alloy forming embedded SiGe structures 32 overfills the recesses in the semiconducting surface of n-well 26 by a significant amount, to such an extent that SiGe structures 32 extend above the surface of channel region 34, and also possibly that of shallow trench isolation structures 25.
Also as shown in
As known in the art, many integrated circuits increase the conductivity of semiconductor structures, such as source and drain regions and gate electrodes, by forming a metal silicide cladding at the surfaces of these structures. Typically, this silicide cladding is formed by way of direct react silicidation, in which a metal is deposited overall, and the structure subjected to a high temperature anneal to react the deposited metal with underlying silicon to form the metal silicide; a subsequent selective etch removes the unreacted metal from non-silicon structures (e.g., the surfaces of shallow trench isolation structures 25). SiGe structures 32 (and gate electrode 28) of transistor 20 of
Further in the alternative, a silicon “cap” layer formed over SiGe structures 32 during selective epitaxy may remain in place without silicidation. In this alternative also, SiGe structures 32 underlying such a “cap” layer will still extend above the surface reference point by at least about 30% of depth D.
It is believed, and has been observed, according to this invention that this overfill of SiGe alloy material greatly reduces the proximity effect of nearby shallow trench isolation structures 25 on the performance of transistor 20, specifically the proximity effect of structures 25 on the compressive strain applied by SiGe structures 32 to channel region 34. This reduction in the proximity effect has been observed as reduced degradation in transistor source/drain current for those transistors nearest to shallow trench isolation structures 25.
Referring back to
c illustrates an array of transistors 20 constructed according to embodiments of the invention. In this case, seven parallel gate electrodes 28 run across active region 35, which is defined as a portion of the semiconducting surface surrounded by shallow trench isolation structure 25 as described above. Gate electrodes 28 are spaced at regular intervals from one another, for photolithographic uniformity as discussed above. Dummy gate electrodes 28′ are disposed on both ends of this group of parallel gate electrodes 28, in this case disposed above shallow trench isolation structure 25, to maintain photolithographic regularity for the outer-most ones of active gate electrodes 28. SiGe structures 32 serve as the source and drain regions for these seven transistors, with each interior SiGe structure 32 serving as the source for one transistor and the drain for another. Contact locations 33 are shown in
Referring now to
The portion of the manufacturing flow shown in
In process 44, gate dielectric film 37 is then formed overall, either by thermal oxidation or nitridation of silicon, or by chemical vapor deposition, depending on the desired material and properties of the transistor gate dielectric. According to embodiments of this invention, gate elements 28 are formed and defined at the desired locations of transistors and dummy gate electrodes 28′, as the case may be, in process 45. For the example of a polysilicon gate structure, process 45 includes the deposition of polycrystalline silicon overall, followed by conventional photolithography and polysilicon etch. The photolithography of gate elements 28 may be performed in the conventional manner by the dispensing of photoresist overall, followed by conventional photolithographic patterning and developing, leaving photoresist mask elements at those locations of the polysilicon layer corresponding to gate electrodes 28, 28′. Etch of the polysilicon layer as protected by the patterned photoresist, also in process 45, then defines the gate element 28, as shown in
As shown in
Optional process 46 may then be performed if lightly-doped drain extensions are to be formed. If so, sidewall dielectric spacers will be formed in the conventional manner, by deposition of the desired dielectric material (e.g., silicon nitride) overall, followed by an anisotropic etch to remove the dielectric material from flat surfaces, leaving sidewall spacers on the side walls of gate electrode 28. A “halo” implant is then performed, typically as an angled implant so as to reach under the edges of gate electrode 28 (especially considering the yet-to-be-performed recess etch of the source/drain regions, described below), and establish the desired dopant profile. Following formation of the spacers and the halo implant, the sidewall spacers may be removed by an isotropic etch, or may remain in place.
In process 48, hard mask 31 is deposited as a layer overall, with the result as shown in
In either case (i.e., including or not including the LDD spacers), the sidewall hard mask spacers 31′ following etch process 50 will define the placement of eventual SiGe structures 32 from the channel of the transistor. As known in the art for SiGe source/drain structures, compressive strain on the transistor channel region is strongly affected by the distance of the SiGe material to the channel region underlying gate electrode 28. As such, it is desirable to precisely control the thickness of sidewall hard mask spacers 31′, as this thickness defines the edge of the recess to be etched into n-well 26 in this embodiment of the invention. As mentioned above, sidewall hard mask spacers 31′ may include the remaining sidewall spacers from optional LDD process 46; if so, those remaining LDD spacers will contribute to the spacing of the SiGe recesses from the edges of gate electrode 28.
In process 52, the structure is then subjected to a plasma etch to form recesses into n-well 26 at locations not protected by hard mask 31. The plasma conditions of etch process 52 may be selected to define the desired shape of the recesses etched into n-well 26. For example, as discussed above, a “diamond-shaped” recess edge is desirable for precise control of the compressive strain effect. It is contemplated that those skilled in the art can select the appropriate conditions of etch 52 suitable for forming recesses of the desired edge shape and profile. As shown in
It is contemplated that the depth of recesses 44 will generally be less than the thickness of adjacent isolation structures 25, for example on the order of one-fourth of that thickness (the depth of recesses 44 are somewhat exaggerated in
Selective epitaxy of a silicon-germanium alloy is then performed in process 54, to form embedded silicon-germanium (eSiGe) structures 45 as shown in
In optional process 56, a single crystal silicon cap layer is formed over SiGe structures 32 as a later stage of selective epitaxy process 54, by turning off the germanium-bearing source gas during epitaxy once the SiGe alloy is formed to the desired thickness. In one embodiment of the invention, this silicon cap layer over SiGe structures 32 has a thickness in range from about 50 to about 200 Å. This cap layer may remain in place in the finished integrated circuit, for example as a doped layer to which subsequent contact is made. Alternatively, this silicon cap resulting from process 56 may be used in the direct react silicidation of the structure, as described below.
P-type doping of SiGe structures 32 may be performed in situ during selective epitaxy process 54, if appropriate. Alternatively or in addition to that in situ doping, an additional source/drain implant is performed in process 58 to increase the dopant concentration of these eventual source/drain regions of transistor 20. Gate electrodes 28 may also be doped p-type at this time, to ensure proper transistor operation and good conductivity. In process 58, hard mask 31 is removed in the conventional manner, preferably by an anisotropic etch to maintain spacers 31′ if silicidation is to be performed. Process 58 may also include ion implantation of the appropriate dopant and dose of p-type donor species into SiGe structures 32 and the desired activation anneal of the implanted species to the desired junction depth and concentration profile. N-channel transistor regions of the integrated circuit will typically be protected from the p-type implant of process 58 by a photoresist or other mask. Following implant and anneal, p+ source and drain SiGe structures 32 are formed on opposite sides of gate element 28 in n-well 26.
As known in the art and as mentioned above, optional silicidation process 60 includes the deposition of a metal with which the silicide is to be formed, for example titanium, tungsten, tantalum, cobalt, and the like. After deposition of the metal layer, the structure is subjected to a high temperature anneal, also as part of process 60, to cause the deposited metal to react with such silicon (or SiGe) material with which it is in contact, to form a metal silicide compound that clads the underlying structure.
The structure of
In any case, regardless of whether silicon cap epitaxy process 58 or silicidation process 60 or both are performed, SiGe structures 32 in the resulting integrated circuit overfill the corresponding recesses 39 in n-well 26 to such an extent that the SiGe alloy material underlying any silicidation or cap layer, extends at least about 30% of the recess depth D above the surface of the structure, as measured at the interface between channel region 34 (i.e., the portion of n-well 26 directly underlying gate electrode 28) and gate dielectric 37. It has been observed, according to this invention, that this SiGe overfill serves to reduce the proximity effect of nearby shallow trench isolation structures 25 on the performance of transistors 20, ensuring that the mobility increase sought to be provided by SiGe strain engineering applies in a matched fashion to all transistors in the integrated circuit.
Additional reduction in this proximity effect can be further improved by spacing the edge of transistor gate electrodes 28 sufficiently from the nearest parallel edge of shallow trench isolation structures 25, particularly for the outermost transistors in a regular array of transistors.
As will be apparent to those skilled in the art having reference to this specification, it is contemplated that the method of fabricating transistors according to embodiments of this invention is quite compatible with modern MOS and CMOS manufacturing process flows, without involving significant added cost (e.g., additional photolithography steps).
While this invention has been described according to its embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.
