The present invention relates to a reliability design method for a semiconductor integrated circuit device including a semiconductor device and a metal interconnection.
In designing a semiconductor integrated circuit device, computer software designated as CAD (computer aided design) or EDA (electronic design automation) is conventionally used for automatically designing the semiconductor integrated circuit device. In designing a mask layout of an electronic circuit (a semiconductor device) included in the semiconductor integrated circuit device, a mask pattern manually designed or automatically designed by using a CAD tool is corrected through verification performed on the basis of a regulation corresponding to a fabrication limit designated as a design rule. Also, a regulation concerned with a product life is provided as a design rule to be used in design and verification in a similar manner.
In accordance with recent development of semiconductor integrated circuit devices, it is necessary to design a semiconductor integrated circuit with high reliability in its life (aging). Physical phenomenon typically concerned with the life of a semiconductor integrated circuit device is electric characteristic degradation due to a hot carrier effect or an antenna effect and physical characteristic degradation due to electro-migration or stress-migration. In order to suppress such degradation, some examples of an apparatus, designated as a reliability design apparatus, that grasps change of the electric characteristic through the aging and analyzes the reliability for optimizing the design of a semiconductor integrated circuit have been proposed as disclosed in, for example, Japanese Laid-Open Patent Publication No. 2003-224258. Such a reliability design apparatus is a reliability design system for a semiconductor integrated circuit device in which reliability design for satisfying the performance concerned with the electric characteristic life required of the semiconductor integrated circuit device can be efficiently performed.
Although a reliability design technique for suppressing the electric characteristic degradation due to the hot carrier effect or the antenna effect that affects the performance of a semiconductor device has been conventionally proposed, a reliability design technique for suppressing the physical characteristic degradation concerned with the product life that depends upon a mask layout has not been proposed. Accordingly, in order to improve the reliability of the performance affecting the product life, fabrication regulation for a semiconductor integrated circuit device designated as a design rule depending upon a mask layout has been employed for the design. In such a conventional design method, however, it is difficult to minimize increase of a chip area or to reduce variation depending upon a mask layout simultaneously with the reliability design.
In consideration of this conventional disadvantage, an object of the invention is providing a reliability design method in which a highly reliable semiconductor integrated circuit device having satisfactory performance concerned with its life can be efficiently designed with characteristic degradation through the aging suppressed.
In order to achieve the object, the first reliability design method of this invention in which it is confirmed that a semiconductor integrated circuit device to be designed has a predetermined desired life, includes at least an aged deterioration target extracting step of obtaining aging derived from a shape of a mask layout pattern of every semiconductor device and every metal interconnection included in the semiconductor integrated circuit device; an aged deterioration executing step of calculating a degree of influence on the whole semiconductor integrated circuit device with the obtained aging input; and an aged deterioration characteristic checking step of calculating an electric characteristic of the semiconductor integrated circuit device resulting from the aging with the calculated degree of influence input.
In this reliability design method, not only the initial characteristic of the semiconductor integrated circuit device but also the characteristic of the semiconductor integrated circuit device resulting from the aging are evaluated, and hence, the performance concerned with the product life can be evaluated. Therefore, highly reliable design for attaining a desired life of the semiconductor integrated circuit device can be performed. Furthermore, since the degree of influence on the semiconductor integrated circuit device and the electric characteristic resulting from the aging are calculated, in the case where some parts of, for example, the semiconductor device or the metal interconnection have sufficient reliability also after aged deterioration, the chip area can be reduced while retaining the performance concerned with the life. Therefore, when the reliability design method of this invention is employed, a semiconductor integrated circuit device with high reliability sufficiently satisfying the performance concerned with the life can be designed while suppressing the increase of the chip area.
Furthermore, the second reliability design method of this invention for providing a semiconductor integrated circuit device to be designed with a predetermined desired life, includes an aged deterioration correcting step of preventing reduction of a life through aging by correcting a mask layout pattern of every semiconductor device and every metal interconnection included in the semiconductor integrated circuit device for attaining the predetermined desired life.
In this reliability design method, the mask layout pattern can be corrected by, for example, increasing the width of a metal interconnection in a portion where disconnection is easily caused through the aged deterioration. Therefore, since occurrence of disconnection or the like is reduced, the reduction of the life derived from the aged deterioration is suppressed, and hence, a semiconductor integrated circuit device with a desired life can be designed.
The third reliability design method of this invention in which it is confirmed that a semiconductor integrated circuit device to be designed has a predetermined desired life, includes at least an aged deterioration target extracting step of obtaining aging derived from a shape of a mask layout pattern of every semiconductor device and every metal interconnection included in the semiconductor integrated circuit device; an aged deterioration executing step of calculating a degree of influence on the whole semiconductor integrated circuit device with the obtained aging input; an aged deterioration characteristic checking step of calculating an electric characteristic of the semiconductor integrated circuit device resulting from the aging with the calculated degree of influence input; and an aged deterioration correcting step of preventing reduction of a life through the aging by correcting the mask layout pattern.
In this reliability design method, since the characteristic of the semiconductor integrated circuit device resulting from the aged deterioration is evaluated in the same manner as in the first reliability design method, the performance concerned with the product life can be evaluated. Therefore, a semiconductor integrated circuit device with a desired life can be designed with high reliability. Furthermore, since the mask layout pattern is corrected, it is possible to realize a highly reliable semiconductor integrated circuit device with the reduction of the life through the aged deterioration definitely suppressed.
The fourth reliability design method of this invention includes at least a data inputting step of reading a mask layout pattern corresponding to design information resulting from aging of a semiconductor integrated circuit device to be designed; a characteristic checking step of extracting a characteristic of every semiconductor device and every metal interconnection of the semiconductor integrated circuit device and checking whether or not a predetermined desired life is attained by the extracted characteristic; and an aged deterioration correcting step of complementing aged deterioration in a part of the mask layout pattern where the predetermined desired life is not attained.
In this reliability design method, the characteristic of every semiconductor device or the like is checked by using a CAD tool for DRC or the like on the basis of the mask layout pattern corresponding to design information of the semiconductor integrated circuit device resulting from the aged deterioration. Therefore, the performance concerned with the product life can be evaluated. Furthermore, in the aged deterioration correcting step, a part of the mask layout pattern where the predetermined desired life is not attained can be complemented. Accordingly, when the fourth reliability design method of this invention is employed, a semiconductor integrated circuit device having satisfactory performance concerned with the life can be efficiently designed.
A preferred embodiment of the invention will now be described in detail with reference to the accompanying drawings.
A reliability design method for a semiconductor integrated circuit device including a semiconductor device and a metal interconnection according to an embodiment of the invention will be first described.
As shown in
First, in the aged deterioration target extracting step 20, a target part can be specified and extracted by checking the initial mask layout pattern 10 through DRC (design rule check) performed on the basis of a regulation according to a design rule. Alternatively, a target part can be specified and extracted through lithography rule check (LRC) for reproducing a pattern to be formed on a silicon wafer. It is noted that procedures performed in the steps described below are also executed by using a DRC tool, an LRC tool or the like included in hardware means of a computer or the like in the same manner as this procedure.
Next, in the aged deterioration executing step 30, the target part specified in the initial mask layout patter 10 on the basis of the regulation according to the design rule in the aged deterioration target extracting step 20 is modified, so as to create a deteriorated mask layout pattern 40 corresponding to a semiconductor device or a metal interconnection resulting from the aging. At this point, the deteriorated mask layout pattern 40 is a mask layout pattern obtained by modifying the initial mask layout pattern 10 and hence has the same structure as the initial mask layout pattern 10 excluding the target part.
Subsequently, the aged deterioration coping step 50 will be described.
Next, the reliability design method for a semiconductor integrated circuit device including a semiconductor device and a metal interconnection according to this embodiment will be described by giving specific examples. First, specific examples of the aged deterioration executing step 30 of
The metal interconnections of the semiconductor integrated circuit device corresponding to the initial mask layout pattern 10 shown in
First, it is determined on the basis of the initial mask layout pattern 10 of
Next, in the aged deterioration executing step 30 of this embodiment, the target part specified in the aged deterioration target extracting step 20 is modified on the basis of the design rule as shown in
First, in the aged deterioration target extracting step 20 of this example, a first region 621 of a second second-layer metal interconnection 622 is extracted as a target part from the initial layout pattern of
Next, in the aged deterioration executing step 30 of this example, the first region 621 of the second second-layer metal interconnection 622 extracted as the target part is modified as shown in
Although one second connection via 620 is removed in
First, the metal interconnections included in the initial mask layout pattern 10 of
In the aged deterioration target extracting step 20 of this example, the first region 711 of the first second-layer metal interconnection 712 and the third region 721 of the second second-layer metal interconnection 722 are extracted as target parts from the initial mask layout pattern of
Next, in the aged deterioration executing step 30, the width of the third region 721 of the second second-layer metal interconnection 722 extracted as the target part in the aged deterioration target extracting step 20 is reduced, thereby forming a seventh region 771 as shown in
First, in the aged deterioration target extracting step 20 of this example, a first connection via 810 for connecting a first second-layer metal interconnection 812 to a first-layer metal interconnection 800 and a second connection via 820 for connecting a second second-layer metal interconnection 822 to the first-layer metal interconnection 800 are extracted as target parts from the initial mask layout pattern of
Subsequently, in the aged deterioration executing step 30, the number of second connection vias 820 extracted as the target part in the aged deterioration target extracting step 20 is reduced from one to zero. Thus, a deteriorated mask layout pattern 40 indicating a risk of the disconnection of the second connection vias 820 and including no connection via for connecting the first-layer metal interconnection 800 to the second second-layer metal interconnection 822 (see a via removal part 870) can be created.
First, in the aged deterioration target extracting step 20 of this embodiment, a first connection via 910 for connecting a first second-layer metal interconnection 912 to a first-layer metal interconnection 900 and a second connection via 920 for connecting a second second-layer metal interconnection 922 to the fist-layer metal interconnection 900 are extracted as target parts on the basis of the shape of the initial layout pattern shown in
Next, in the aged deterioration executing step 30, the number of second connection vias 920 extracted as the target part in the aged deterioration target extracting step 20 is reduced from one to 0.5. Thus, the second connection via 920 is modified into a fourth connection via 970 having an area in the cross-section along a direction parallel to the metal interconnection halved as compared with the second connection via 920, and in this manner, a deteriorated mask layout pattern 40 indicating a risk of the disconnection of the metal interconnection can be created. In this case, since the number of second connection vias included in the deteriorated mask layout pattern 40 is expressed with a positive real number, the deteriorated mask layout pattern 40 can be created constantly on the basis of the probability previously calculated in the aged deterioration target extracting step 20.
Next, specific examples of the aged deterioration coping step 50 will be described with reference to
First, a deteriorated mask layout pattern 40 is created by extracting a target part where there is much possibility of the aging from the initial mask layout pattern shown in
Next, in the aged deterioration coping step 50, circuit information of every semiconductor device and every metal interconnection is extracted from the deteriorated mask layout pattern 40, and it is determined through, for example, circuit simulation, whether or not an initially designed characteristic can be retained. In the case where it is determined that the initially designed characteristic cannot be retained, the first region 221 of the second second-layer metal interconnection 222 is corrected as shown in
First, a deteriorated mask layout pattern 40 is created by extracting a target part where there is much possibility of the aging from the initial mask layout pattern shown in
Next, in the aged deterioration coping step 50, circuit information of every semiconductor device and every metal interconnection is extracted from the deteriorated mask layout pattern 40, and it is determined through, for example, the circuit simulation, whether or not an initially designed characteristic can be retained. In the case where it is determined that the initially designed characteristic cannot be retained, a corrected mask layout pattern 90 (see
First, a deteriorated mask layout pattern 40 is created by extracting a target part where there is much possibility of the aging from the initial mask layout pattern shown in
Next, in the aged deterioration coping step 50, circuit information of every semiconductor device and every metal interconnection is extracted from the deteriorated mask layout pattern 40, and it is determined through, for example, the circuit simulation, whether or not an initially designed characteristic can be retained. In the case where it is determined that the initially designed characteristic cannot be retained, a second connection via 420 for connecting the first region 421 to a first-layer metal interconnection 400 is modified, on the basis of the initial mask layout pattern of
As described so far, in the reliability design method of this embodiment, not only the characteristic of a semiconductor integrated circuit device having a structure corresponding to an initial mask layout pattern but also the characteristic of the semiconductor integrated circuit device having a structure corresponding to a deteriorated mask layout pattern resulting from the aging are evaluated, so that a semiconductor integrated circuit device with high reliability in performance concerned with the product life can be designed. In the case where a metal interconnection and a via are designed in consideration of, for example, the electro-migration, it is difficult to obtain a semiconductor integrated circuit device with a desired life merely by using an initial mask layout pattern. Therefore, a deteriorated mask layout pattern resulting from the aging is used, so as to evaluate not only the electro-migration but also other performance concerned with the product life such as the stress-migration, and thus, highly reliable design can be executed for attaining a desired life of the semiconductor integrated circuit device.
Furthermore, since the characteristic is evaluated by using the deteriorated mask layout pattern, in the case where some parts of, for example, a semiconductor device or a metal interconnection have sufficient reliability also after the aged deterioration, the chip area can be reduced while retaining the performance concerned with the life. Therefore, when the reliability design method of this embodiment is employed, a semiconductor integrated circuit device with high reliability sufficiently satisfying the performance concerned with the life can be designed while suppressing the increase of the chip area.
Moreover, since the procedures of the aged deterioration target extracting step 20, the aged deterioration executing step 30 and the aged deterioration coping step 50 are performed by using a CAD tool for the DRC or the like in the reliability design method of this invention, the design procedures can be automatically executed. Therefore, the time and labor necessary for the design of a mask layout pattern can be reduced, so that the reliability design can be efficiently performed.
In this manner, the reliability design method for a semiconductor integrated circuit device of this invention is useful for improving the efficiency of the reliability design of semiconductor integrated circuit devices.
Number | Date | Country | Kind |
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2007-045989 | Feb 2007 | JP | national |