Patent Application
20100182147
Phase-change memory (also known as PCM, PRAM, PCRAM, Chalcogenide RAM and C-RAM) is a type of non-volatile memory device that employs a reversible phase-change material to store information.
Phase-change memory uses a medium called chalcogenide, the physical state of which can be reversibly changed between crystalline and amorphous through the application of heat. The physical states have different electrical resistance properties that can be easily measured, making chalcogenide useful for data storage.
In the amorphous phase, the material is highly disordered, that is, there is an absence of regular order to the crystalline lattice. In this phase, the material demonstrates high resistivity and high reflectivity. In contrast, in the crystalline phase, the material has a regular crystalline structure and exhibits low reflectivity and low resistivity.
Phase-change memory uses electrical current to trigger the structural change. An electrical charge just a few nanoseconds in duration melts the chalcogenide in a given location; when the charge ends, the location's temperature drops so quickly that the disorganized atoms freeze in place before they can rearrange themselves back into their regular, crystalline order.
Going in the other direction, the process applies a longer, less-intense current that warms the amorphous patch without melting it. This energizes the atoms just enough that they rearrange themselves into a crystalline lattice, which is characterized by lower energy or electrical resistance.
To read recorded information, a probe measures the electrical resistance of the location. The amorphous state's high resistance is read as a binary 0; the lower-resistance, crystalline state is a 1.
Security circuit 100 functions to protect security-relevant data stored on the chip against unauthorized access, and to prevent manipulation of the chip's method of operation. Unauthorized data access and/or operation manipulation has been accomplished using many different methods, as will be discussed below.
Security circuit 100 includes a central alarm handler 110, which may be, for example, a processor. A plurality of sensors 122, 124, 126, 128 are coupled to, but located remotely from, central alarm handler 110. More specifically, sensor 122 is coupled to central alarm handler 110 via conductive line 142, sensor 124 is coupled to central alarm handler 110 via conductive line 144, sensor 126 via conductive line 146, and sensor 128 via conductive line 148.
Each of sensors 122, 124, 126, 128 may be a light sensor configured to detect light attacks, a temperature sensor configured to detect temperature attacks, a voltage sensor configured to detect glitch attacks, or any other sensor suitable for detecting an attack used to access data stored on the chip or manipulate chip operation. When a sensor 122, 124, 126, 128 senses that its condition, that is light, temperature, voltage, etc., becomes out of range, such as exceeding a predetermined threshold, the sensor thereby senses an attack.
Light attacks may include, for example, irradiating the chip with X-rays to erase targeted memory areas and to reset codes, X-raying the chip in order to analyze its construction, optically reading ROM memory components, or exposing the chip to UV light in order to bring the micro-controller into an undefined state.
Temperature attacks may include, for example, heating a chip to randomly modify cells to exploit the fact that read and write temperature thresholds do not coincide in most non-volatile memories. By tuning a chip temperature to a value where write operations work but reads do not, or visa versa, a number of attacks can be mounted.
Glitch attacks may include, for example, changing the operating voltage or using voltage spikes to bring a microcontroller of the chip into an undefined state, over-clocking the chip, scanning signals present on corresponding chip circuits with the help of contact pins and subsequent analysis of those signals.
A plurality of phase-change memories 132, 134, 136, 138 are respectively coupled to and located remotely with sensors 122, 124, 126, 128. In one embodiment, phase-change memory cells 132, 134, 136, 138 are respectively coupled on top of sensors 122, 124, 126, 128.
When a sensor 122, 124, 126, 128 senses an attack, an alarm event is stored in the respective phase-change memory 132, 134, 136, 138. The alarm event is stored by applying an electrical current to the chalcogenide material of the phase-change memory 132, 134, 136, 138, thereby changing its resistance, as discussed above.
A phase-change memory cell 132, 134, 136, 138 can store the alarm event as a flag. In an alternative embodiment, phase-change memory 132, 134, 136, 138 stores the alarm event as an alarm count value indicating a number of times an attack is sensed by a respective sensor 122, 124, 126, 128. By storing an alarm count value rather than simply a flag, central alarm handler 110 may be designed to trigger an alarm action only when the alarm count value exceeds a predetermined alarm count value. The predetermined alarm count value may be stored in central alarm handler 110 or a separate memory device, and may be any value considered suitable. Of course this alarm count value could be zero, thereby triggering an alarm action each time an attack is sensed. However, there is a trade-off between security and performance; the more alarm actions are triggered, the more performance is sacrificed.
A phase-change memory cell 132, 134, 136, 138 may store an alarm event in either a digital or an analog manner. In a digital manner, there is one phase-change memory cell 132, 134, 136, 138 for each data bit, and each cell is turned on or off to represent a logical “1” or a logical “0”.
When storing the alarm event in an analog manner, only a single phase-change memory cell 132, 134, 136, 138 is required for a respective sensor 122, 124, 126, 128. The resistance of the chalcogenide material of the cell changes each time an electrical current is applied, or the resistance may be in proportion to the strength of the applied electrical current. As long as there is no clearing or erasing of the stored data, the resistance of the chalcogenide material generally will be further increased each time an electrical current is applied thereto. Since the resistance corresponds with the stored value, phase-change memory cells can act as an adder to increase the alarm count value. Since only a single cell is needed, analog storage is more area efficient than digital storage.
Phase-change memories 132, 134, 136, 138 are located remotely with sensors 122, 124, 126, 128, and thus alarm events are stored locally, as opposed to being stored centrally in central alarm handler 110. Central alarm handler 110 reads phase-change memories 132, 134, 136, 138 and may take any appropriate alarm action if necessary, such as a chip reset, disable, or shutdown. Central alarm handler 110 reads the local phase-change memories 132, 134, 136, 138 at startup in order to determine if a local attack occurred anywhere in the chip. In an alternative embodiment, central alarm handler 110 reads the local phase-change memories 132, 134, 136, 138 periodically, or at any time deemed appropriate. Further, central alarm handler 110 can read any one, or more of the local phase-change memories 132, 134, 136, 138 at any time.
While
Under the security method, first an attack is sensed by one or more sensors 122, 124, 126, 128, located remotely from central alarm handler 110. (Step 210.) Using a light sensor as an example, a light attack may be sensed when the sensor senses that a light intensity is out of an expected range, such as when the light intensity exceeds a predetermined light intensity threshold, thereby indicating an attack.
When an attack is sensed by a sensor 122, 124, 126, 128, an alarm event is stored in a phase-change memory cell 132, 134, 136, 138 coupled to and located remotely with the respective sensor 122, 124, 126, 128, such as by increasing a stored alarm count value. (Step 220.) The alarm count value therefore represents the number of times an attack is sensed by the particular sensor 122, 124, 126, 128. Again, the phase-change memory cell 132, 134, 136, 138 may store the alarm count value in analog or digital format.
Central alarm handler 110 reads the stored alarm count values in the phase-change memory cell 132, 134, 136, 138. (Step 230.) Central alarm handler 110 can read phase-change memory cell 132, 134, 136, 138 at startup to determine whether there has been a local attack on the chip. Alternatively, central alarm handler can read the stored alarm count value in phase-change memory cell 132, 134, 136, 138 periodically or any time deemed appropriate. When the alarm count value exceeds a predetermined alarm count value, central alarm handler 110 performs an alarm action. (Step 240.) The alarm action can be a chip shut down, a clearing of all security data, a security check, or any other responsive action considered appropriate.
At some point, such as after the alarm action is performed, the stored alarm count value is reset, so that circuit 100 is not continuously in an alarm condition. As discussed above, the count value may be reset by applying a longer, less-intense current that warms the chalcogenide material of the cell without melting it. This energizes the atoms just enough that they rearrange themselves into a crystalline lattice, which is characterized by lower energy or electrical resistance. The cell is then read as a binary 0.
There are many advantages to including local phase-change memory cells 132, 134, 136, 138 at sensors 122, 124, 126, 128 to store alarm events. For example, the alarm event is stored in a non-volatile manner and is therefore present even if an attacker switches off the power to security circuit 100 when the sensor triggers an alarm.
Also, the alarm event information is available locally and does not rely on central alarm handler 110. Thus if an attacker disables central alarm handler 110, an alarm response, such as a security reset, can still occur.
Circuit 300 includes central processing unit (CPU) 310, memory 320, subcircuits 332, 334, 336, 338, each coupled to system bus 350, and phase-change memory cells 342, 344, 346, 348. More specifically, CPU 310 is coupled to system bus 350 via conductive line 353, memory 320 is coupled to system bus 350 via conductive line 355, and subcircuits 332, 334, 336, 338 are coupled to system bus via conductive lines 352, 354, 356, 358, respectively.
Phase-change memory cells 342, 344, 346, 348 are respectively coupled to and located remotely with subcircuits 332, 334, 336, 338. In one embodiment, phase-change memory cells 342, 344, 346, 348 are respectively located on top of subcircuits 332, 334, 336, 338.
Phase-change memory cells 342, 344, 346, 348 are configured to store configuration data that would otherwise be hosted in special function registers (SFR). This configuration data is therefore available locally to subcircuits 332, 334, 336, 338, and CPU 310 does not need to transfer the configuration data from memory 320 to SFRs during startup.
Phase-change memory cells 342, 344, 346, 348 may store configuration data in a digital manner. More specifically, one phase-change memory cell 342, 344, 346, 348 corresponds to a single data bit, and each cell is turned on or off to represent a logical “1” or a logical “0”. If there are 16 bits of configuration data, there are 16 phase-change memory cells 342, 344, 346, 348, with electrical currents causing the respective cells to store either a logical “1” or a logical “0”.
Alternatively, phase-change memory cells 342, 344, 346, 348 may store configuration data in an analog manner. As discussed above, only a single cell is needed, with the resistance of the cell changing each time an electrical current is applied or generally in proportion to the strength of the electrical current.
Also, the configuration data from each of phase-change memory cells 342, 344, 346, 348 may be loaded into the respective subcircuits 332, 334, 336, 338 in parallel. Conventionally, values are read in a serial manner, that is, at startup a CPU reads a first value and writes it into a first special function register, then subsequently reads a second value and writes it into a second special function register, etc. Now, with the local, non-volatile storage of configuration data in phase-change memory cells 342, 344, 346, 348, the configuration data in each of phase-change memory cells 342, 344, 346, 348 can be loaded into respective subcircuits 332, 334, 336, 338 in parallel (i.e., concurrently) without using CPU 310 that couples memory 320 with subcircuits 332, 334, 336, 338. Startup time is effectively reduced. Additionally, a transfer of the configuration data through the circuit 300 is avoided, thereby reducing an opportunity for an attacker to listen to or manipulate the configuration data during such transfer.
Further, with the local, non-volatile storage of configuration data in phase-change memory cells 342, 344, 346, 348, centralized storage of the configuration data for the circuit is not needed, and the configuration data is present at subcircuits 332, 334, 336, 338 even after a power down.
Subcircuit 332, 344, 346, 348 may be any type of logic requiring configuration data during startup or any other time. In one embodiment, subcircuit 332, 344, 346, 348 is a random number generator. In such a case, the corresponding phase-change memory cell 342, 344, 346, 348 is configured to store a seed for the random number generator locally such that it is available immediately during start-up. Further, any time there is a power up the seed can be changed. At the next power up there is a new seed, even if there were several system power-downs in between.
In another embodiment, subcircuit 332, 344, 346, 348 is an analog subcircuit. In such a case, the corresponding phase-change memory cell 342, 344, 346, 348 is configured to store adjustment values locally in a non-volatile manner. This enables stable operation without any system interaction, such as loading a SFR value from memory 320.
In another embodiment, subcircuit 332, 344, 346, 348 is a communication subcircuit. In such a case, the corresponding phase-change memory cell 342, 344, 346, 348 is configured to act as a buffer. Since the phase-change memory cell 342, 344, 346, 348 is placed on top of the communication subcircuit, the subcircuit area is minimized.
Alternatively, in another embodiment, subcircuit 332, 344, 346, 348 is an encryption unit. In such a case, the corresponding phase-change memory cell 342, 344, 346, 348 is configured to store keys locally. There is therefore no need to transfer the key through circuit 300 during start-up.
While
A subcircuit 332, 334, 336, 338 is provided remotely from CPU 310. (Step 410.) A phase-change memory cell 342, 344, 346, 348 is provided to be coupled to and located remotely with subcircuit 332, 334, 336, 338. (Step 420.) Configuration data is stored in phase-change memory cell 342, 344, 346, 348. (Step 430.) As discussed above, the configuration data can be stored in either analog or digital format. At startup, the configuration data is provided from phase-change memory cell 342, 344, 346, 348 to subcircuit 332, 334, 336, 338. (Step 440.)
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present application. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein.
