BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing a conventional reordering control operation;
FIG. 2 is a principle diagram of a reordering apparatus according to the present invention;
FIG. 3 is a diagram showing a first bit matrix;
FIG. 4 is a diagram showing a second bit matrix;
FIG. 5 is a diagram showing a third bit matrix;
FIG. 6 is a diagram showing a fourth bit matrix;
FIG. 7 is a diagram showing a fifth bit matrix;
FIG. 8 is a diagram showing a sixth bit matrix;
FIG. 9 is a diagram showing initial values of the bit matrix;
FIG. 10 is a block diagram of a microprocessor;
FIG. 11A is a block diagram (1) of a reordering circuit;
FIG. 11B is a block diagram (2) of the reordering circuit;
FIG. 12 is a block diagram of a communication LSI; and
FIG. 13 is a block diagram of a parallel computer.