1. Field of the Invention
The invention relates to a memory device, and more particularly to a resistive memory device.
2. Description of the Related Art
Generally, there are two kinds of computer memory: non-volatile memory and volatile memory. Non-volatile memory comprises Read-only memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM) and flash memory. Volatile memory comprises Dynamic Random Access Memory (DRAM) and Static Random-Access Memory (SRAM).
New kinds of volatile memory comprise ferroelectric memory, Phase-change memory, Magnetoresistive Random Access Memory (MRAM) and Resistive Random Access Memory (RRAM). The RRAMs are widely used as they possess such favorable advantages as having a simple structure, low cost, high speed and low power consumption.
In accordance with an embodiment, a resistive memory device comprises a first cell, a second cell and a control circuit. The first cell is coupled to a word line, a first bit line and a source line. The second cell is coupled to the word line, a second bit line and the source line. The control circuit controls the levels of the word line, the first bit line and the source line to execute a set operation for the first cell such that the first cell has a first resistance. The control circuit controls the levels of the word line, the second bit line and the source line to execute a reset operation for the second cell such that the second cell has a second resistance that is greater than the first resistance. During the execution of the set operation, the control circuit asserts the level of the source line at a pre-determined level. During the execution of the reset operation, the control circuit asserts the level of the source line at the pre-determined level.
An exemplary embodiment of a control method for a resistive memory device comprising a first cell and a second cell is described in the following. The first cell is coupled to a word line, a first bit line and a source line. The second cell is coupled to the word line, a second bit line and the source line. A set operation is executed such that the first cell has a first resistance. The set operation provides a pre-determined level to the source line. A reset operation is executed such that the second cell has a second resistance higher than the first resistance. The reset operation is to provide the pre-determined level to the source line.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The control circuit 120 controls the levels of the word lines WL<0>˜WL<M>, bit lines BL<0>˜BL<N> and source lines SL<0>˜SL<M> to access the cells M00˜MMN. For example, in a write mode, the control circuit 120 executes a set operation or a reset operation for the cells M00˜MMN to write data into the cells M00˜MMN, and in a read mode, the control circuit 120 executes a verify operation for the cells M00˜MMN to read the data stored in the cells M00˜MMN.
For example, after the control circuit 120 executes the set operation for a first specific cell, the first specific cell has a low resistance, which means that the data stored in the first specific cell is 0. After the reset operation, a second specific cell has a high resistance. This means that the data stored in the second specific cell is 1. Therefore, the control circuit 120 obtains the data stored in the cells M00˜MMN according to the resistances of the cells M00˜MMN.
In this embodiment, during the executions of the set, reset and verify operations, the control circuit 120 maintains the level of each of the source lines SL<0>˜SL<M> at a pre-determined level. Since the levels of the source lines SL<0>˜SL<M> are fixed at the pre-determined level, the control circuit 120 does not need to change the levels of the source lines SL<0>˜SL<M>. Therefore, the write time when the control circuit 120 writes data into the cells M00˜MMN, is reduced.
In another embodiment, the control circuit 120 simultaneously executes the set and reset operations. For example, the control circuit 120 executes the set operation for the cell M00, meanwhile, the control circuit 120 executes the reset operation for the cell M01. In other embodiments, the control circuit 120 first executes the set operation for the cells M00˜MMN and then executes the reset operation for the cells M00˜MMN.
In this embodiment, the control circuit 120 comprises a row decoder 121, a column decoder 122, a write buffer 123, a level controller 124 and a sensing amplifying unit 125, but the disclosure is not limited thereto. Any circuit structure can serve as the control circuit 120, as long as the circuit structure is capable of controlling the levels of the word lines WL<0>˜WL<M>, the bit lines BL<0>˜BL<N> and the source lines SL<0>˜SL<M>.
The row decoder 121 is coupled to the word lines WL<0>˜WL<M>, decodes the input address AW and turns on at least one word line according to the decoded result. The column decoder 122 is coupled to the bit lines BL<0>˜BL<N>, decodes the input address AB and turns on at least one bit line according to the decoded result. The write buffer 123 writes the input data DA to at least one cell.
The level controller 124 is coupled to the source lines SL<0>˜SL<M> to control the levels of the source lines SL<0>˜SL<M>. In this embodiment, each of the source lines SL<O>˜SL<M> is coupled to the same level controller 124. The invention does not limit the connection relationship between each of the source lines SL<O>˜SL<M> and the level controller. In another embodiment, the source lines SL<O>˜SL<M> are coupled to each other and then coupled to a level controller. In some embodiments, the source lines SL<O>˜SL<M> are divided into various group. Each group is coupled to a corresponding level controller.
The sensing amplifying unit 125 verifies the data stored in the cells M00˜MMN and outputs the data by a parallel-out method or a serial-out method. The invention does not limit how the sensing amplifying unit 125 verifies the cells M00˜MMN. In one embodiment, the sensing amplifying unit 125 utilizes a complement sensing method to verify the data stored in the cells. In this case, each cell comprises a first sub-cell and a second sub-cell. The resistance of the first sub-cell is complemented with the resistance of the second sub-cell. In one embodiment, when the first sub-cell has a low resistance and the second sub-cell has a high resistance, it means that the data stored in the cell is 0. When the first sub-cell has a high resistance and the second sub-cell has a low resistance, it means that the data stored in the cell is 1. Therefore, the data stored in the cell can be identified according to the resistances of the first and second sub-cells.
In another embodiment, the sensing amplifying unit 125 utilizes a reference sensing method to identify the data stored in the cells. In this case, the sensing amplifying unit 125 compares each resistance with a reference resistance and identifies the data stored in the cells according to the compared result.
As shown in
When the word line WL<0> is at a turn-on level VON1, the transistors T00˜T03 of the cells M00˜M03 are turned on. Since the word line WL<1> is at a turn-off level VOFF1, the transistors T10˜T13 of the cells M10˜M13 are turned off. In one embodiment, the turn-off level VOFF1 is a ground level.
In this embodiment, each of the source lines SL<0> and SL<1> is at a pre-determined level VSL. The bit line BL<0> is at a setting level VSET1 and the setting level VSET1 is higher than the pre-determined level VSL. Therefore, a current path 310 is formed in the cell M00. Since the current in the current path 310 flows from the variable resistor R00 to the transistor T00, a set operation is executed for the cell M00. After the set operation, the variable resistor R00 has a low resistance. In one embodiment, the data stored in the cell M00 is 0.
In this embodiment, the bit line BL<1> is at the pre-determined level VSL. Since the level of the bit line BL<1> is the same as the level of the source line SL<0>, no current path is formed in the cell M01. Therefore, the set operation and the reset operation are not executed for the cell M01. In other embodiments, if there is no need to execute the set or the reset operation for some cells, the levels of the bit lines coupled to those cells are the same as the levels of the source lines coupled to those cells.
Each of the bit lines BL<2>˜BL<3> is at a reset level VRESET1. In this embodiment, since the reset level VRESET1 is less than the pre-determined level VSL, current paths 320 and 330 are formed in the cells M02 and M03. The current in the current path 320 flows from the transistor T02 to the variable resistor R02, the reset operation is executed for the cell M02. Similarly, the reset operation is also executed for the cell M03. After the reset operation, each of the variable resistors R02 and R03 has a high resistance. In this embodiment, the data stored in the cells M02 and M03 are 1.
The invention does not limit the extent of the pre-determined level VSL. In this embodiment, the pre-determined level VSL is between the setting level VSET1 and the reset level VRESET1, and the setting level VSET1 is higher than the reset level VRESET1. In one embodiment, the reset level VRESET1 is ground level. In this case, no negative level is generated. Therefore, the complexity of the resistive memory device is reduced.
In this embodiment, during the executions of the set and the reset operations, the level of the source line SL<0> is maintained at the pre-determined level VSL. Furthermore, since the set and the reset operations are executed simultaneously, the write time of the cell array 110 is reduced.
Since the level of the word line WL<l> is a turn-off level VOFF2, the transistors T10˜T13 in the cells M10˜M13 are turned off. In one embodiment, the turn-off level VOFF2 is equal to the reset level VRESET2. In another embodiment, the turn-off level VOFF2 is less than the turn-off level VOFF1. In some embodiments, the turn-on level VON2, the setting level VSET2, and the reset level VRESET2 in
A set operation is executed (step S510). Assume that the set operation is executed for the first cell. In one embodiment, a turn-on level is provided to the word line, a setting level is provided to the first bit line, and a pre-determined level is provided to the source line. After executing the set operation, the first cell has a first resistance, such as a low resistance.
A reset operation is executed (step S520). Assume that the reset operation is executed for the second cell. In one embodiment, the turn-on level is provided to the word line, a reset level is provided to the second bit line and the pre-determined level is provided to the source line. In this case, after executing the reset operation, the second cell has a second resistance, such as a high resistance. During the executions of the set and the reset operations, the same level is provided to the source line. Therefore, the level of the source line does not need to be adjusted, and the write time of the resistive memory device is reduced.
In one embodiment, steps S510 and S520 are simultaneously executed. In another embodiment, the reset level is less than the setting level. In this embodiment, the pre-determined level is between the setting level and the reset level. In one embodiment, the reset level is a ground level.
In another embodiment, the pre-determined level is the ground level. In this case, the reset level is a negative level. In some embodiments, if a specific cell does not need to be set or reset, the pre-determined level is provided to the corresponding bit line coupled to the specific cell. In one embodiment, the specific cell is disposed between the first and the second cells.
In some embodiments, during the verify operation, the turn-on level is provided to the word line, a read level is provided to the first and the second bit lines and a pre-determined level is provided to the source line to detect the resistances of the cells. In one embodiment, the read level is higher than the pre-determined level, but the disclosure is not limited thereto. When the verify operation is executed, the same pre-determined level is provided to the source line. Therefore, the level of the source line does not need to be adjusted, the read time of the resistive memory device is reduced.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.